Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3568	1			T146	1		T222	8		T510	15
all_values[1]	3638	1			T146	2		T222	3		T510	15
all_values[2]	3586	1			T146	1		T222	3		T510	8
all_values[3]	3666	1			T146	2		T222	2		T510	14
all_values[4]	3525	1			T146	1		T222	5		T510	12
all_values[5]	3575	1			T510	15		T399	10		T472	5
all_values[6]	3524	1			T222	6		T510	5		T399	12
all_values[7]	3586	1			T146	3		T222	1		T510	12
all_values[8]	3501	1			T222	2		T510	4		T399	9
all_values[9]	3572	1			T222	3		T510	11		T399	17
all_values[10]	3511	1			T146	1		T222	3		T510	7
all_values[11]	3595	1			T146	1		T222	2		T510	10
all_values[12]	3608	1			T222	2		T510	15		T399	12
all_values[13]	3580	1			T146	1		T222	6		T510	12
all_values[14]	3507	1			T222	4		T510	9		T399	11
all_values[15]	3593	1			T222	4		T510	12		T399	9
all_values[16]	3596	1			T222	8		T510	11		T399	15
all_values[17]	3620	1			T146	1		T222	4		T510	8
all_values[18]	3503	1			T222	2		T510	11		T399	11
all_values[19]	3595	1			T146	1		T222	1		T510	11
all_values[20]	3534	1			T146	2		T222	4		T510	14
all_values[21]	3526	1			T146	2		T222	5		T510	8
all_values[22]	3458	1			T146	1		T222	3		T510	12
all_values[23]	3569	1			T146	1		T222	1		T510	9
all_values[24]	3570	1			T146	2		T222	4		T510	16
all_values[25]	3548	1			T222	3		T510	8		T399	7
all_values[26]	3513	1			T222	2		T510	17		T399	12
all_values[27]	3533	1			T146	1		T222	2		T510	10
all_values[28]	3591	1			T146	4		T222	5		T510	7
all_values[29]	3532	1			T222	2		T510	9		T399	18
all_values[30]	3524	1			T222	6		T510	11		T399	12
all_values[31]	3582	1			T146	1		T222	3		T510	9
all_values[32]	3538	1			T146	2		T222	4		T510	16
all_values[33]	3685	1			T222	2		T510	14		T399	14
all_values[34]	3518	1			T222	3		T510	8		T399	8
all_values[35]	3594	1			T146	1		T222	3		T510	12
all_values[36]	3567	1			T146	2		T222	2		T510	5
all_values[37]	3590	1			T146	1		T222	4		T510	10
all_values[38]	3634	1			T146	1		T222	1		T510	15
all_values[39]	3512	1			T222	5		T510	12		T399	15
all_values[40]	3544	1			T510	13		T399	8		T472	1
all_values[41]	3536	1			T146	1		T222	4		T510	12
all_values[42]	3531	1			T146	1		T222	2		T510	10
all_values[43]	3570	1			T146	3		T222	3		T510	7
all_values[44]	3512	1			T146	1		T510	7		T399	11
all_values[45]	3665	1			T222	6		T510	10		T399	5
all_values[46]	3631	1			T146	1		T222	2		T510	14
all_values[47]	3392	1			T146	1		T510	9		T399	10
all_values[48]	3501	1			T146	1		T222	2		T510	10
all_values[49]	3560	1			T222	2		T510	13		T399	14
all_values[50]	3663	1			T146	2		T222	1		T510	12
all_values[51]	3526	1			T222	5		T510	7		T399	11
all_values[52]	3593	1			T146	2		T222	2		T510	7
all_values[53]	3616	1			T222	3		T510	9		T399	10
all_values[54]	3562	1			T146	1		T222	3		T510	10
all_values[55]	3501	1			T222	7		T510	9		T399	11
all_values[56]	3579	1			T146	1		T222	5		T510	9
all_values[57]	3479	1			T222	1		T510	6		T399	18
all_values[58]	3599	1			T222	2		T510	11		T399	12
all_values[59]	3621	1			T146	1		T222	4		T510	14
all_values[60]	3631	1			T222	1		T510	14		T399	15
all_values[61]	3478	1			T146	1		T222	5		T510	5
all_values[62]	3480	1			T510	5		T399	12		T472	2
all_values[63]	3561	1			T222	3		T510	6		T399	17