Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	421	1			T77	3		T381	1		T501	1
all_values[1]	468	1			T77	1		T501	3		T823	4
all_values[2]	444	1			T75	1		T77	1		T416	1
all_values[3]	447	1			T75	1		T395	1		T382	1
all_values[4]	507	1			T77	1		T416	1		T395	1
all_values[5]	446	1			T77	2		T416	1		T501	1
all_values[6]	437	1			T77	3		T416	1		T395	2
all_values[7]	446	1			T75	1		T77	6		T416	2
all_values[8]	449	1			T75	1		T77	5		T501	2
all_values[9]	430	1			T75	1		T77	1		T395	1
all_values[10]	427	1			T77	1		T605	1		T819	1
all_values[11]	451	1			T77	2		T416	3		T381	2
all_values[12]	448	1			T77	1		T382	1		T501	2
all_values[13]	458	1			T75	1		T77	3		T416	1
all_values[14]	433	1			T75	4		T77	3		T395	1
all_values[15]	453	1			T75	1		T77	1		T416	1
all_values[16]	430	1			T77	4		T381	1		T501	4
all_values[17]	461	1			T77	4		T501	1		T823	2
all_values[18]	413	1			T77	1		T382	3		T501	1
all_values[19]	425	1			T77	2		T416	1		T381	2
all_values[20]	467	1			T77	2		T501	2		T422	1
all_values[21]	456	1			T75	1		T77	6		T381	1
all_values[22]	449	1			T77	3		T395	1		T501	3
all_values[23]	432	1			T77	1		T382	1		T819	1
all_values[24]	479	1			T416	1		T395	1		T819	1
all_values[25]	447	1			T75	1		T77	1		T808	1
all_values[26]	464	1			T75	2		T77	6		T501	2
all_values[27]	465	1			T75	1		T77	2		T416	2
all_values[28]	481	1			T75	1		T77	3		T395	1
all_values[29]	419	1			T395	1		T381	1		T382	2
all_values[30]	448	1			T75	1		T77	2		T381	1
all_values[31]	454	1			T75	5		T77	4		T416	2
all_values[32]	432	1			T75	1		T77	4		T382	1
all_values[33]	463	1			T75	2		T77	4		T422	1
all_values[34]	429	1			T75	1		T77	2		T381	2
all_values[35]	391	1			T75	2		T77	3		T381	1
all_values[36]	420	1			T77	1		T605	1		T382	1
all_values[37]	451	1			T77	3		T416	1		T395	1
all_values[38]	428	1			T77	1		T416	1		T395	1
all_values[39]	445	1			T77	1		T416	1		T395	1
all_values[40]	412	1			T77	2		T823	1		T827	3
all_values[41]	423	1			T75	1		T382	2		T501	1
all_values[42]	416	1			T75	2		T77	4		T381	2
all_values[43]	443	1			T77	1		T501	1		T651	2
all_values[44]	439	1			T75	1		T77	5		T382	2
all_values[45]	468	1			T77	2		T416	1		T395	2
all_values[46]	481	1			T75	2		T77	2		T395	1
all_values[47]	414	1			T75	1		T77	2		T381	1
all_values[48]	438	1			T75	2		T77	3		T501	1
all_values[49]	464	1			T75	1		T77	1		T416	2