Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.30	95.45	94.45	95.62		95.33	97.38	99.55

Total tests in report: 2770

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.46	40.46	45.66	45.66	43.19	43.19	32.05	32.05			58.31	58.31	63.15	63.15	0.43	0.43	/workspace/coverage/default/43.chip_sw_all_escalation_resets.3830623907
52.83	12.36	58.88	13.22	57.68	14.49	36.99	4.95			71.50	13.19	90.93	27.78	0.99	0.55	/workspace/coverage/default/1.chip_jtag_csr_rw.2946122205
58.90	6.07	71.62	12.74	66.16	8.48	40.90	3.90			82.80	11.30	90.93	0.00	0.99	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1997410092
64.33	5.43	71.66	0.03	68.32	2.16	40.90	0.00			83.00	0.20	90.93	0.00	31.19	30.21	/workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1932009574
68.51	4.18	78.15	6.49	69.49	1.17	47.11	6.22			83.19	0.19	90.93	0.00	42.18	10.99	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.1145345688
71.59	3.08	78.15	0.00	69.73	0.23	47.11	0.00			83.20	0.02	90.93	0.00	60.44	18.26	/workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.614738951
74.27	2.68	78.15	0.00	69.73	0.00	63.13	16.01			83.20	0.00	90.93	0.00	60.49	0.05	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.676573842
76.85	2.58	78.15	0.00	69.73	0.00	63.13	0.00			83.20	0.00	90.93	0.00	75.95	15.46	/workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.731969652
79.15	2.30	83.16	5.02	73.53	3.80	66.59	3.46			84.74	1.53	90.93	0.00	75.95	0.00	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.105421500
80.88	1.73	85.19	2.02	76.29	2.76	68.56	1.97			86.74	2.00	91.11	0.19	77.39	1.45	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3383976157
82.55	1.67	85.19	0.00	76.46	0.17	68.56	0.00			86.77	0.03	91.11	0.00	87.23	9.83	/workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.657770544
84.00	1.45	85.34	0.15	76.51	0.05	76.68	8.12			86.79	0.02	91.48	0.37	87.23	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1264131761
85.29	1.28	87.08	1.74	80.00	3.49	77.35	0.67			87.88	1.09	91.48	0.00	87.95	0.72	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.203026360
86.43	1.14	87.39	0.32	80.18	0.17	79.46	2.11			88.06	0.18	95.56	4.07	87.95	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3688523520
87.43	1.00	88.96	1.57	82.21	2.03	79.95	0.49			89.98	1.92	95.56	0.00	87.95	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1939940543
88.23	0.80	89.99	1.02	83.01	0.80	81.85	1.90			90.81	0.83	95.74	0.19	87.98	0.04	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2639852904
88.97	0.74	91.06	1.08	84.01	1.00	83.07	1.23			91.97	1.16	95.74	0.00	87.98	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.3082315919
89.70	0.73	91.07	0.01	85.31	1.30	83.07	0.00			91.98	0.01	95.74	0.00	91.04	3.05	/workspace/coverage/cover_reg_top/9.xbar_stress_all.2020940039
90.18	0.48	91.86	0.79	86.21	0.90	83.55	0.47			92.70	0.72	95.74	0.00	91.04	0.00	/workspace/coverage/default/1.chip_sw_gpio.618958684
90.66	0.47	92.34	0.48	86.71	0.50	84.92	1.37			93.19	0.49	95.74	0.00	91.04	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.3776344073
91.13	0.47	92.34	0.00	86.71	0.00	84.92	0.00			93.19	0.00	95.74	0.00	93.87	2.83	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.335005965
91.55	0.42	92.37	0.03	87.13	0.43	84.92	0.00			93.23	0.04	95.74	0.00	95.89	2.02	/workspace/coverage/cover_reg_top/90.xbar_access_same_device.2355467059
91.87	0.32	92.56	0.18	87.29	0.15	86.43	1.51			93.32	0.09	95.74	0.00	95.89	0.00	/workspace/coverage/default/0.rom_e2e_smoke.370121976
92.16	0.29	92.57	0.01	87.29	0.01	88.15	1.72			93.32	0.00	95.74	0.00	95.89	0.00	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1383321198
92.44	0.28	92.58	0.01	88.62	1.33	88.15	0.00			93.32	0.00	95.74	0.00	96.23	0.34	/workspace/coverage/cover_reg_top/17.chip_tl_errors.3381555487
92.66	0.22	92.70	0.13	89.58	0.96	88.20	0.05			93.35	0.02	95.74	0.00	96.40	0.18	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.520744341
92.87	0.20	92.91	0.21	89.71	0.13	88.39	0.19			93.49	0.14	96.30	0.56	96.40	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3908265941
93.07	0.20	93.67	0.76	89.88	0.17	88.59	0.21			93.56	0.07	96.30	0.00	96.40	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.191903046
93.27	0.20	93.67	0.00	89.96	0.08	88.59	0.00			93.56	0.00	96.30	0.00	97.51	1.10	/workspace/coverage/cover_reg_top/37.xbar_random_large_delays.3010927919
93.44	0.18	93.77	0.10	90.05	0.09	89.29	0.70			93.73	0.17	96.30	0.00	97.52	0.01	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1420395363
93.62	0.17	93.83	0.06	90.46	0.41	89.39	0.10			94.16	0.43	96.30	0.00	97.57	0.05	/workspace/coverage/default/0.chip_jtag_csr_rw.4251307076
93.78	0.17	94.11	0.28	90.72	0.26	89.49	0.09			94.48	0.32	96.30	0.00	97.60	0.04	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2285283167
93.94	0.16	94.12	0.01	90.75	0.03	90.27	0.78			94.49	0.01	96.30	0.00	97.74	0.14	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2366531432
94.09	0.14	94.33	0.21	90.80	0.05	90.82	0.55			94.53	0.04	96.30	0.00	97.74	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4017852757
94.22	0.14	94.33	0.00	91.63	0.83	90.82	0.00			94.53	0.00	96.30	0.00	97.74	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.2796629834
94.35	0.13	94.33	0.00	91.63	0.00	91.60	0.78			94.53	0.00	96.30	0.00	97.74	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.208828430
94.46	0.11	94.33	0.01	91.65	0.02	92.05	0.45			94.53	0.00	96.48	0.19	97.74	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3465560975
94.57	0.10	94.50	0.17	91.91	0.26	92.23	0.18			94.53	0.00	96.48	0.00	97.74	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4032559720
94.67	0.10	94.53	0.03	92.17	0.27	92.25	0.02			94.82	0.30	96.48	0.00	97.74	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1836657149
94.75	0.08	94.53	0.00	92.17	0.00	92.72	0.47			94.82	0.00	96.48	0.00	97.74	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3761067514
94.82	0.07	94.53	0.00	92.17	0.00	93.16	0.44			94.82	0.00	96.48	0.00	97.74	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3419476082
94.89	0.07	94.53	0.00	92.34	0.17	93.16	0.00			94.86	0.03	96.48	0.00	97.96	0.21	/workspace/coverage/cover_reg_top/20.xbar_stress_all.120115439
94.95	0.06	94.53	0.00	92.51	0.17	93.17	0.01			95.06	0.20	96.48	0.00	97.96	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1015176837
95.01	0.06	94.65	0.12	92.53	0.02	93.18	0.02			95.07	0.02	96.67	0.19	97.97	0.01	/workspace/coverage/default/52.chip_sw_all_escalation_resets.1614542359
95.07	0.06	94.65	0.00	92.53	0.00	93.54	0.36			95.07	0.00	96.67	0.00	97.97	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2560191742
95.13	0.05	94.65	0.00	92.79	0.26	93.54	0.00			95.07	0.00	96.67	0.00	98.04	0.07	/workspace/coverage/cover_reg_top/15.chip_tl_errors.1467732620
95.17	0.05	94.65	0.00	92.79	0.00	93.83	0.29			95.07	0.00	96.67	0.00	98.04	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3498106212
95.22	0.04	94.66	0.01	92.83	0.04	93.83	0.00			95.09	0.02	96.85	0.19	98.05	0.01	/workspace/coverage/default/39.chip_sw_all_escalation_resets.914671344
95.26	0.04	94.74	0.08	92.83	0.00	94.00	0.17			95.10	0.01	96.85	0.00	98.05	0.00	/workspace/coverage/default/2.chip_tap_straps_testunlock0.1666060807
95.30	0.04	94.75	0.01	92.85	0.02	94.00	0.00			95.12	0.02	97.04	0.19	98.06	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.3271738409
95.34	0.04	94.75	0.01	92.86	0.01	94.00	0.01			95.13	0.01	97.22	0.19	98.07	0.01	/workspace/coverage/default/69.chip_sw_all_escalation_resets.3125161159
95.37	0.03	94.77	0.01	92.90	0.04	94.15	0.15			95.13	0.00	97.22	0.00	98.07	0.00	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1389631105
95.41	0.03	94.77	0.00	93.09	0.19	94.15	0.00			95.13	0.00	97.22	0.00	98.07	0.00	/workspace/coverage/cover_reg_top/21.chip_tl_errors.2858246461
95.44	0.03	94.77	0.00	93.09	0.00	94.35	0.19			95.13	0.00	97.22	0.00	98.07	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3671673167
95.47	0.03	94.77	0.00	93.09	0.00	94.35	0.01			95.13	0.00	97.41	0.19	98.07	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2872697178
95.50	0.03	94.77	0.00	93.24	0.14	94.35	0.00			95.15	0.02	97.41	0.00	98.10	0.02	/workspace/coverage/cover_reg_top/19.xbar_stress_all.4132564833
95.53	0.03	94.77	0.00	93.24	0.00	94.53	0.18			95.15	0.00	97.41	0.00	98.10	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1729791479
95.56	0.03	94.80	0.04	93.29	0.06	94.56	0.02			95.20	0.05	97.41	0.00	98.10	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4162947341
95.58	0.03	94.80	0.00	93.35	0.06	94.56	0.00			95.21	0.02	97.41	0.00	98.18	0.08	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.415147076
95.61	0.02	94.80	0.00	93.35	0.00	94.70	0.14			95.21	0.00	97.41	0.00	98.18	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.559818275
95.63	0.02	94.80	0.00	93.35	0.00	94.70	0.00			95.21	0.00	97.41	0.00	98.32	0.14	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1995907448
95.65	0.02	94.84	0.04	93.42	0.07	94.70	0.00			95.24	0.02	97.41	0.00	98.32	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1438684846
95.67	0.02	94.89	0.06	93.47	0.05	94.70	0.00			95.25	0.02	97.41	0.00	98.32	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1790495374
95.69	0.02	94.89	0.00	93.50	0.03	94.70	0.00			95.25	0.00	97.41	0.00	98.41	0.09	/workspace/coverage/cover_reg_top/2.xbar_access_same_device.3594838926
95.71	0.02	94.89	0.00	93.50	0.00	94.82	0.12			95.25	0.00	97.41	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2310835234
95.73	0.02	94.95	0.05	93.54	0.05	94.82	0.00			95.27	0.02	97.41	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.115158599
95.75	0.02	94.97	0.02	93.54	0.00	94.90	0.09			95.27	0.00	97.41	0.00	98.41	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.675762046
95.77	0.02	94.97	0.00	93.55	0.01	94.90	0.00			95.27	0.00	97.41	0.00	98.51	0.09	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2137972853
95.78	0.02	94.97	0.00	93.55	0.00	94.99	0.09			95.27	0.00	97.41	0.00	98.51	0.00	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.144538922
95.80	0.02	94.97	0.00	93.64	0.09	94.99	0.00			95.27	0.00	97.41	0.00	98.51	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3011653541
95.81	0.01	95.00	0.03	93.67	0.03	95.01	0.02			95.29	0.02	97.41	0.00	98.51	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2354682479
95.83	0.01	95.00	0.00	93.67	0.00	95.09	0.08			95.29	0.00	97.41	0.00	98.51	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.400667470
95.84	0.01	95.01	0.02	93.70	0.03	95.11	0.02			95.29	0.00	97.41	0.00	98.52	0.01	/workspace/coverage/default/1.chip_sw_alert_test.3813598764
95.85	0.01	95.01	0.00	93.77	0.07	95.11	0.00			95.29	0.00	97.41	0.00	98.52	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.409611121
95.86	0.01	95.01	0.00	93.77	0.00	95.18	0.07			95.29	0.00	97.41	0.00	98.52	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2298316941
95.87	0.01	95.01	0.00	93.77	0.00	95.18	0.00			95.29	0.00	97.41	0.00	98.59	0.07	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3040157180
95.89	0.01	95.01	0.00	93.84	0.07	95.18	0.00			95.29	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/24.chip_tl_errors.3980330041
95.90	0.01	95.05	0.04	93.86	0.02	95.18	0.00			95.29	0.01	97.41	0.00	98.59	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1316513709
95.91	0.01	95.08	0.03	93.88	0.01	95.19	0.01			95.29	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3467897759
95.91	0.01	95.11	0.03	93.88	0.01	95.19	0.01			95.31	0.02	97.41	0.00	98.59	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.702087115
95.92	0.01	95.11	0.00	93.90	0.01	95.19	0.00			95.31	0.00	97.41	0.00	98.63	0.04	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2531152327
95.93	0.01	95.11	0.00	93.90	0.00	95.24	0.05			95.31	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2718119109
95.94	0.01	95.11	0.00	93.94	0.05	95.24	0.00			95.31	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/cover_reg_top/3.chip_tl_errors.1056766332
95.95	0.01	95.11	0.00	93.99	0.05	95.24	0.00			95.31	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3641831526
95.95	0.01	95.11	0.00	93.99	0.00	95.28	0.04			95.31	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3825786825
95.96	0.01	95.11	0.00	94.03	0.04	95.28	0.00			95.31	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/cover_reg_top/86.xbar_stress_all.4276131302
95.97	0.01	95.11	0.00	94.04	0.01	95.32	0.03			95.31	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1095795435
95.97	0.01	95.11	0.01	94.06	0.01	95.34	0.02			95.31	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx.3635176111
95.98	0.01	95.11	0.00	94.09	0.04	95.34	0.00			95.31	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/cover_reg_top/8.chip_tl_errors.608017376
95.99	0.01	95.11	0.00	94.09	0.00	95.34	0.00			95.31	0.00	97.41	0.00	98.66	0.04	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3962720248
95.99	0.01	95.11	0.00	94.09	0.00	95.34	0.00			95.31	0.00	97.41	0.00	98.70	0.04	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3787649510
96.00	0.01	95.11	0.00	94.09	0.00	95.37	0.03			95.31	0.00	97.41	0.00	98.70	0.00	/workspace/coverage/default/0.chip_sw_flash_init.2206479469
96.00	0.01	95.11	0.00	94.09	0.01	95.40	0.03			95.31	0.00	97.41	0.00	98.70	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1530291712
96.01	0.01	95.11	0.01	94.12	0.02	95.40	0.01			95.31	0.00	97.41	0.00	98.70	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.389900801
96.01	0.01	95.11	0.00	94.15	0.03	95.40	0.00			95.31	0.00	97.41	0.00	98.70	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.3370195721
96.02	0.01	95.11	0.00	94.17	0.03	95.40	0.00			95.31	0.00	97.41	0.00	98.70	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1073193182
96.02	0.01	95.11	0.00	94.17	0.00	95.43	0.03			95.31	0.00	97.41	0.00	98.70	0.00	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4215273894
96.03	0.01	95.11	0.00	94.17	0.00	95.43	0.00			95.31	0.00	97.41	0.00	98.72	0.02	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.2057129202
96.03	0.01	95.11	0.00	94.20	0.02	95.43	0.00			95.31	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.342651581
96.03	0.01	95.11	0.00	94.22	0.02	95.43	0.00			95.31	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1797556359
96.04	0.01	95.11	0.00	94.24	0.02	95.43	0.00			95.31	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/62.xbar_access_same_device.3809739534
96.04	0.01	95.11	0.00	94.26	0.02	95.43	0.00			95.31	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.841830844
96.04	0.01	95.11	0.00	94.27	0.01	95.43	0.00			95.31	0.00	97.41	0.00	98.73	0.01	/workspace/coverage/cover_reg_top/10.chip_tl_errors.1421092461
96.05	0.01	95.11	0.00	94.28	0.01	95.43	0.00			95.31	0.00	97.41	0.00	98.74	0.01	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2805963892
96.05	0.01	95.11	0.00	94.28	0.01	95.43	0.00			95.31	0.00	97.41	0.00	98.75	0.01	/workspace/coverage/cover_reg_top/60.xbar_stress_all.1826742299
96.05	0.01	95.11	0.00	94.28	0.00	95.45	0.02			95.31	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_kmac_entropy.1937784406
96.06	0.01	95.11	0.00	94.28	0.00	95.47	0.02			95.31	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.1213494688
96.06	0.01	95.11	0.00	94.30	0.02	95.47	0.00			95.31	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2803901767
96.06	0.01	95.13	0.01	94.30	0.00	95.47	0.01			95.31	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2110361662
96.06	0.01	95.13	0.00	94.30	0.01	95.47	0.01			95.32	0.01	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2711951558
96.07	0.01	95.13	0.00	94.30	0.00	95.48	0.01			95.32	0.00	97.41	0.00	98.77	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.4193756640
96.07	0.01	95.14	0.01	94.30	0.00	95.48	0.01			95.32	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.1821228429
96.07	0.01	95.14	0.00	94.31	0.01	95.48	0.00			95.32	0.00	97.41	0.00	98.78	0.01	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1630707725
96.07	0.01	95.14	0.00	94.32	0.01	95.48	0.00			95.32	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_rw.2587044158
96.08	0.01	95.14	0.00	94.34	0.01	95.48	0.00			95.32	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.704431782
96.08	0.01	95.14	0.00	94.35	0.01	95.48	0.00			95.32	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/75.xbar_random_large_delays.3447663561
96.08	0.01	95.15	0.01	94.36	0.01	95.48	0.00			95.32	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.161610573
96.08	0.01	95.15	0.00	94.36	0.00	95.50	0.01			95.32	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1914630405
96.09	0.01	95.15	0.00	94.36	0.00	95.51	0.01			95.32	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2973571650
96.09	0.01	95.15	0.00	94.36	0.00	95.52	0.01			95.32	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1929031535
96.09	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.79	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3351416400
96.09	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.80	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.1666378777
96.09	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.81	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.714121501
96.10	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.83	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2482195423
96.10	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.84	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.656473159
96.10	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.85	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.3109795133
96.10	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.86	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.4129576224
96.10	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.87	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.767856270
96.11	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.88	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.2174897738
96.11	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.90	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.2745308071
96.11	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.91	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.1066797220
96.11	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.92	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.512420675
96.11	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.93	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1997520975
96.12	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.94	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2552966788
96.12	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.95	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.4101920095
96.12	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.97	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3051977959
96.12	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.98	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.690302031
96.12	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	98.99	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.567131023
96.13	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.00	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.909387463
96.13	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.01	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.3889681593
96.13	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.02	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.3308230129
96.13	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.04	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3194575016
96.13	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.05	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.2158084698
96.14	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.06	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1173571081
96.14	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.07	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.1010164878
96.14	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.08	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2251915937
96.14	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.10	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.868824009
96.14	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.11	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.4114402983
96.15	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.12	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.497542145
96.15	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.13	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.1292267614
96.15	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.14	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2127353291
96.15	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.15	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.2299515030
96.15	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.17	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.613646413
96.16	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.18	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.436443300
96.16	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.19	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3826098772
96.16	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.20	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3152091519
96.16	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.21	0.01	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1359638243
96.16	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.22	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.702424557
96.17	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.24	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2881444310
96.17	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.25	0.01	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3051757136
96.17	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.26	0.01	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1243937264
96.17	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.27	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.54751505
96.17	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.28	0.01	/workspace/coverage/default/40.chip_sw_all_escalation_resets.4123995304
96.18	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.30	0.01	/workspace/coverage/default/41.chip_sw_all_escalation_resets.1790707112
96.18	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.31	0.01	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3594987127
96.18	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.32	0.01	/workspace/coverage/default/44.chip_sw_all_escalation_resets.548349213
96.18	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.33	0.01	/workspace/coverage/default/45.chip_sw_all_escalation_resets.3585330884
96.18	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.34	0.01	/workspace/coverage/default/48.chip_sw_all_escalation_resets.3876908233
96.18	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.35	0.01	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2411724947
96.19	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.37	0.01	/workspace/coverage/default/5.chip_sw_all_escalation_resets.951605120
96.19	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.38	0.01	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.847561033
96.19	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.39	0.01	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2299594176
96.19	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.40	0.01	/workspace/coverage/default/56.chip_sw_all_escalation_resets.751061482
96.19	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.41	0.01	/workspace/coverage/default/58.chip_sw_all_escalation_resets.563641716
96.20	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.42	0.01	/workspace/coverage/default/59.chip_sw_all_escalation_resets.465070127
96.20	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.44	0.01	/workspace/coverage/default/70.chip_sw_all_escalation_resets.2724244601
96.20	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.45	0.01	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3560929191
96.20	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.46	0.01	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4292894533
96.20	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.47	0.01	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1155448186
96.21	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.48	0.01	/workspace/coverage/default/79.chip_sw_all_escalation_resets.3706331212
96.21	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.4158206319
96.21	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3692475890
96.21	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/87.chip_sw_all_escalation_resets.1061748519
96.21	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/88.chip_sw_all_escalation_resets.1479343083
96.22	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.54	0.01	/workspace/coverage/default/91.chip_sw_all_escalation_resets.3467012080
96.22	0.01	95.15	0.00	94.36	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.55	0.01	/workspace/coverage/default/96.chip_sw_all_escalation_resets.3798365016
96.22	0.01	95.15	0.00	94.37	0.01	95.52	0.00			95.32	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/14.chip_tl_errors.3009839854
96.22	0.01	95.15	0.00	94.38	0.01	95.52	0.00			95.32	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.1994239849
96.22	0.01	95.15	0.00	94.39	0.01	95.52	0.00			95.32	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_gpio.1758147556
96.23	0.01	95.16	0.01	94.39	0.00	95.52	0.00			95.32	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2867065493
96.23	0.01	95.16	0.01	94.39	0.00	95.53	0.01			95.32	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/29.chip_sw_all_escalation_resets.501290589
96.23	0.01	95.16	0.00	94.39	0.00	95.54	0.01			95.32	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.562669990
96.23	0.01	95.16	0.00	94.39	0.00	95.55	0.01			95.32	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1998133710
96.23	0.01	95.16	0.00	94.39	0.00	95.56	0.01			95.32	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3235429366
96.23	0.01	95.16	0.00	94.39	0.00	95.57	0.01			95.32	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1136895686
96.23	0.01	95.16	0.00	94.39	0.00	95.57	0.00			95.33	0.01	97.41	0.00	99.55	0.00	/workspace/coverage/default/1.chip_tap_straps_dev.3209965971
96.24	0.01	95.16	0.00	94.40	0.01	95.57	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.909585458
96.24	0.01	95.16	0.00	94.40	0.01	95.57	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3868277388
96.24	0.01	95.16	0.00	94.41	0.01	95.57	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2128399217
96.24	0.01	95.16	0.00	94.42	0.01	95.57	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1225773385
96.24	0.01	95.17	0.01	94.42	0.00	95.57	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4239936890
96.24	0.01	95.17	0.01	94.42	0.00	95.57	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2875937251
96.24	0.01	95.17	0.00	94.42	0.00	95.58	0.01			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.226535126
96.24	0.01	95.17	0.00	94.42	0.00	95.58	0.01			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1471741858
96.25	0.01	95.17	0.00	94.42	0.00	95.59	0.01			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1738153109
96.25	0.01	95.17	0.00	94.42	0.00	95.60	0.01			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1910918462
96.25	0.01	95.17	0.00	94.42	0.00	95.60	0.01			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.451432632
96.25	0.01	95.17	0.00	94.42	0.00	95.61	0.01			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2940090131
96.25	0.01	95.17	0.00	94.42	0.00	95.61	0.01			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3294747637
96.25	0.01	95.17	0.00	94.42	0.01	95.61	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/20.xbar_error_random.2491589688
96.25	0.01	95.17	0.00	94.43	0.01	95.61	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3669705612
96.25	0.01	95.17	0.00	94.43	0.01	95.61	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.3169317984
96.25	0.01	95.17	0.00	94.43	0.01	95.61	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1992839107
96.25	0.01	95.17	0.00	94.44	0.01	95.61	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/4.chip_tl_errors.3660085385
96.25	0.01	95.17	0.00	94.44	0.01	95.61	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.1475912848
96.25	0.01	95.17	0.00	94.44	0.01	95.61	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.2149312494
96.25	0.01	95.17	0.00	94.45	0.01	95.61	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4245573905
96.25	0.01	95.17	0.00	94.45	0.01	95.61	0.00			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_gpio.3282054760
96.25	0.01	95.17	0.00	94.45	0.00	95.61	0.01			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_aes_enc.2122580607
96.25	0.01	95.17	0.00	94.45	0.00	95.61	0.01			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_irq.135148848
96.26	0.01	95.17	0.00	94.45	0.00	95.62	0.01			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.1252986652
96.26	0.01	95.17	0.00	94.45	0.00	95.62	0.01			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.450981740
96.26	0.01	95.17	0.00	94.45	0.00	95.62	0.01			95.33	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.509825662

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3421382618
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.4074070626
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1842626014
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2317969743
/workspace/coverage/cover_reg_top/0.chip_tl_errors.2017666193
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2770492834
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3940729336
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2435970688
/workspace/coverage/cover_reg_top/0.xbar_error_random.2113794670
/workspace/coverage/cover_reg_top/0.xbar_random.3316564586
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.392823306
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1103016616
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.540491894
/workspace/coverage/cover_reg_top/0.xbar_same_source.745963506
/workspace/coverage/cover_reg_top/0.xbar_smoke.1181569912
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2332826335
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.970883596
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2701084674
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2480017608
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3620377351
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3760893066
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.897095071
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3207491304
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1645646278
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1190696547
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.299494508
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3809195349
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1947798789
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2512102024
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1943285149
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2621468967
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3333193026
/workspace/coverage/cover_reg_top/1.xbar_error_random.3021183113
/workspace/coverage/cover_reg_top/1.xbar_random.1364655252
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1434713108
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2787662082
/workspace/coverage/cover_reg_top/1.xbar_same_source.656882768
/workspace/coverage/cover_reg_top/1.xbar_smoke.530174096
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3718684609
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3131829556
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3577694697
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3998794368
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.594605439
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1275329804
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2277654609
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.683705989
/workspace/coverage/cover_reg_top/10.chip_csr_rw.4069299586
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2988882701
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1776613390
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3607655658
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2010248473
/workspace/coverage/cover_reg_top/10.xbar_error_random.879158895
/workspace/coverage/cover_reg_top/10.xbar_random.3525019156
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3444385956
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2367585957
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3820763286
/workspace/coverage/cover_reg_top/10.xbar_same_source.1502391446
/workspace/coverage/cover_reg_top/10.xbar_smoke.3251230756
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.4163229156
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.61131404
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.4184543980
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1864024599
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.676115539
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.923854891
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3495679882
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.449021540
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.106942024
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1705698778
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.217027447
/workspace/coverage/cover_reg_top/11.xbar_error_random.247733700
/workspace/coverage/cover_reg_top/11.xbar_random.3060870955
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3558229494
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2433045608
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.62108908
/workspace/coverage/cover_reg_top/11.xbar_same_source.971294845
/workspace/coverage/cover_reg_top/11.xbar_smoke.4011823546
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1100524269
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3647559588
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2265257815
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1944258179
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1791431613
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1490475170
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2132969719
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3813461980
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2805283852
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.875804264
/workspace/coverage/cover_reg_top/12.chip_tl_errors.3793344143
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1733603549
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.865014282
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.869162380
/workspace/coverage/cover_reg_top/12.xbar_error_random.4199706212
/workspace/coverage/cover_reg_top/12.xbar_random.1756530881
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.619776789
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1768954897
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1654119362
/workspace/coverage/cover_reg_top/12.xbar_same_source.3655252537
/workspace/coverage/cover_reg_top/12.xbar_smoke.448911781
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2765616209
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3763242934
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1161314456
/workspace/coverage/cover_reg_top/12.xbar_stress_all.3347536581
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.4275783124
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3831920944
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1280312924
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1231539762
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3832421078
/workspace/coverage/cover_reg_top/13.chip_tl_errors.2724598889
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.471654402
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.466090773
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3035116730
/workspace/coverage/cover_reg_top/13.xbar_error_random.3715132037
/workspace/coverage/cover_reg_top/13.xbar_random.3231161065
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.581426210
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3797017862
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3491157944
/workspace/coverage/cover_reg_top/13.xbar_same_source.1147740939
/workspace/coverage/cover_reg_top/13.xbar_smoke.2045099060
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2645690602
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3526321294
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.4206751059
/workspace/coverage/cover_reg_top/13.xbar_stress_all.387114591
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.504960069
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1676363112
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.3641450910
/workspace/coverage/cover_reg_top/14.chip_csr_rw.3915469652
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2270487899
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.2007736577
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3105599017
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3393659664
/workspace/coverage/cover_reg_top/14.xbar_error_random.1476874899
/workspace/coverage/cover_reg_top/14.xbar_random.1164544514
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2833408269
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1475305085
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1333775904
/workspace/coverage/cover_reg_top/14.xbar_same_source.3343551074
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/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2120622597
/workspace/coverage/default/71.chip_sw_all_escalation_resets.1141215837
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2359956683
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.158955734
/workspace/coverage/default/73.chip_sw_all_escalation_resets.925347936
/workspace/coverage/default/74.chip_sw_all_escalation_resets.3730397621
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3542165164
/workspace/coverage/default/75.chip_sw_all_escalation_resets.4113308042
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3727713655
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2734729132
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.461980124
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1215714787
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.4189588906
/workspace/coverage/default/78.chip_sw_all_escalation_resets.4082422319
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3636550345
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2758567397
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.90328738
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2401492725
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1577385737
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.249860506
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1461641812
/workspace/coverage/default/82.chip_sw_all_escalation_resets.386755402
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1415757819
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3311588799
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.494184309
/workspace/coverage/default/84.chip_sw_all_escalation_resets.4204659815
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1312768801
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3668656905
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.947651901
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2256047106
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1012506583
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3138392228
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1299921291
/workspace/coverage/default/89.chip_sw_all_escalation_resets.202234725
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4037750140
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3869485886
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2235539621
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1326170514
/workspace/coverage/default/90.chip_sw_all_escalation_resets.4260127685
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3385920300
/workspace/coverage/default/93.chip_sw_all_escalation_resets.737384023
/workspace/coverage/default/94.chip_sw_all_escalation_resets.699727088
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1180470847
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3262942717
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1119278854
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2030303390
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1883840197
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1460998923
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.24573120
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1657292441
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1843679934
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.530764947
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.587327547
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.366413025

---

Total test records in report: 2770

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3194575016			May 09 04:49:32 PM PDT 24	May 09 04:55:35 PM PDT 24	3802714964 ps
T2	/workspace/coverage/default/43.chip_sw_all_escalation_resets.3830623907			May 09 04:52:44 PM PDT 24	May 09 05:00:32 PM PDT 24	4696186118 ps
T3	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1136895686			May 09 04:40:04 PM PDT 24	May 09 05:32:16 PM PDT 24	24201026546 ps
T62	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2639852904			May 09 04:40:57 PM PDT 24	May 09 04:47:55 PM PDT 24	6158987390 ps
T33	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2053802537			May 09 04:40:29 PM PDT 24	May 09 04:47:11 PM PDT 24	3743198853 ps
T83	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3997922802			May 09 04:21:28 PM PDT 24	May 09 04:25:15 PM PDT 24	2704269968 ps
T84	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2867149616			May 09 04:40:47 PM PDT 24	May 09 04:45:05 PM PDT 24	2692529000 ps
T46	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1316513709			May 09 04:19:29 PM PDT 24	May 09 04:23:33 PM PDT 24	3104584572 ps
T85	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.953905558			May 09 04:45:00 PM PDT 24	May 09 04:51:05 PM PDT 24	4252464564 ps
T34	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3465560975			May 09 04:20:55 PM PDT 24	May 09 04:28:37 PM PDT 24	4433965976 ps
T98	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1389631105			May 09 04:42:00 PM PDT 24	May 09 05:17:59 PM PDT 24	12980341528 ps
T99	/workspace/coverage/default/0.chip_sw_kmac_entropy.1937784406			May 09 04:10:40 PM PDT 24	May 09 04:15:07 PM PDT 24	3267287270 ps
T48	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1738153109			May 09 04:39:23 PM PDT 24	May 09 04:41:00 PM PDT 24	2277526667 ps
T49	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4215273894			May 09 04:22:43 PM PDT 24	May 09 04:31:02 PM PDT 24	4091497064 ps
T43	/workspace/coverage/default/0.rom_e2e_smoke.370121976			May 09 04:16:48 PM PDT 24	May 09 05:27:33 PM PDT 24	17510345000 ps
T100	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3688523520			May 09 04:19:47 PM PDT 24	May 09 04:22:33 PM PDT 24	2850088696 ps
T4	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1125028161			May 09 04:21:27 PM PDT 24	May 09 05:04:11 PM PDT 24	34148980488 ps
T244	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.436443300			May 09 04:43:05 PM PDT 24	May 09 04:48:47 PM PDT 24	3709479740 ps
T10	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.4142895081			May 09 04:17:05 PM PDT 24	May 09 04:20:47 PM PDT 24	2439632878 ps
T261	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1264220447			May 09 04:22:14 PM PDT 24	May 09 04:31:29 PM PDT 24	4682969036 ps
T50	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.144538922			May 09 04:41:46 PM PDT 24	May 09 04:51:07 PM PDT 24	5000688040 ps
T141	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1659780895			May 09 04:38:03 PM PDT 24	May 09 04:48:53 PM PDT 24	4022048250 ps
T20	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.675762046			May 09 04:18:59 PM PDT 24	May 09 04:46:17 PM PDT 24	23296123764 ps
T117	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.4092951292			May 09 04:09:48 PM PDT 24	May 09 04:13:18 PM PDT 24	2779189656 ps
T68	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3626422213			May 09 04:40:36 PM PDT 24	May 09 04:48:21 PM PDT 24	3296654284 ps
T64	/workspace/coverage/default/19.chip_sw_all_escalation_resets.3758948746			May 09 04:44:49 PM PDT 24	May 09 04:55:33 PM PDT 24	6001625912 ps
T47	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2711951558			May 09 04:11:26 PM PDT 24	May 09 04:18:46 PM PDT 24	5702709927 ps
T271	/workspace/coverage/default/4.chip_sw_uart_tx_rx.3635176111			May 09 04:43:31 PM PDT 24	May 09 04:52:57 PM PDT 24	3827255220 ps
T5	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.873213201			May 09 04:18:41 PM PDT 24	May 09 07:15:00 PM PDT 24	59220461352 ps
T865	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2502319042			May 09 04:41:07 PM PDT 24	May 09 04:52:42 PM PDT 24	4858847640 ps
T6	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1420395363			May 09 04:07:04 PM PDT 24	May 09 07:12:53 PM PDT 24	58591102953 ps
T137	/workspace/coverage/default/0.chip_sw_otbn_smoketest.3226774351			May 09 04:14:00 PM PDT 24	May 09 04:32:03 PM PDT 24	6469598672 ps
T114	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1337220730			May 09 04:42:06 PM PDT 24	May 09 04:50:47 PM PDT 24	4056188730 ps
T176	/workspace/coverage/default/87.chip_sw_all_escalation_resets.1061748519			May 09 04:45:35 PM PDT 24	May 09 04:54:53 PM PDT 24	5746154046 ps
T108	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1435460441			May 09 04:10:27 PM PDT 24	May 09 04:14:00 PM PDT 24	3112102825 ps
T279	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2682187798			May 09 04:47:55 PM PDT 24	May 09 04:54:16 PM PDT 24	3138704824 ps
T285	/workspace/coverage/default/95.chip_sw_all_escalation_resets.1180470847			May 09 04:51:45 PM PDT 24	May 09 04:59:30 PM PDT 24	4441643840 ps
T217	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4017852757			May 09 04:40:32 PM PDT 24	May 09 04:59:57 PM PDT 24	12724926198 ps
T65	/workspace/coverage/default/2.chip_tap_straps_testunlock0.1666060807			May 09 04:39:32 PM PDT 24	May 09 04:41:50 PM PDT 24	2428348879 ps
T7	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1939940543			May 09 04:20:58 PM PDT 24	May 09 04:26:07 PM PDT 24	3316412007 ps
T286	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3351416400			May 09 04:10:18 PM PDT 24	May 09 04:17:07 PM PDT 24	3125901054 ps
T163	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3946723904			May 09 04:11:20 PM PDT 24	May 09 04:15:01 PM PDT 24	2634234752 ps
T287	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3290550091			May 09 04:42:15 PM PDT 24	May 09 04:48:25 PM PDT 24	3016233600 ps
T218	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1537665562			May 09 04:40:03 PM PDT 24	May 09 04:58:35 PM PDT 24	17019038823 ps
T288	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2371723934			May 09 04:11:03 PM PDT 24	May 09 04:13:54 PM PDT 24	2472188528 ps
T69	/workspace/coverage/default/4.chip_tap_straps_rma.445368722			May 09 04:42:46 PM PDT 24	May 09 04:48:33 PM PDT 24	3909857168 ps
T79	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3383976157			May 09 04:40:08 PM PDT 24	May 09 05:00:21 PM PDT 24	11235287032 ps
T63	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1264131761			May 09 04:40:10 PM PDT 24	May 09 04:53:22 PM PDT 24	7240198625 ps
T330	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2881444310			May 09 04:49:32 PM PDT 24	May 09 04:56:11 PM PDT 24	3550612996 ps
T174	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1246877423			May 09 04:39:45 PM PDT 24	May 09 04:47:57 PM PDT 24	3587807184 ps
T109	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.723228472			May 09 04:23:26 PM PDT 24	May 09 04:27:14 PM PDT 24	3001463950 ps
T337	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3814287013			May 09 04:19:52 PM PDT 24	May 09 04:26:49 PM PDT 24	6723247708 ps
T150	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3753173306			May 09 04:12:57 PM PDT 24	May 09 04:14:28 PM PDT 24	2138316397 ps
T272	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.4181490565			May 09 04:44:05 PM PDT 24	May 09 04:53:10 PM PDT 24	4383972908 ps
T118	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1827372928			May 09 04:41:15 PM PDT 24	May 09 04:48:19 PM PDT 24	4960196204 ps
T338	/workspace/coverage/default/0.chip_sw_aes_idle.968941679			May 09 04:11:18 PM PDT 24	May 09 04:15:43 PM PDT 24	2751940280 ps
T339	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.750839666			May 09 04:48:45 PM PDT 24	May 09 04:55:34 PM PDT 24	3623461736 ps
T21	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.979997758			May 09 04:19:58 PM PDT 24	May 09 05:17:27 PM PDT 24	20107524519 ps
T866	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.647100152			May 09 04:07:49 PM PDT 24	May 09 04:12:21 PM PDT 24	3091735336 ps
T13	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.581810123			May 09 04:42:27 PM PDT 24	May 09 04:53:31 PM PDT 24	4247598456 ps
T316	/workspace/coverage/default/88.chip_sw_all_escalation_resets.1479343083			May 09 04:43:36 PM PDT 24	May 09 04:52:16 PM PDT 24	5535526398 ps
T175	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1331527654			May 09 04:09:43 PM PDT 24	May 09 04:19:07 PM PDT 24	3788618340 ps
T674	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.656473159			May 09 04:45:40 PM PDT 24	May 09 04:51:47 PM PDT 24	3242094928 ps
T700	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2253284097			May 09 04:19:49 PM PDT 24	May 09 04:33:32 PM PDT 24	10149552184 ps
T405	/workspace/coverage/default/2.chip_sw_kmac_smoketest.2458408222			May 09 04:42:15 PM PDT 24	May 09 04:47:32 PM PDT 24	3418705960 ps
T205	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1355434667			May 09 04:23:12 PM PDT 24	May 09 04:31:57 PM PDT 24	4327902536 ps
T867	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2197965796			May 09 04:45:16 PM PDT 24	May 09 04:54:26 PM PDT 24	7664335470 ps
T177	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3909674794			May 09 04:39:46 PM PDT 24	May 09 04:50:02 PM PDT 24	4317616410 ps
T403	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2668617464			May 09 04:18:44 PM PDT 24	May 09 04:37:59 PM PDT 24	6132042633 ps
T333	/workspace/coverage/default/1.chip_sw_edn_sw_mode.2518515351			May 09 04:21:48 PM PDT 24	May 09 04:54:57 PM PDT 24	9498774004 ps
T310	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2951493542			May 09 04:08:05 PM PDT 24	May 09 04:13:04 PM PDT 24	3187168202 ps
T16	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2972795338			May 09 04:15:27 PM PDT 24	May 09 04:22:08 PM PDT 24	5371019824 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_vbus.2489138268			May 09 04:07:41 PM PDT 24	May 09 04:11:06 PM PDT 24	3399673740 ps
T71	/workspace/coverage/default/4.chip_tap_straps_prod.859723127			May 09 04:41:44 PM PDT 24	May 09 05:04:46 PM PDT 24	15604525927 ps
T291	/workspace/coverage/default/2.chip_plic_all_irqs_0.1997410092			May 09 04:44:02 PM PDT 24	May 09 04:58:14 PM PDT 24	5518364282 ps
T215	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1544289923			May 09 04:42:29 PM PDT 24	May 09 04:47:58 PM PDT 24	2879517488 ps
T14	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4162947341			May 09 04:19:13 PM PDT 24	May 09 08:01:53 PM PDT 24	75890144904 ps
T695	/workspace/coverage/default/2.chip_sw_aes_smoketest.296019361			May 09 04:42:25 PM PDT 24	May 09 04:46:43 PM PDT 24	2967568256 ps
T868	/workspace/coverage/default/1.chip_sw_aes_idle.598752612			May 09 04:20:01 PM PDT 24	May 09 04:23:25 PM PDT 24	1987624424 ps
T201	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1317742216			May 09 04:43:31 PM PDT 24	May 09 04:52:36 PM PDT 24	5022502556 ps
T119	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2285283167			May 09 04:10:43 PM PDT 24	May 09 04:23:49 PM PDT 24	7955795266 ps
T112	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2669610813			May 09 04:42:14 PM PDT 24	May 09 04:57:28 PM PDT 24	10154218057 ps
T267	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2365630101			May 09 04:43:31 PM PDT 24	May 09 05:04:42 PM PDT 24	7787735080 ps
T207	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4037750140			May 09 04:44:11 PM PDT 24	May 09 04:50:14 PM PDT 24	3033024200 ps
T251	/workspace/coverage/default/0.chip_sival_flash_info_access.4198194839			May 09 04:12:10 PM PDT 24	May 09 04:17:31 PM PDT 24	3465203800 ps
T252	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2210201218			May 09 04:38:35 PM PDT 24	May 09 04:46:36 PM PDT 24	4079850691 ps
T253	/workspace/coverage/default/44.chip_sw_all_escalation_resets.548349213			May 09 04:53:02 PM PDT 24	May 09 05:04:01 PM PDT 24	5051463720 ps
T15	/workspace/coverage/default/0.chip_sw_gpio_smoketest.1958540767			May 09 04:14:10 PM PDT 24	May 09 04:18:21 PM PDT 24	2592145012 ps
T254	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.2718956587			May 09 04:38:32 PM PDT 24	May 09 07:48:09 PM PDT 24	64760044586 ps
T255	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4088577800			May 09 04:18:00 PM PDT 24	May 09 04:25:26 PM PDT 24	4022422666 ps
T138	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1668256324			May 09 04:39:59 PM PDT 24	May 09 05:25:10 PM PDT 24	17235729432 ps
T256	/workspace/coverage/default/3.chip_tap_straps_prod.3062144916			May 09 04:39:26 PM PDT 24	May 09 04:41:40 PM PDT 24	2690001072 ps
T257	/workspace/coverage/default/1.chip_sw_aes_smoketest.2956122946			May 09 04:38:57 PM PDT 24	May 09 04:44:38 PM PDT 24	2607815616 ps
T203	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2693953701			May 09 04:37:41 PM PDT 24	May 09 04:49:10 PM PDT 24	6650171824 ps
T120	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4032559720			May 09 04:09:53 PM PDT 24	May 09 04:17:10 PM PDT 24	5528941144 ps
T683	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1461641812			May 09 04:39:00 PM PDT 24	May 09 04:45:14 PM PDT 24	3737848344 ps
T494	/workspace/coverage/default/59.chip_sw_all_escalation_resets.465070127			May 09 04:48:30 PM PDT 24	May 09 04:57:40 PM PDT 24	5148904416 ps
T113	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3419476082			May 09 04:19:10 PM PDT 24	May 09 04:50:21 PM PDT 24	22680493578 ps
T110	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1383321198			May 09 04:43:05 PM PDT 24	May 09 04:59:45 PM PDT 24	6703585038 ps
T280	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2845872434			May 09 04:48:47 PM PDT 24	May 09 04:55:33 PM PDT 24	4168874172 ps
T157	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1162449814			May 09 04:38:17 PM PDT 24	May 09 04:43:00 PM PDT 24	3506570555 ps
T869	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1266138342			May 09 04:40:13 PM PDT 24	May 09 04:44:00 PM PDT 24	2920708480 ps
T870	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.22291141			May 09 04:09:58 PM PDT 24	May 09 04:23:57 PM PDT 24	4981856260 ps
T321	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3995004818			May 09 04:43:18 PM PDT 24	May 09 04:48:15 PM PDT 24	2658812759 ps
T212	/workspace/coverage/default/1.chip_sw_plic_sw_irq.31982140			May 09 04:20:17 PM PDT 24	May 09 04:26:04 PM PDT 24	2338155508 ps
T186	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.676573842			May 09 04:13:13 PM PDT 24	May 09 05:23:52 PM PDT 24	16075767938 ps
T146	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2366531432			May 09 04:07:47 PM PDT 24	May 09 04:26:49 PM PDT 24	10425766860 ps
T675	/workspace/coverage/default/13.chip_sw_all_escalation_resets.2745308071			May 09 04:45:28 PM PDT 24	May 09 04:55:10 PM PDT 24	5729002520 ps
T208	/workspace/coverage/default/39.chip_sw_all_escalation_resets.914671344			May 09 04:45:55 PM PDT 24	May 09 04:55:26 PM PDT 24	5253020320 ps
T871	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2623495815			May 09 04:41:41 PM PDT 24	May 09 04:50:28 PM PDT 24	6866664388 ps
T684	/workspace/coverage/default/47.chip_sw_all_escalation_resets.4084150741			May 09 04:48:35 PM PDT 24	May 09 04:59:40 PM PDT 24	5936690872 ps
T677	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2183938991			May 09 04:43:50 PM PDT 24	May 09 04:50:02 PM PDT 24	3757724088 ps
T493	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4104794493			May 09 04:12:01 PM PDT 24	May 09 04:33:26 PM PDT 24	8676564626 ps
T66	/workspace/coverage/default/2.chip_tap_straps_rma.3318256918			May 09 04:38:25 PM PDT 24	May 09 04:46:13 PM PDT 24	5412709733 ps
T268	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3268704598			May 09 04:42:50 PM PDT 24	May 09 04:55:01 PM PDT 24	4790567908 ps
T406	/workspace/coverage/default/1.chip_sw_kmac_entropy.4114031473			May 09 04:18:54 PM PDT 24	May 09 04:22:21 PM PDT 24	2567344950 ps
T872	/workspace/coverage/default/0.chip_sw_aes_enc.2122580607			May 09 04:09:25 PM PDT 24	May 09 04:14:11 PM PDT 24	2475367620 ps
T209	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.472382256			May 09 04:53:14 PM PDT 24	May 09 04:59:52 PM PDT 24	3780193600 ps
T679	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3159700550			May 09 04:22:19 PM PDT 24	May 09 04:29:26 PM PDT 24	3109058000 ps
T409	/workspace/coverage/default/0.chip_sw_otbn_randomness.3151453566			May 09 04:09:00 PM PDT 24	May 09 04:23:43 PM PDT 24	5515637020 ps
T682	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1958541163			May 09 04:47:30 PM PDT 24	May 09 04:55:32 PM PDT 24	3781148210 ps
T40	/workspace/coverage/default/2.chip_sw_spi_device_tpm.2245291566			May 09 04:39:09 PM PDT 24	May 09 04:44:42 PM PDT 24	3160542625 ps
T873	/workspace/coverage/default/4.chip_tap_straps_dev.4120668094			May 09 04:36:09 PM PDT 24	May 09 04:38:42 PM PDT 24	2486891584 ps
T874	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2234290752			May 09 04:37:36 PM PDT 24	May 09 04:45:04 PM PDT 24	3898659182 ps
T352	/workspace/coverage/default/45.chip_sw_all_escalation_resets.3585330884			May 09 04:52:44 PM PDT 24	May 09 05:01:53 PM PDT 24	4678966010 ps
T875	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3502677664			May 09 04:20:51 PM PDT 24	May 09 04:27:53 PM PDT 24	4441238416 ps
T80	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1898413741			May 09 04:14:53 PM PDT 24	May 09 07:41:14 PM PDT 24	255179812440 ps
T275	/workspace/coverage/default/93.chip_sw_all_escalation_resets.737384023			May 09 04:41:47 PM PDT 24	May 09 04:51:54 PM PDT 24	5478380290 ps
T270	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.969757945			May 09 04:37:47 PM PDT 24	May 09 04:51:34 PM PDT 24	5557547132 ps
T404	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.690302031			May 09 04:44:42 PM PDT 24	May 09 04:50:40 PM PDT 24	3659575350 ps
T224	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3223736988			May 09 04:10:02 PM PDT 24	May 09 04:11:40 PM PDT 24	2407515258 ps
T319	/workspace/coverage/default/50.chip_sw_all_escalation_resets.2907602290			May 09 04:50:21 PM PDT 24	May 09 04:59:14 PM PDT 24	4166904152 ps
T202	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2096135773			May 09 04:07:35 PM PDT 24	May 09 04:15:48 PM PDT 24	3458675780 ps
T11	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.806256246			May 09 04:07:53 PM PDT 24	May 09 04:11:29 PM PDT 24	2949027180 ps
T265	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.4197690588			May 09 04:08:55 PM PDT 24	May 09 04:18:15 PM PDT 24	3806239458 ps
T876	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.4033320171			May 09 04:19:25 PM PDT 24	May 09 04:31:00 PM PDT 24	8804003088 ps
T877	/workspace/coverage/default/2.chip_sw_uart_smoketest.1829745904			May 09 04:41:25 PM PDT 24	May 09 04:45:39 PM PDT 24	2460681906 ps
T770	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3542165164			May 09 04:41:55 PM PDT 24	May 09 04:49:42 PM PDT 24	4046863606 ps
T171	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.795749422			May 09 04:46:05 PM PDT 24	May 09 04:49:09 PM PDT 24	2731670990 ps
T51	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2946022118			May 09 04:23:34 PM PDT 24	May 09 04:29:07 PM PDT 24	4182507250 ps
T386	/workspace/coverage/default/0.chip_sw_kmac_idle.964937111			May 09 04:13:16 PM PDT 24	May 09 04:17:51 PM PDT 24	2963544220 ps
T274	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1452371785			May 09 04:43:59 PM PDT 24	May 09 05:11:14 PM PDT 24	20431283392 ps
T387	/workspace/coverage/default/1.chip_sw_aes_enc.2233187477			May 09 04:19:29 PM PDT 24	May 09 04:23:43 PM PDT 24	2817015268 ps
T216	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.259695423			May 09 04:36:08 PM PDT 24	May 09 04:39:47 PM PDT 24	2323623088 ps
T178	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3152091519			May 09 04:48:52 PM PDT 24	May 09 04:55:40 PM PDT 24	4495767690 ps
T388	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3321560901			May 09 04:21:03 PM PDT 24	May 09 04:33:30 PM PDT 24	6328306860 ps
T389	/workspace/coverage/default/0.chip_tap_straps_prod.2453272549			May 09 04:10:45 PM PDT 24	May 09 04:13:02 PM PDT 24	2479205076 ps
T266	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.537093344			May 09 04:19:05 PM PDT 24	May 09 04:28:58 PM PDT 24	5293088632 ps
T390	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.321232442			May 09 04:11:23 PM PDT 24	May 09 04:14:38 PM PDT 24	3307900898 ps
T878	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1324884914			May 09 04:10:10 PM PDT 24	May 09 04:14:30 PM PDT 24	3482499451 ps
T879	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2692987232			May 09 04:18:57 PM PDT 24	May 09 04:28:41 PM PDT 24	5311815180 ps
T278	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3392850410			May 09 04:43:56 PM PDT 24	May 09 04:52:58 PM PDT 24	7189087865 ps
T153	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1303817269			May 09 04:18:50 PM PDT 24	May 09 05:45:53 PM PDT 24	45908007750 ps
T880	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3491692049			May 09 04:10:12 PM PDT 24	May 09 04:28:52 PM PDT 24	6771058989 ps
T881	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.838838012			May 09 04:13:08 PM PDT 24	May 09 04:17:29 PM PDT 24	2752217852 ps
T882	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1976669054			May 09 04:21:52 PM PDT 24	May 09 05:11:28 PM PDT 24	31374145104 ps
T142	/workspace/coverage/default/1.chip_plic_all_irqs_10.3776344073			May 09 04:21:02 PM PDT 24	May 09 04:28:11 PM PDT 24	3695073526 ps
T299	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2017179549			May 09 04:19:44 PM PDT 24	May 09 04:28:26 PM PDT 24	5303139769 ps
T883	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.587935587			May 09 04:41:02 PM PDT 24	May 09 05:02:34 PM PDT 24	8650996980 ps
T884	/workspace/coverage/default/1.chip_sw_aes_entropy.148517544			May 09 04:19:51 PM PDT 24	May 09 04:23:37 PM PDT 24	2323741654 ps
T276	/workspace/coverage/default/76.chip_sw_all_escalation_resets.2734729132			May 09 04:45:39 PM PDT 24	May 09 04:53:40 PM PDT 24	5302474792 ps
T294	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2641145565			May 09 04:43:27 PM PDT 24	May 09 04:52:47 PM PDT 24	4730658674 ps
T399	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1116406088			May 09 04:43:54 PM PDT 24	May 09 04:49:57 PM PDT 24	2780989374 ps
T885	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3176741474			May 09 04:39:15 PM PDT 24	May 09 04:45:52 PM PDT 24	3453574052 ps
T886	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2655460075			May 09 04:09:57 PM PDT 24	May 09 04:48:28 PM PDT 24	21396493372 ps
T729	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.1161000350			May 09 04:23:51 PM PDT 24	May 09 04:39:54 PM PDT 24	6373851468 ps
T680	/workspace/coverage/default/67.chip_sw_all_escalation_resets.76104114			May 09 04:47:48 PM PDT 24	May 09 04:58:20 PM PDT 24	5371792468 ps
T273	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2991720830			May 09 04:38:32 PM PDT 24	May 09 04:43:25 PM PDT 24	3277186050 ps
T348	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1863937244			May 09 04:45:06 PM PDT 24	May 09 04:52:32 PM PDT 24	3251585276 ps
T887	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2423175511			May 09 04:18:45 PM PDT 24	May 09 04:24:48 PM PDT 24	5233926334 ps
T888	/workspace/coverage/default/1.chip_sw_example_flash.451095888			May 09 04:17:17 PM PDT 24	May 09 04:20:22 PM PDT 24	2795297180 ps
T187	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.559818275			May 09 04:24:15 PM PDT 24	May 09 04:45:09 PM PDT 24	6496754764 ps
T344	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3600577388			May 09 04:08:06 PM PDT 24	May 09 04:11:08 PM PDT 24	2100177630 ps
T277	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2120622597			May 09 04:42:28 PM PDT 24	May 09 04:47:46 PM PDT 24	4206098864 ps
T37	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.635711931			May 09 04:40:51 PM PDT 24	May 09 04:49:06 PM PDT 24	4861174836 ps
T889	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1276770707			May 09 04:43:28 PM PDT 24	May 09 04:53:49 PM PDT 24	4723626600 ps
T26	/workspace/coverage/default/1.chip_sw_gpio.618958684			May 09 04:18:36 PM PDT 24	May 09 04:25:46 PM PDT 24	4322373416 ps
T188	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3495235699			May 09 04:40:53 PM PDT 24	May 09 05:05:06 PM PDT 24	8093074784 ps
T890	/workspace/coverage/default/0.chip_sw_example_flash.1077485629			May 09 04:07:33 PM PDT 24	May 09 04:10:40 PM PDT 24	2726662970 ps
T307	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3564404277			May 09 04:07:44 PM PDT 24	May 09 04:18:31 PM PDT 24	4892337176 ps
T334	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3477453108			May 09 04:48:47 PM PDT 24	May 09 04:54:38 PM PDT 24	3368842760 ps
T676	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1299921291			May 09 04:44:51 PM PDT 24	May 09 04:50:52 PM PDT 24	3001040620 ps
T891	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2997099348			May 09 04:10:08 PM PDT 24	May 09 04:18:01 PM PDT 24	5393078832 ps
T81	/workspace/coverage/default/14.chip_sw_all_escalation_resets.1066797220			May 09 04:44:25 PM PDT 24	May 09 04:53:54 PM PDT 24	4711447226 ps
T89	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2748952004			May 09 04:38:57 PM PDT 24	May 09 04:45:50 PM PDT 24	3900119912 ps
T90	/workspace/coverage/default/2.chip_sw_aes_masking_off.1416917747			May 09 04:39:28 PM PDT 24	May 09 04:44:22 PM PDT 24	3206748729 ps
T91	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2758944379			May 09 04:38:14 PM PDT 24	May 09 04:47:31 PM PDT 24	3960162800 ps
T27	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1438684846			May 09 04:12:02 PM PDT 24	May 09 04:15:59 PM PDT 24	3107070440 ps
T92	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2848429296			May 09 04:24:46 PM PDT 24	May 09 04:32:47 PM PDT 24	5570798488 ps
T93	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1406327675			May 09 04:41:34 PM PDT 24	May 09 04:46:09 PM PDT 24	3135784544 ps
T94	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.1262199058			May 09 04:21:00 PM PDT 24	May 09 04:33:16 PM PDT 24	5540737160 ps
T95	/workspace/coverage/default/31.chip_sw_all_escalation_resets.1949394620			May 09 04:47:38 PM PDT 24	May 09 04:56:40 PM PDT 24	5391437800 ps
T18	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3908265941			May 09 04:09:45 PM PDT 24	May 09 04:34:54 PM PDT 24	19488291004 ps
T362	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.988126997			May 09 04:46:02 PM PDT 24	May 09 05:09:58 PM PDT 24	7901055068 ps
T281	/workspace/coverage/default/52.chip_sw_all_escalation_resets.1614542359			May 09 04:51:55 PM PDT 24	May 09 05:01:31 PM PDT 24	6429556916 ps
T22	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.263431502			May 09 04:40:04 PM PDT 24	May 09 05:25:41 PM PDT 24	20296680304 ps
T331	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3533554268			May 09 04:46:48 PM PDT 24	May 09 04:53:53 PM PDT 24	3442047932 ps
T378	/workspace/coverage/default/2.chip_sw_example_rom.3424211013			May 09 04:37:32 PM PDT 24	May 09 04:39:24 PM PDT 24	2663954944 ps
T379	/workspace/coverage/default/2.rom_keymgr_functest.195993640			May 09 04:39:41 PM PDT 24	May 09 04:46:37 PM PDT 24	3937874740 ps
T380	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.767856270			May 09 04:46:04 PM PDT 24	May 09 04:53:35 PM PDT 24	3980762160 ps
T179	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.4158206319			May 09 04:47:14 PM PDT 24	May 09 04:52:16 PM PDT 24	3741874200 ps
T131	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1428886143			May 09 04:44:29 PM PDT 24	May 09 04:49:41 PM PDT 24	2716046406 ps
T892	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.446502023			May 09 04:42:32 PM PDT 24	May 09 04:49:35 PM PDT 24	5037139190 ps
T893	/workspace/coverage/default/2.chip_sw_kmac_entropy.3945173876			May 09 04:39:17 PM PDT 24	May 09 04:42:56 PM PDT 24	2639922236 ps
T78	/workspace/coverage/default/2.chip_jtag_mem_access.1764727941			May 09 04:29:17 PM PDT 24	May 09 04:53:57 PM PDT 24	12821037700 ps
T710	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1251992404			May 09 04:48:06 PM PDT 24	May 09 04:55:49 PM PDT 24	3907048376 ps
T12	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.191903046			May 09 04:19:05 PM PDT 24	May 09 04:30:06 PM PDT 24	6576662515 ps
T732	/workspace/coverage/default/49.chip_sw_all_escalation_resets.2879500406			May 09 04:47:50 PM PDT 24	May 09 04:57:15 PM PDT 24	5540327040 ps
T54	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.115158599			May 09 04:07:19 PM PDT 24	May 09 04:10:46 PM PDT 24	2603294862 ps
T373	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1100195132			May 09 04:41:37 PM PDT 24	May 09 04:47:49 PM PDT 24	4431833024 ps
T374	/workspace/coverage/default/63.chip_sw_all_escalation_resets.2746242832			May 09 04:52:50 PM PDT 24	May 09 05:01:59 PM PDT 24	4781936480 ps
T147	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.947651901			May 09 04:45:12 PM PDT 24	May 09 04:51:22 PM PDT 24	3151904908 ps
T325	/workspace/coverage/default/2.chip_sw_hmac_enc.3634553587			May 09 04:44:34 PM PDT 24	May 09 04:49:38 PM PDT 24	2774401720 ps
T132	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1392840547			May 09 04:40:29 PM PDT 24	May 09 04:48:33 PM PDT 24	8574021143 ps
T375	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1841456991			May 09 04:11:20 PM PDT 24	May 09 04:21:14 PM PDT 24	4631579190 ps
T311	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3692475890			May 09 04:45:56 PM PDT 24	May 09 04:57:24 PM PDT 24	5567577890 ps
T151	/workspace/coverage/default/3.chip_sw_all_escalation_resets.4172823304			May 09 04:43:32 PM PDT 24	May 09 04:51:42 PM PDT 24	4538555110 ps
T162	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.176883466			May 09 04:40:49 PM PDT 24	May 09 04:52:05 PM PDT 24	7623441750 ps
T206	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.2825310580			May 09 04:22:13 PM PDT 24	May 09 04:32:45 PM PDT 24	6404633928 ps
T707	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3294747637			May 09 04:13:25 PM PDT 24	May 09 05:07:47 PM PDT 24	20752714718 ps
T101	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2162208927			May 09 04:19:40 PM PDT 24	May 09 04:28:02 PM PDT 24	18132401376 ps
T894	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.143570647			May 09 04:21:13 PM PDT 24	May 09 04:25:07 PM PDT 24	3311233762 ps
T895	/workspace/coverage/default/2.chip_sw_kmac_idle.1059814977			May 09 04:40:18 PM PDT 24	May 09 04:45:09 PM PDT 24	2433912340 ps
T269	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1850783450			May 09 04:17:43 PM PDT 24	May 09 04:35:44 PM PDT 24	9283541572 ps
T102	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.638290386			May 09 04:40:00 PM PDT 24	May 09 04:48:52 PM PDT 24	17706510000 ps
T396	/workspace/coverage/default/0.chip_sw_kmac_app_rom.1174933627			May 09 04:08:29 PM PDT 24	May 09 04:11:55 PM PDT 24	2574117658 ps
T896	/workspace/coverage/default/2.chip_sw_csrng_kat_test.3081798015			May 09 04:40:54 PM PDT 24	May 09 04:44:57 PM PDT 24	2233349260 ps
T897	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1828976768			May 09 04:19:58 PM PDT 24	May 09 04:25:53 PM PDT 24	3417200425 ps
T898	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3456259295			May 09 04:35:20 PM PDT 24	May 09 04:43:33 PM PDT 24	5073427624 ps
T899	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.3747474472			May 09 04:21:00 PM PDT 24	May 09 04:24:34 PM PDT 24	2671431820 ps
T900	/workspace/coverage/default/1.chip_sw_hmac_smoketest.3325287096			May 09 04:38:54 PM PDT 24	May 09 04:46:03 PM PDT 24	3399447000 ps
T901	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.860848310			May 09 04:43:32 PM PDT 24	May 09 04:52:55 PM PDT 24	4453715190 ps
T115	/workspace/coverage/default/1.chip_sw_edn_boot_mode.1763649791			May 09 04:22:14 PM PDT 24	May 09 04:29:56 PM PDT 24	3030697800 ps
T902	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.894166393			May 09 04:11:32 PM PDT 24	May 09 04:22:48 PM PDT 24	4266176680 ps
T200	/workspace/coverage/default/54.chip_sw_all_escalation_resets.3224960556			May 09 04:46:20 PM PDT 24	May 09 04:56:21 PM PDT 24	5908256356 ps
T778	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1164621857			May 09 04:48:04 PM PDT 24	May 09 04:54:59 PM PDT 24	3665386440 ps
T715	/workspace/coverage/default/53.chip_sw_all_escalation_resets.1090356400			May 09 04:48:40 PM PDT 24	May 09 04:58:49 PM PDT 24	4353888110 ps
T903	/workspace/coverage/default/2.chip_sw_example_manufacturer.4288233667			May 09 04:35:50 PM PDT 24	May 09 04:39:44 PM PDT 24	2698358888 ps
T164	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2964142500			May 09 04:40:51 PM PDT 24	May 09 04:43:51 PM PDT 24	2402360957 ps
T70	/workspace/coverage/default/3.chip_tap_straps_rma.1162116215			May 09 04:42:09 PM PDT 24	May 09 04:45:31 PM PDT 24	3204747630 ps
T312	/workspace/coverage/default/1.chip_sw_uart_tx_rx.1076378735			May 09 04:17:55 PM PDT 24	May 09 04:25:59 PM PDT 24	4435525752 ps
T126	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.4270359320			May 09 04:41:31 PM PDT 24	May 09 04:49:32 PM PDT 24	4020368760 ps
T82	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.4106278335			May 09 04:09:06 PM PDT 24	May 09 04:14:12 PM PDT 24	2679456571 ps
T904	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.389900801			May 09 04:08:04 PM PDT 24	May 09 07:52:29 PM PDT 24	78184481425 ps
T19	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4011228415			May 09 04:41:29 PM PDT 24	May 09 04:58:37 PM PDT 24	17562094132 ps
T905	/workspace/coverage/default/2.chip_sw_aes_idle.796610099			May 09 04:38:28 PM PDT 24	May 09 04:43:50 PM PDT 24	2983812544 ps
T678	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1997520975			May 09 04:44:54 PM PDT 24	May 09 04:55:31 PM PDT 24	5292743374 ps
T736	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.817477537			May 09 04:52:44 PM PDT 24	May 09 04:59:55 PM PDT 24	3749689800 ps
T711	/workspace/coverage/default/17.chip_sw_all_escalation_resets.4193756640			May 09 04:43:53 PM PDT 24	May 09 04:51:45 PM PDT 24	5777291378 ps
T158	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1807917460			May 09 04:12:08 PM PDT 24	May 09 04:41:58 PM PDT 24	34379573232 ps