Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3320	1			T75	8		T76	1		T77	17
all_values[1]	3274	1			T75	11		T76	3		T77	20
all_values[2]	3269	1			T75	8		T76	1		T77	22
all_values[3]	3342	1			T75	10		T77	22		T381	6
all_values[4]	3348	1			T75	9		T76	4		T77	19
all_values[5]	3382	1			T75	6		T76	2		T77	25
all_values[6]	3329	1			T75	15		T76	2		T77	21
all_values[7]	3321	1			T75	9		T76	3		T77	26
all_values[8]	3303	1			T75	5		T77	21		T410	2
all_values[9]	3358	1			T75	13		T77	18		T410	1
all_values[10]	3417	1			T75	13		T77	28		T416	2
all_values[11]	3397	1			T75	10		T76	1		T77	18
all_values[12]	3324	1			T75	8		T76	2		T77	18
all_values[13]	3302	1			T75	11		T76	2		T77	21
all_values[14]	3348	1			T75	8		T76	5		T77	18
all_values[15]	3294	1			T75	8		T77	22		T416	4
all_values[16]	3328	1			T75	8		T77	16		T410	2
all_values[17]	3346	1			T75	14		T76	1		T77	16
all_values[18]	3289	1			T75	7		T76	1		T77	27
all_values[19]	3382	1			T75	9		T76	1		T77	18
all_values[20]	3307	1			T75	9		T77	21		T416	3
all_values[21]	3382	1			T75	8		T76	2		T77	21
all_values[22]	3308	1			T75	6		T77	16		T410	1
all_values[23]	3295	1			T75	12		T76	3		T77	20
all_values[24]	3383	1			T75	14		T76	3		T77	22
all_values[25]	3337	1			T75	15		T76	2		T77	13
all_values[26]	3358	1			T75	9		T76	1		T77	16
all_values[27]	3335	1			T75	12		T76	1		T77	25
all_values[28]	3397	1			T75	12		T76	1		T77	25
all_values[29]	3362	1			T75	9		T76	3		T77	18
all_values[30]	3311	1			T75	9		T76	3		T77	9
all_values[31]	3301	1			T75	7		T77	24		T416	2
all_values[32]	3321	1			T75	9		T76	1		T77	20
all_values[33]	3239	1			T75	5		T76	1		T77	10
all_values[34]	3406	1			T75	15		T76	3		T77	25
all_values[35]	3345	1			T75	11		T77	20		T410	2
all_values[36]	3377	1			T75	11		T76	1		T77	14
all_values[37]	3307	1			T75	10		T77	27		T416	4
all_values[38]	3351	1			T75	10		T77	11		T416	3
all_values[39]	3413	1			T75	12		T76	2		T77	28
all_values[40]	3269	1			T75	18		T76	2		T77	21
all_values[41]	3272	1			T75	12		T76	2		T77	23
all_values[42]	3381	1			T75	7		T76	1		T77	19
all_values[43]	3296	1			T75	6		T76	2		T77	19
all_values[44]	3250	1			T75	11		T77	21		T416	2
all_values[45]	3299	1			T75	5		T77	23		T410	1
all_values[46]	3338	1			T75	13		T76	2		T77	22
all_values[47]	3219	1			T75	7		T76	1		T77	15
all_values[48]	3337	1			T75	10		T76	1		T77	18
all_values[49]	3285	1			T75	5		T76	3		T77	15
all_values[50]	3364	1			T75	6		T76	2		T77	23
all_values[51]	3386	1			T75	9		T76	2		T77	22
all_values[52]	3270	1			T75	14		T76	2		T77	19
all_values[53]	3356	1			T75	12		T76	1		T77	24
all_values[54]	3362	1			T75	9		T77	22		T416	2
all_values[55]	3333	1			T75	7		T76	2		T77	26
all_values[56]	3468	1			T75	6		T76	2		T77	19
all_values[57]	3417	1			T75	13		T77	24		T416	1
all_values[58]	3325	1			T75	8		T76	1		T77	26
all_values[59]	3306	1			T75	8		T76	2		T77	26
all_values[60]	3382	1			T75	10		T76	1		T77	24
all_values[61]	3422	1			T75	13		T77	19		T416	2
all_values[62]	3354	1			T75	10		T77	20		T416	1
all_values[63]	3296	1			T75	17		T76	3		T77	16