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 LINE       60
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T76,T139,T410
1	1	Covered	T1,T2,T3

 LINE       72
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T81,T86,T87
1	0	Not Covered

 LINE       79
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T81,T86,T87
0	1	0	Covered	T77,T411,T412
1	0	0	Covered	T81,T86,T87

 LINE       121
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T77,T411,T412
0	1	0	Covered	T76,T139,T413
1	0	0	Covered	T76,T139,T410

 LINE       5740
 EXPRESSION (mio_periph_insel_0_we & mio_periph_insel_regwen_0_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T135,T136,T360
1	1	Covered	T15,T26,T27

 LINE       5772
 EXPRESSION (mio_periph_insel_1_we & mio_periph_insel_regwen_1_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T328,T135,T360
1	1	Covered	T15,T26,T27

 LINE       5804
 EXPRESSION (mio_periph_insel_2_we & mio_periph_insel_regwen_2_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T326,T135,T401
1	1	Covered	T15,T26,T27

 LINE       5836
 EXPRESSION (mio_periph_insel_3_we & mio_periph_insel_regwen_3_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T122,T326,T135
1	1	Covered	T15,T26,T27

 LINE       5868
 EXPRESSION (mio_periph_insel_4_we & mio_periph_insel_regwen_4_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T122,T135
1	1	Covered	T15,T26,T27

 LINE       5900
 EXPRESSION (mio_periph_insel_5_we & mio_periph_insel_regwen_5_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T135,T136,T329
1	1	Covered	T15,T26,T27

 LINE       5932
 EXPRESSION (mio_periph_insel_6_we & mio_periph_insel_regwen_6_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T326,T135,T136
1	1	Covered	T15,T26,T27

 LINE       5964
 EXPRESSION (mio_periph_insel_7_we & mio_periph_insel_regwen_7_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T328,T135,T360
1	1	Covered	T15,T26,T27

 LINE       5996
 EXPRESSION (mio_periph_insel_8_we & mio_periph_insel_regwen_8_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T122,T135
1	1	Covered	T15,T26,T24

 LINE       6028
 EXPRESSION (mio_periph_insel_9_we & mio_periph_insel_regwen_9_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T329,T360,T327
1	1	Covered	T15,T26,T52

 LINE       6060
 EXPRESSION (mio_periph_insel_10_we & mio_periph_insel_regwen_10_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T24,T122
1	1	Covered	T15,T26,T28

 LINE       6092
 EXPRESSION (mio_periph_insel_11_we & mio_periph_insel_regwen_11_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T122,T326,T135
1	1	Covered	T15,T26,T52

 LINE       6124
 EXPRESSION (mio_periph_insel_12_we & mio_periph_insel_regwen_12_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T328,T326
1	1	Covered	T15,T26,T52

 LINE       6156
 EXPRESSION (mio_periph_insel_13_we & mio_periph_insel_regwen_13_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T122,T135
1	1	Covered	T15,T26,T24

 LINE       6188
 EXPRESSION (mio_periph_insel_14_we & mio_periph_insel_regwen_14_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T135,T136
1	1	Covered	T15,T26,T52

 LINE       6220
 EXPRESSION (mio_periph_insel_15_we & mio_periph_insel_regwen_15_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T122,T135
1	1	Covered	T15,T26,T24

 LINE       6252
 EXPRESSION (mio_periph_insel_16_we & mio_periph_insel_regwen_16_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T328,T326,T135
1	1	Covered	T15,T26,T52

 LINE       6284
 EXPRESSION (mio_periph_insel_17_we & mio_periph_insel_regwen_17_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T122,T326,T329
1	1	Covered	T15,T26,T52

 LINE       6316
 EXPRESSION (mio_periph_insel_18_we & mio_periph_insel_regwen_18_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T328,T326
1	1	Covered	T15,T26,T24

 LINE       6348
 EXPRESSION (mio_periph_insel_19_we & mio_periph_insel_regwen_19_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T122,T135,T327
1	1	Covered	T15,T26,T52

 LINE       6380
 EXPRESSION (mio_periph_insel_20_we & mio_periph_insel_regwen_20_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T328,T135,T136
1	1	Covered	T15,T26,T52

 LINE       6412
 EXPRESSION (mio_periph_insel_21_we & mio_periph_insel_regwen_21_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T122,T326,T135
1	1	Covered	T15,T26,T52

 LINE       6444
 EXPRESSION (mio_periph_insel_22_we & mio_periph_insel_regwen_22_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T135,T360
1	1	Covered	T1,T2,T3

 LINE       6476
 EXPRESSION (mio_periph_insel_23_we & mio_periph_insel_regwen_23_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T24,T122
1	1	Covered	T1,T2,T3

 LINE       6508
 EXPRESSION (mio_periph_insel_24_we & mio_periph_insel_regwen_24_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T122,T326,T360
1	1	Covered	T1,T2,T3

 LINE       6540
 EXPRESSION (mio_periph_insel_25_we & mio_periph_insel_regwen_25_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T122,T326
1	1	Covered	T15,T26,T52

 LINE       6572
 EXPRESSION (mio_periph_insel_26_we & mio_periph_insel_regwen_26_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T122,T326,T135
1	1	Covered	T15,T26,T52

 LINE       6604
 EXPRESSION (mio_periph_insel_27_we & mio_periph_insel_regwen_27_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T135,T136,T361
1	1	Covered	T15,T26,T52

 LINE       6636
 EXPRESSION (mio_periph_insel_28_we & mio_periph_insel_regwen_28_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T122,T135
1	1	Covered	T15,T26,T24

 LINE       6668
 EXPRESSION (mio_periph_insel_29_we & mio_periph_insel_regwen_29_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T136,T361,T414
1	1	Covered	T15,T26,T52

 LINE       6700
 EXPRESSION (mio_periph_insel_30_we & mio_periph_insel_regwen_30_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T122,T326,T135
1	1	Covered	T15,T26,T52

 LINE       6732
 EXPRESSION (mio_periph_insel_31_we & mio_periph_insel_regwen_31_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T122,T328
1	1	Covered	T15,T26,T24

 LINE       6764
 EXPRESSION (mio_periph_insel_32_we & mio_periph_insel_regwen_32_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T122,T135
1	1	Covered	T265,T266,T308

 LINE       6796
 EXPRESSION (mio_periph_insel_33_we & mio_periph_insel_regwen_33_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T326,T135
1	1	Covered	T265,T266,T308

 LINE       6828
 EXPRESSION (mio_periph_insel_34_we & mio_periph_insel_regwen_34_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T326,T135
1	1	Covered	T24,T295,T345

 LINE       6860
 EXPRESSION (mio_periph_insel_35_we & mio_periph_insel_regwen_35_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T326,T135
1	1	Covered	T24,T295,T345

 LINE       6892
 EXPRESSION (mio_periph_insel_36_we & mio_periph_insel_regwen_36_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T135,T360,T361
1	1	Covered	T270,T52,T347

 LINE       6924
 EXPRESSION (mio_periph_insel_37_we & mio_periph_insel_regwen_37_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T326,T135,T329
1	1	Covered	T270,T52,T347

 LINE       6956
 EXPRESSION (mio_periph_insel_38_we & mio_periph_insel_regwen_38_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T135,T123,T125
1	1	Covered	T10,T11,T52

 LINE       6988
 EXPRESSION (mio_periph_insel_39_we & mio_periph_insel_regwen_39_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T328,T135,T360
1	1	Covered	T10,T11,T52

 LINE       7020
 EXPRESSION (mio_periph_insel_40_we & mio_periph_insel_regwen_40_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T326,T135,T361
1	1	Covered	T10,T11,T52

 LINE       7052
 EXPRESSION (mio_periph_insel_41_we & mio_periph_insel_regwen_41_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T328,T135,T361
1	1	Covered	T10,T11,T12

 LINE       7084
 EXPRESSION (mio_periph_insel_42_we & mio_periph_insel_regwen_42_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T122,T135
1	1	Covered	T1,T2,T3

 LINE       7116
 EXPRESSION (mio_periph_insel_43_we & mio_periph_insel_regwen_43_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T135,T329
1	1	Covered	T1,T2,T3

 LINE       7148
 EXPRESSION (mio_periph_insel_44_we & mio_periph_insel_regwen_44_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T122,T360,T361
1	1	Covered	T177,T307,T91

 LINE       7180
 EXPRESSION (mio_periph_insel_45_we & mio_periph_insel_regwen_45_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T24,T122
1	1	Covered	T13,T14,T294

 LINE       7212
 EXPRESSION (mio_periph_insel_46_we & mio_periph_insel_regwen_46_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T135,T360,T361
1	1	Covered	T40,T52,T24

 LINE       7244
 EXPRESSION (mio_periph_insel_47_we & mio_periph_insel_regwen_47_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T122,T135,T360
1	1	Covered	T52,T24,T415

 LINE       7276
 EXPRESSION (mio_periph_insel_48_we & mio_periph_insel_regwen_48_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T328,T135
1	1	Covered	T52,T382,T122

 LINE       7308
 EXPRESSION (mio_periph_insel_49_we & mio_periph_insel_regwen_49_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T328,T135,T136
1	1	Covered	T52,T24,T122

 LINE       7340
 EXPRESSION (mio_periph_insel_50_we & mio_periph_insel_regwen_50_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T122,T328
1	1	Covered	T20,T252,T273

 LINE       7372
 EXPRESSION (mio_periph_insel_51_we & mio_periph_insel_regwen_51_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T122,T135
1	1	Covered	T20,T217,T218

 LINE       7404
 EXPRESSION (mio_periph_insel_52_we & mio_periph_insel_regwen_52_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T122,T326
1	1	Covered	T20,T21,T252

 LINE       7436
 EXPRESSION (mio_periph_insel_53_we & mio_periph_insel_regwen_53_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T328,T326
1	1	Covered	T20,T21,T252

 LINE       7468
 EXPRESSION (mio_periph_insel_54_we & mio_periph_insel_regwen_54_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T122,T326,T135
1	1	Covered	T20,T21,T252

 LINE       7500
 EXPRESSION (mio_periph_insel_55_we & mio_periph_insel_regwen_55_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T135,T136,T350
1	1	Covered	T20,T252,T273

 LINE       7532
 EXPRESSION (mio_periph_insel_56_we & mio_periph_insel_regwen_56_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T328,T326,T135
1	1	Covered	T17,T23,T52

 LINE       8927
 EXPRESSION (mio_outsel_0_we & mio_outsel_regwen_0_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T27

 LINE       8959
 EXPRESSION (mio_outsel_1_we & mio_outsel_regwen_1_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T14,T15

 LINE       8991
 EXPRESSION (mio_outsel_2_we & mio_outsel_regwen_2_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T27

 LINE       9023
 EXPRESSION (mio_outsel_3_we & mio_outsel_regwen_3_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T27

 LINE       9055
 EXPRESSION (mio_outsel_4_we & mio_outsel_regwen_4_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T46,T15,T26

 LINE       9087
 EXPRESSION (mio_outsel_5_we & mio_outsel_regwen_5_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T177,T15,T26

 LINE       9119
 EXPRESSION (mio_outsel_6_we & mio_outsel_regwen_6_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T27

 LINE       9151
 EXPRESSION (mio_outsel_7_we & mio_outsel_regwen_7_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T265,T266

 LINE       9183
 EXPRESSION (mio_outsel_8_we & mio_outsel_regwen_8_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T265,T266

 LINE       9215
 EXPRESSION (mio_outsel_9_we & mio_outsel_regwen_9_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T12

 LINE       9247
 EXPRESSION (mio_outsel_10_we & mio_outsel_regwen_10_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T12

 LINE       9279
 EXPRESSION (mio_outsel_11_we & mio_outsel_regwen_11_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T181,T182

 LINE       9311
 EXPRESSION (mio_outsel_12_we & mio_outsel_regwen_12_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T12

 LINE       9343
 EXPRESSION (mio_outsel_13_we & mio_outsel_regwen_13_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       9375
 EXPRESSION (mio_outsel_14_we & mio_outsel_regwen_14_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       9407
 EXPRESSION (mio_outsel_15_we & mio_outsel_regwen_15_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T15,T11

 LINE       9439
 EXPRESSION (mio_outsel_16_we & mio_outsel_regwen_16_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T21,T15,T37

 LINE       9471
 EXPRESSION (mio_outsel_17_we & mio_outsel_regwen_17_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T28

 LINE       9503
 EXPRESSION (mio_outsel_18_we & mio_outsel_regwen_18_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T21,T15,T26

 LINE       9535
 EXPRESSION (mio_outsel_19_we & mio_outsel_regwen_19_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T269

 LINE       9567
 EXPRESSION (mio_outsel_20_we & mio_outsel_regwen_20_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T270,T26

 LINE       9599
 EXPRESSION (mio_outsel_21_we & mio_outsel_regwen_21_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T270,T26

 LINE       9631
 EXPRESSION (mio_outsel_22_we & mio_outsel_regwen_22_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T416,T417,T418

 LINE       9663
 EXPRESSION (mio_outsel_23_we & mio_outsel_regwen_23_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T394,T372,T419

 LINE       9695
 EXPRESSION (mio_outsel_24_we & mio_outsel_regwen_24_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T382,T394,T393

 LINE       9727
 EXPRESSION (mio_outsel_25_we & mio_outsel_regwen_25_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       9759
 EXPRESSION (mio_outsel_26_we & mio_outsel_regwen_26_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       9791
 EXPRESSION (mio_outsel_27_we & mio_outsel_regwen_27_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T416,T420,T421

 LINE       9823
 EXPRESSION (mio_outsel_28_we & mio_outsel_regwen_28_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T422,T423,T424

 LINE       9855
 EXPRESSION (mio_outsel_29_we & mio_outsel_regwen_29_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       9887
 EXPRESSION (mio_outsel_30_we & mio_outsel_regwen_30_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T395,T382,T394

 LINE       9919
 EXPRESSION (mio_outsel_31_we & mio_outsel_regwen_31_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T21,T15,T26

 LINE       9951
 EXPRESSION (mio_outsel_32_we & mio_outsel_regwen_32_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T269

 LINE       9983
 EXPRESSION (mio_outsel_33_we & mio_outsel_regwen_33_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T269

 LINE       10015
 EXPRESSION (mio_outsel_34_we & mio_outsel_regwen_34_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T269

 LINE       10047
 EXPRESSION (mio_outsel_35_we & mio_outsel_regwen_35_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T28

 LINE       10079
 EXPRESSION (mio_outsel_36_we & mio_outsel_regwen_36_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T28

 LINE       10111
 EXPRESSION (mio_outsel_37_we & mio_outsel_regwen_37_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T28

 LINE       10143
 EXPRESSION (mio_outsel_38_we & mio_outsel_regwen_38_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T28

 LINE       10175
 EXPRESSION (mio_outsel_39_we & mio_outsel_regwen_39_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T28

 LINE       10207
 EXPRESSION (mio_outsel_40_we & mio_outsel_regwen_40_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T21,T15,T26

 LINE       10239
 EXPRESSION (mio_outsel_41_we & mio_outsel_regwen_41_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T21,T15,T26

 LINE       10271
 EXPRESSION (mio_outsel_42_we & mio_outsel_regwen_42_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T28

 LINE       10303
 EXPRESSION (mio_outsel_43_we & mio_outsel_regwen_43_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T28

 LINE       10335
 EXPRESSION (mio_outsel_44_we & mio_outsel_regwen_44_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T28

 LINE       10367
 EXPRESSION (mio_outsel_45_we & mio_outsel_regwen_45_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T28

 LINE       10399
 EXPRESSION (mio_outsel_46_we & mio_outsel_regwen_46_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T26,T28

 LINE       11797
 EXPRESSION (mio_pad_attr_0_we & mio_pad_attr_regwen_0_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T372,T425,T426

 LINE       11950
 EXPRESSION (mio_pad_attr_1_we & mio_pad_attr_regwen_1_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T427,T428,T429

 LINE       12103
 EXPRESSION (mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T35

 LINE       12256
 EXPRESSION (mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T382,T393,T430

 LINE       12409
 EXPRESSION (mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T422,T431,T432

 LINE       12562
 EXPRESSION (mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T433,T434,T435

 LINE       12715
 EXPRESSION (mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T372,T436,T437

 LINE       12868
 EXPRESSION (mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T40,T41,T42

 LINE       13021
 EXPRESSION (mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T382,T393,T438

 LINE       13174
 EXPRESSION (mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T35

 LINE       13327
 EXPRESSION (mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T12

 LINE       13480
 EXPRESSION (mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T372,T439,T440

 LINE       13633
 EXPRESSION (mio_pad_attr_12_we & mio_pad_attr_regwen_12_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T12

 LINE       13786
 EXPRESSION (mio_pad_attr_13_we & mio_pad_attr_regwen_13_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T35

 LINE       13939
 EXPRESSION (mio_pad_attr_14_we & mio_pad_attr_regwen_14_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T35

 LINE       14092
 EXPRESSION (mio_pad_attr_15_we & mio_pad_attr_regwen_15_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T35

 LINE       14245
 EXPRESSION (mio_pad_attr_16_we & mio_pad_attr_regwen_16_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T393,T441,T427

 LINE       14398
 EXPRESSION (mio_pad_attr_17_we & mio_pad_attr_regwen_17_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T442,T443,T444

 LINE       14551
 EXPRESSION (mio_pad_attr_18_we & mio_pad_attr_regwen_18_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T445,T423,T446

 LINE       14704
 EXPRESSION (mio_pad_attr_19_we & mio_pad_attr_regwen_19_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T447,T448,T449

 LINE       14857
 EXPRESSION (mio_pad_attr_20_we & mio_pad_attr_regwen_20_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T450,T440,T451

 LINE       15010
 EXPRESSION (mio_pad_attr_21_we & mio_pad_attr_regwen_21_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T416,T372,T452

 LINE       15163
 EXPRESSION (mio_pad_attr_22_we & mio_pad_attr_regwen_22_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T43,T44,T45

 LINE       15316
 EXPRESSION (mio_pad_attr_23_we & mio_pad_attr_regwen_23_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T43,T44,T45

 LINE       15469
 EXPRESSION (mio_pad_attr_24_we & mio_pad_attr_regwen_24_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T43,T44,T45

 LINE       15622
 EXPRESSION (mio_pad_attr_25_we & mio_pad_attr_regwen_25_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       15775
 EXPRESSION (mio_pad_attr_26_we & mio_pad_attr_regwen_26_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T419,T427,T451

 LINE       15928
 EXPRESSION (mio_pad_attr_27_we & mio_pad_attr_regwen_27_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T392,T450,T453

 LINE       16081
 EXPRESSION (mio_pad_attr_28_we & mio_pad_attr_regwen_28_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T454,T455,T456

 LINE       16234
 EXPRESSION (mio_pad_attr_29_we & mio_pad_attr_regwen_29_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T372,T457,T458

 LINE       16387
 EXPRESSION (mio_pad_attr_30_we & mio_pad_attr_regwen_30_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T422,T423,T434

 LINE       16540
 EXPRESSION (mio_pad_attr_31_we & mio_pad_attr_regwen_31_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T459,T460,T461

 LINE       16693
 EXPRESSION (mio_pad_attr_32_we & mio_pad_attr_regwen_32_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T462,T463,T460

 LINE       16846
 EXPRESSION (mio_pad_attr_33_we & mio_pad_attr_regwen_33_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T464,T465,T466

 LINE       16999
 EXPRESSION (mio_pad_attr_34_we & mio_pad_attr_regwen_34_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T393,T442,T427

 LINE       17152
 EXPRESSION (mio_pad_attr_35_we & mio_pad_attr_regwen_35_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T446,T467,T468

 LINE       17305
 EXPRESSION (mio_pad_attr_36_we & mio_pad_attr_regwen_36_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T434,T435,T469

 LINE       17458
 EXPRESSION (mio_pad_attr_37_we & mio_pad_attr_regwen_37_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T417,T470,T471

 LINE       17611
 EXPRESSION (mio_pad_attr_38_we & mio_pad_attr_regwen_38_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T382,T450,T472

 LINE       17764
 EXPRESSION (mio_pad_attr_39_we & mio_pad_attr_regwen_39_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T382,T473,T434

 LINE       17917
 EXPRESSION (mio_pad_attr_40_we & mio_pad_attr_regwen_40_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T474,T470,T475

 LINE       18070
 EXPRESSION (mio_pad_attr_41_we & mio_pad_attr_regwen_41_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T417,T476,T437

 LINE       18223
 EXPRESSION (mio_pad_attr_42_we & mio_pad_attr_regwen_42_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T477,T434,T478