Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142646	1			T68	8		T69	36		T70	4
values[2]	9859	1			T75	1		T412	2		T503	4
values[3]	3706	1			T413	86		T422	3		T737	1
values[4]	1969	1			T413	71		T422	2		T434	65
values[5]	1241	1			T413	30		T422	2		T434	61
values[6]	997	1			T413	26		T422	4		T434	65
values[7]	708	1			T413	18		T422	2		T434	28
values[8]	511	1			T413	1		T422	2		T434	18
values[9]	416	1			T422	7		T434	6		T738	2
values[10]	350	1			T422	14		T738	1		T739	28
values[11]	312	1			T422	7		T738	1		T739	8
values[12]	328	1			T422	4		T738	1		T739	11
values[13]	325	1			T422	1		T738	1		T739	12
values[14]	291	1			T422	2		T738	1		T739	7
values[15]	262	1			T422	1		T738	1		T739	12
values[16]	293	1			T422	1		T738	1		T739	22
values[17]	301	1			T422	1		T738	1		T739	9
values[18]	294	1			T422	2		T738	1		T739	20
values[19]	332	1			T422	1		T738	1		T739	19
values[20]	264	1			T422	1		T738	1		T739	11
values[21]	242	1			T422	3		T738	1		T739	9
values[22]	284	1			T422	1		T738	1		T739	10
values[23]	273	1			T422	3		T738	1		T739	10
values[24]	262	1			T422	1		T738	1		T739	18
values[25]	280	1			T422	1		T738	1		T739	30
values[26]	292	1			T422	2		T738	1		T739	20
values[27]	244	1			T422	5		T738	1		T739	17
values[28]	251	1			T422	5		T738	1		T739	8
values[29]	245	1			T422	3		T738	1		T739	7
values[30]	237	1			T422	2		T738	1		T739	13
values[31]	306	1			T422	2		T738	1		T739	21
values[32]	316	1			T422	2		T738	1		T739	11
values[33]	302	1			T422	1		T738	1		T739	19
values[34]	323	1			T422	1		T738	1		T739	38
values[35]	207	1			T422	2		T738	1		T739	6
values[36]	244	1			T422	8		T738	1		T739	11
values[37]	225	1			T422	2		T738	1		T739	8
values[38]	263	1			T422	1		T738	1		T739	20
values[39]	232	1			T422	5		T738	1		T739	13
values[40]	275	1			T422	6		T738	1		T739	13
values[41]	246	1			T422	5		T738	1		T739	14
values[42]	220	1			T422	3		T738	1		T739	7
values[43]	251	1			T422	8		T738	1		T739	18
values[44]	310	1			T422	3		T738	1		T739	33
values[45]	240	1			T422	4		T738	1		T739	6
values[46]	231	1			T422	3		T738	1		T739	5
values[47]	239	1			T422	1		T738	1		T739	2
values[48]	227	1			T422	2		T738	1		T739	20
values[49]	212	1			T422	2		T738	1		T739	5
values[50]	257	1			T422	1		T738	1		T739	5
values[51]	219	1			T422	1		T738	1		T739	4
values[52]	216	1			T422	7		T738	1		T739	10
values[53]	230	1			T422	2		T738	1		T739	7
values[54]	188	1			T422	3		T738	1		T739	6
values[55]	209	1			T422	1		T738	1		T739	13
values[56]	225	1			T422	2		T738	1		T739	5
values[57]	218	1			T422	1		T738	1		T739	8
values[58]	184	1			T422	1		T738	1		T739	16
values[59]	193	1			T422	2		T738	1		T739	5
values[60]	186	1			T422	3		T738	1		T739	5
values[61]	178	1			T422	2		T738	1		T739	7
values[62]	154	1			T422	1		T738	1		T739	9
values[63]	179	1			T422	3		T738	1		T739	8
values[64]	136	1			T422	4		T738	1		T739	9
values[65]	96	1			T422	2		T738	1		T739	8
values[66]	117	1			T422	7		T738	1		T739	4
values[67]	110	1			T422	3		T738	1		T739	4
values[68]	111	1			T422	2		T738	1		T739	5
values[69]	100	1			T422	1		T738	1		T739	3
values[70]	89	1			T422	5		T738	1		T739	9
values[71]	105	1			T422	10		T738	1		T739	8
values[72]	71	1			T422	5		T738	1		T739	4
values[73]	70	1			T422	1		T738	1		T739	4
values[74]	73	1			T422	3		T738	1		T739	2
values[75]	64	1			T422	4		T738	1		T740	1
values[76]	71	1			T422	2		T738	1		T740	1
values[77]	68	1			T422	2		T738	1		T740	1
values[78]	50	1			T422	2		T738	1		T740	1
values[79]	70	1			T422	2		T738	1		T740	1
values[80]	49	1			T422	1		T738	1		T740	1
values[81]	46	1			T422	2		T738	1		T740	1
values[82]	68	1			T422	1		T738	1		T740	1
values[83]	52	1			T422	3		T738	1		T740	1
values[84]	82	1			T422	4		T738	1		T740	1
values[85]	65	1			T422	1		T738	1		T740	1
values[86]	72	1			T422	1		T738	1		T740	1
values[87]	78	1			T422	2		T738	1		T740	1
values[88]	78	1			T422	3		T738	1		T740	1
values[89]	89	1			T422	12		T738	1		T740	1
values[90]	96	1			T422	3		T738	1		T740	1
values[91]	82	1			T422	8		T738	1		T740	1
values[92]	89	1			T422	9		T738	1		T740	1
values[93]	68	1			T422	9		T738	1		T740	1
values[94]	89	1			T422	7		T738	1		T740	1
values[95]	52	1			T422	4		T738	1		T740	1
values[96]	62	1			T422	3		T738	1		T740	1
values[97]	66	1			T422	8		T738	1		T740	1
values[98]	74	1			T422	5		T738	1		T740	1
values[99]	68	1			T422	11		T738	1		T740	1
values[100]	86	1			T422	15		T738	1		T740	1
values[101]	69	1			T422	8		T738	1		T740	1
values[102]	70	1			T422	2		T738	1		T740	1
values[103]	79	1			T422	2		T738	2		T740	1
values[104]	70	1			T422	5		T738	1		T740	1
values[105]	85	1			T422	7		T738	1		T740	1
values[106]	63	1			T422	2		T738	2		T740	1
values[107]	63	1			T422	2		T738	2		T740	1
values[108]	65	1			T422	7		T738	2		T740	1
values[109]	57	1			T422	3		T738	1		T740	1
values[110]	84	1			T422	3		T738	4		T740	1
values[111]	68	1			T422	5		T738	1		T740	3
values[112]	72	1			T422	4		T738	2		T740	2
values[113]	54	1			T422	5		T738	1		T740	3
values[114]	64	1			T422	6		T738	2		T740	3
values[115]	67	1			T422	3		T738	1		T740	4
values[116]	64	1			T422	6		T738	1		T740	1
values[117]	61	1			T422	4		T738	4		T740	2
values[118]	63	1			T422	5		T738	1		T740	1
values[119]	54	1			T422	3		T738	2		T740	2
values[120]	54	1			T422	6		T738	2		T740	1
values[121]	68	1			T422	2		T738	2		T740	2
values[122]	77	1			T422	4		T738	3		T740	1
values[123]	70	1			T422	7		T738	3		T740	2
values[124]	58	1			T422	7		T738	1		T740	1
values[125]	78	1			T422	10		T738	3		T740	4
values[126]	128	1			T422	9		T738	1		T740	4
values[127]	836	1			T422	40		T738	24		T740	33
values[128]	6655	1			T422	22		T738	258		T740	337

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	164388	1			T69	19		T70	16		T76	6
values[2]	4913	1			T412	1		T503	8		T427	3
values[3]	2360	1			T413	18		T741	1		T398	20
values[4]	1827	1			T413	5		T741	1		T398	19
values[5]	1466	1			T741	1		T398	4		T609	6
values[6]	1326	1			T741	1		T398	2		T609	17
values[7]	1163	1			T741	1		T609	11		T742	3
values[8]	923	1			T741	1		T609	2		T742	2
values[9]	877	1			T741	1		T609	7		T742	4
values[10]	767	1			T741	1		T609	12		T742	1
values[11]	629	1			T741	1		T609	7		T742	1
values[12]	598	1			T741	1		T609	16		T742	3
values[13]	515	1			T741	1		T609	7		T742	7
values[14]	450	1			T741	1		T609	1		T742	9
values[15]	416	1			T741	1		T609	2		T742	3
values[16]	485	1			T741	1		T609	2		T742	1
values[17]	450	1			T741	1		T609	3		T742	1
values[18]	420	1			T741	1		T609	6		T742	2
values[19]	343	1			T741	1		T609	9		T742	3
values[20]	330	1			T741	1		T609	18		T742	4
values[21]	280	1			T741	1		T609	26		T742	5
values[22]	259	1			T741	1		T609	25		T742	1
values[23]	255	1			T741	1		T609	28		T742	2
values[24]	256	1			T741	1		T609	28		T742	4
values[25]	240	1			T741	1		T609	27		T742	2
values[26]	220	1			T741	1		T609	12		T742	2
values[27]	167	1			T741	1		T609	8		T742	1
values[28]	156	1			T741	1		T609	5		T742	1
values[29]	165	1			T741	1		T609	4		T742	4
values[30]	162	1			T741	1		T609	5		T742	1
values[31]	163	1			T741	1		T609	10		T742	2
values[32]	164	1			T741	1		T609	21		T742	5
values[33]	110	1			T741	1		T609	10		T742	3
values[34]	119	1			T741	1		T609	15		T742	3
values[35]	151	1			T741	1		T609	18		T742	2
values[36]	125	1			T741	1		T609	20		T742	1
values[37]	140	1			T741	1		T609	23		T742	2
values[38]	153	1			T741	1		T609	31		T742	3
values[39]	132	1			T741	1		T609	21		T742	2
values[40]	97	1			T741	1		T609	3		T742	1
values[41]	96	1			T741	1		T742	3		T738	1
values[42]	85	1			T741	1		T742	3		T738	1
values[43]	93	1			T741	1		T742	4		T738	1
values[44]	92	1			T741	1		T742	3		T738	1
values[45]	76	1			T741	1		T742	1		T738	1
values[46]	69	1			T741	1		T742	2		T738	1
values[47]	86	1			T741	1		T742	1		T738	2
values[48]	111	1			T741	1		T742	3		T738	1
values[49]	127	1			T741	1		T742	2		T738	1
values[50]	113	1			T741	1		T742	4		T738	1
values[51]	73	1			T741	1		T742	2		T738	1
values[52]	95	1			T741	1		T742	2		T738	1
values[53]	98	1			T741	1		T742	2		T738	1
values[54]	88	1			T741	1		T742	3		T738	1
values[55]	74	1			T741	1		T742	1		T738	1
values[56]	74	1			T741	1		T742	1		T738	1
values[57]	62	1			T741	1		T742	2		T738	1
values[58]	60	1			T741	1		T742	2		T738	1
values[59]	86	1			T741	1		T742	5		T738	1
values[60]	70	1			T741	1		T742	1		T738	1
values[61]	76	1			T741	1		T742	4		T738	1
values[62]	75	1			T741	1		T742	5		T738	1
values[63]	63	1			T741	1		T742	1		T738	1
values[64]	65	1			T741	1		T742	1		T738	1
values[65]	76	1			T741	1		T742	2		T738	1
values[66]	72	1			T741	1		T742	2		T738	1
values[67]	77	1			T741	1		T742	1		T738	1
values[68]	65	1			T741	1		T742	3		T738	1
values[69]	90	1			T741	1		T742	2		T738	1
values[70]	92	1			T741	1		T742	6		T738	1
values[71]	92	1			T741	1		T742	1		T738	1
values[72]	113	1			T741	1		T742	1		T738	1
values[73]	91	1			T741	1		T742	2		T738	1
values[74]	97	1			T741	2		T742	1		T738	1
values[75]	97	1			T741	1		T742	1		T738	1
values[76]	97	1			T741	1		T742	3		T738	1
values[77]	107	1			T741	1		T742	5		T738	1
values[78]	109	1			T741	1		T742	7		T738	1
values[79]	86	1			T741	1		T742	6		T738	1
values[80]	94	1			T741	1		T742	2		T738	1
values[81]	87	1			T741	1		T742	3		T738	1
values[82]	112	1			T741	1		T742	8		T738	1
values[83]	109	1			T741	1		T742	6		T738	1
values[84]	97	1			T741	1		T742	6		T738	1
values[85]	99	1			T741	1		T742	7		T738	1
values[86]	102	1			T741	1		T742	1		T738	1
values[87]	120	1			T741	1		T742	3		T738	1
values[88]	103	1			T741	1		T742	3		T738	1
values[89]	78	1			T741	1		T742	3		T738	1
values[90]	89	1			T741	6		T742	3		T738	1
values[91]	97	1			T741	2		T742	2		T738	1
values[92]	117	1			T741	7		T742	6		T738	1
values[93]	110	1			T741	3		T742	6		T738	1
values[94]	101	1			T741	1		T742	3		T738	1
values[95]	103	1			T741	1		T742	1		T738	1
values[96]	90	1			T741	2		T742	3		T738	2
values[97]	112	1			T741	5		T742	3		T738	1
values[98]	131	1			T741	3		T742	4		T738	2
values[99]	117	1			T741	3		T742	2		T738	1
values[100]	126	1			T741	5		T742	2		T738	2
values[101]	100	1			T741	5		T742	4		T738	1
values[102]	105	1			T741	3		T742	5		T738	3
values[103]	113	1			T741	3		T742	2		T738	2
values[104]	97	1			T741	1		T742	8		T738	4
values[105]	108	1			T741	1		T742	6		T738	1
values[106]	147	1			T741	2		T742	5		T738	4
values[107]	134	1			T741	4		T742	4		T738	1
values[108]	129	1			T741	3		T742	2		T738	2
values[109]	126	1			T741	3		T742	4		T738	3
values[110]	128	1			T741	3		T742	6		T738	4
values[111]	122	1			T741	2		T742	7		T738	1
values[112]	137	1			T741	1		T742	2		T738	5
values[113]	133	1			T741	2		T742	4		T738	2
values[114]	115	1			T741	1		T742	7		T738	2
values[115]	114	1			T741	4		T742	8		T738	3
values[116]	143	1			T741	3		T742	11		T738	5
values[117]	149	1			T741	1		T742	8		T738	3
values[118]	123	1			T741	1		T742	2		T738	3
values[119]	113	1			T741	1		T742	3		T738	2
values[120]	123	1			T741	1		T742	4		T738	3
values[121]	145	1			T741	3		T742	4		T738	1
values[122]	144	1			T741	1		T742	4		T738	3
values[123]	139	1			T741	3		T742	2		T738	4
values[124]	196	1			T741	1		T742	10		T738	1
values[125]	390	1			T741	4		T742	37		T738	1
values[126]	698	1			T741	16		T742	57		T738	6
values[127]	2054	1			T741	112		T742	26		T738	112
values[128]	3730	1			T741	190		T742	4		T738	280

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143230	1			T68	5		T69	18		T70	11
values[2]	10440	1			T70	1		T412	1		T503	4
values[3]	4071	1			T503	1		T399	1		T441	1
values[4]	2294	1			T609	17		T434	1		T484	9
values[5]	1423	1			T609	6		T434	1		T484	4
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