Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	95.37	93.88	95.58		94.49	97.38	99.54

Total tests in report: 2783

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.41	40.41	45.69	45.69	43.17	43.17	31.95	31.95			58.29	58.29	62.96	62.96	0.39	0.39	/workspace/coverage/default/69.chip_sw_all_escalation_resets.3838771843
52.67	12.27	57.00	11.31	60.81	17.64	37.06	5.12			70.13	11.83	89.63	26.67	1.41	1.02	/workspace/coverage/cover_reg_top/4.chip_csr_rw.2289291365
57.89	5.22	67.99	10.99	68.28	7.47	40.07	3.01			79.97	9.85	89.63	0.00	1.41	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.103714386
62.48	4.59	67.99	0.00	68.31	0.03	40.07	0.00			79.97	0.00	89.63	0.00	28.93	27.52	/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1135158161
66.27	3.78	74.01	6.02	69.55	1.24	43.23	3.16			80.03	0.06	89.63	0.00	41.14	12.21	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.252184519
69.83	3.56	74.01	0.00	69.55	0.00	43.23	0.00			80.03	0.00	89.63	0.00	62.52	21.38	/workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2678206151
72.76	2.93	74.01	0.00	69.55	0.00	60.79	17.56			80.03	0.00	89.63	0.00	62.57	0.05	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2126023205
75.14	2.38	79.40	5.39	73.39	3.84	64.29	3.50			81.56	1.52	89.63	0.00	62.57	0.00	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.384342049
77.39	2.25	79.40	0.00	73.67	0.28	64.29	0.00			81.62	0.07	89.63	0.00	75.70	13.14	/workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1203457304
79.53	2.14	81.58	2.18	76.55	2.87	68.27	3.97			83.72	2.10	89.81	0.19	77.24	1.54	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.958490637
81.04	1.51	84.30	2.72	79.56	3.01	68.78	0.51			86.38	2.65	90.00	0.19	77.24	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.728855304
82.33	1.29	84.34	0.03	79.56	0.00	76.47	7.69			86.38	0.00	90.00	0.00	77.24	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.4272167195
83.41	1.08	85.88	1.54	80.73	1.17	77.06	0.60			87.68	1.30	91.85	1.85	77.26	0.02	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1863061179
84.38	0.97	85.88	0.00	81.63	0.90	77.06	0.00			87.77	0.09	91.85	0.00	82.09	4.83	/workspace/coverage/cover_reg_top/14.xbar_stress_all.3374780385
85.29	0.91	87.26	1.39	82.53	0.90	79.11	2.04			88.92	1.15	91.85	0.00	82.09	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.501026134
86.17	0.87	88.02	0.75	82.71	0.19	79.12	0.02			89.12	0.21	95.93	4.07	82.09	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4199621216
87.03	0.86	89.23	1.21	83.74	1.03	80.90	1.77			90.28	1.16	95.93	0.00	82.09	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.1379396365
87.79	0.76	89.23	0.00	83.74	0.00	80.90	0.00			90.28	0.00	95.93	0.00	86.66	4.57	/workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2348285910
88.39	0.60	89.99	0.76	84.24	0.50	82.46	1.56			91.08	0.80	95.93	0.00	86.66	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.444121363
88.98	0.59	91.40	1.41	84.29	0.05	83.28	0.82			91.08	0.00	95.93	0.00	87.92	1.26	/workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3617961936
89.55	0.57	91.40	0.00	84.29	0.00	83.28	0.00			91.08	0.00	95.93	0.00	91.32	3.40	/workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3869932198
90.11	0.56	91.54	0.14	84.41	0.12	86.03	2.75			91.26	0.17	96.11	0.19	91.32	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.18721489
90.63	0.52	91.55	0.01	87.09	2.68	86.03	0.00			91.26	0.00	96.11	0.00	91.74	0.42	/workspace/coverage/cover_reg_top/23.chip_tl_errors.2015821572
91.09	0.46	92.33	0.77	87.96	0.87	86.42	0.40			91.96	0.71	96.11	0.00	91.74	0.00	/workspace/coverage/default/2.chip_sw_gpio_smoketest.1122771337
91.54	0.45	92.33	0.00	88.00	0.03	86.42	0.00			91.96	0.00	96.11	0.00	94.43	2.69	/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.4058855808
91.96	0.42	92.93	0.60	89.18	1.18	86.52	0.10			92.40	0.44	96.11	0.00	94.63	0.20	/workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2219917460
92.27	0.31	92.94	0.01	89.18	0.01	88.35	1.83			92.40	0.00	96.11	0.00	94.67	0.04	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3950148752
92.54	0.26	92.99	0.05	89.25	0.06	89.44	1.10			92.40	0.00	96.11	0.00	95.04	0.38	/workspace/coverage/default/0.chip_sw_alert_test.2051366236
92.79	0.25	92.99	0.00	89.37	0.12	89.44	0.00			92.40	0.00	96.11	0.00	96.40	1.36	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.421987923
93.02	0.23	92.99	0.01	89.43	0.06	89.44	0.00			92.41	0.01	96.11	0.00	97.72	1.32	/workspace/coverage/cover_reg_top/63.xbar_random_large_delays.1001696640
93.25	0.23	93.08	0.09	89.48	0.05	90.64	1.19			92.43	0.02	96.11	0.00	97.73	0.01	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.671430067
93.44	0.19	93.11	0.03	89.99	0.52	90.68	0.04			93.00	0.57	96.11	0.00	97.73	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2255129871
93.61	0.17	93.32	0.22	90.32	0.33	91.14	0.46			93.00	0.00	96.11	0.00	97.73	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.834659231
93.75	0.14	93.64	0.32	90.48	0.16	91.43	0.29			93.09	0.09	96.11	0.00	97.73	0.00	/workspace/coverage/default/1.rom_e2e_smoke.888430883
93.88	0.13	93.88	0.24	90.68	0.19	91.45	0.01			93.42	0.32	96.11	0.00	97.73	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1682725818
93.99	0.11	94.09	0.22	90.85	0.17	91.61	0.16			93.53	0.12	96.11	0.00	97.73	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.898882598
94.09	0.10	94.12	0.02	91.14	0.29	91.62	0.01			93.84	0.30	96.11	0.00	97.73	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3380985928
94.19	0.10	94.16	0.04	91.20	0.06	91.88	0.26			93.86	0.02	96.30	0.19	97.73	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1746359676
94.27	0.08	94.16	0.00	91.20	0.00	92.39	0.51			93.86	0.00	96.30	0.00	97.73	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2364511342
94.36	0.08	94.23	0.08	91.20	0.00	92.80	0.41			93.87	0.01	96.30	0.00	97.73	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.840623379
94.43	0.08	94.23	0.00	91.68	0.48	92.80	0.00			93.87	0.00	96.30	0.00	97.73	0.00	/workspace/coverage/cover_reg_top/15.chip_tl_errors.1003352449
94.51	0.08	94.34	0.11	91.74	0.06	93.01	0.21			93.94	0.07	96.30	0.00	97.73	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.4213115015
94.58	0.07	94.45	0.11	91.89	0.15	93.12	0.11			94.03	0.08	96.30	0.00	97.73	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.360828500
94.66	0.07	94.45	0.00	91.94	0.05	93.12	0.00			94.04	0.02	96.30	0.00	98.11	0.38	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3723191363
94.73	0.07	94.45	0.00	91.94	0.00	93.54	0.41			94.04	0.00	96.30	0.00	98.11	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3685987568
94.79	0.06	94.45	0.00	91.94	0.00	93.92	0.38			94.04	0.00	96.30	0.00	98.11	0.00	/workspace/coverage/default/1.chip_sw_edn_auto_mode.2816610795
94.85	0.06	94.49	0.04	91.98	0.05	93.95	0.03			94.09	0.05	96.48	0.19	98.12	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1298081674
94.90	0.04	94.49	0.00	91.98	0.00	94.21	0.26			94.09	0.00	96.48	0.00	98.12	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3955588974
94.94	0.04	94.51	0.02	92.01	0.03	94.21	0.00			94.11	0.02	96.67	0.19	98.13	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.1917624377
94.98	0.04	94.52	0.01	92.03	0.02	94.21	0.00			94.13	0.02	96.85	0.19	98.14	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2708060954
95.02	0.04	94.52	0.01	92.04	0.01	94.22	0.01			94.14	0.01	97.04	0.19	98.16	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.4215237254
95.06	0.04	94.53	0.01	92.05	0.01	94.23	0.01			94.15	0.01	97.22	0.19	98.17	0.01	/workspace/coverage/default/49.chip_sw_all_escalation_resets.1374333333
95.09	0.04	94.53	0.00	92.26	0.21	94.23	0.00			94.15	0.00	97.22	0.00	98.18	0.01	/workspace/coverage/cover_reg_top/7.chip_tl_errors.2844889916
95.13	0.04	94.53	0.00	92.26	0.00	94.45	0.22			94.15	0.00	97.22	0.00	98.18	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2057418853
95.17	0.04	94.53	0.00	92.27	0.01	94.45	0.00			94.15	0.00	97.22	0.00	98.39	0.21	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1542864441
95.20	0.04	94.61	0.08	92.34	0.07	94.45	0.01			94.21	0.06	97.22	0.00	98.39	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.26573244
95.24	0.03	94.61	0.00	92.53	0.19	94.45	0.00			94.21	0.00	97.22	0.00	98.39	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1327869097
95.27	0.03	94.61	0.00	92.53	0.00	94.64	0.19			94.21	0.00	97.22	0.00	98.39	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1311088367
95.30	0.03	94.61	0.00	92.53	0.00	94.64	0.00			94.21	0.00	97.41	0.19	98.39	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.387510446
95.32	0.03	94.61	0.00	92.66	0.12	94.64	0.00			94.24	0.03	97.41	0.00	98.39	0.00	/workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3482800283
95.35	0.02	94.68	0.07	92.71	0.05	94.65	0.01			94.26	0.02	97.41	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2030563695
95.37	0.02	94.71	0.03	92.80	0.09	94.65	0.01			94.28	0.02	97.41	0.00	98.39	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.2280788383
95.40	0.02	94.72	0.01	92.84	0.04	94.73	0.08			94.30	0.02	97.41	0.00	98.39	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1349458416
95.42	0.02	94.75	0.03	92.88	0.04	94.78	0.05			94.32	0.02	97.41	0.00	98.39	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4045117188
95.44	0.02	94.82	0.07	92.93	0.05	94.78	0.00			94.34	0.02	97.41	0.00	98.39	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1408249983
95.47	0.02	94.89	0.07	92.98	0.05	94.78	0.00			94.35	0.02	97.41	0.00	98.39	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2518702056
95.49	0.02	94.94	0.05	93.02	0.04	94.79	0.01			94.38	0.02	97.41	0.00	98.39	0.00	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2700110772
95.51	0.02	94.95	0.01	93.04	0.02	94.87	0.07			94.40	0.02	97.41	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2687905639
95.53	0.02	94.96	0.01	93.04	0.00	94.97	0.10			94.40	0.00	97.41	0.00	98.39	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.2872822841
95.54	0.02	94.96	0.00	93.04	0.00	95.07	0.10			94.40	0.00	97.41	0.00	98.39	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3977509654
95.56	0.02	94.96	0.00	93.09	0.05	95.07	0.00			94.40	0.00	97.41	0.00	98.44	0.05	/workspace/coverage/cover_reg_top/22.xbar_stress_all.687373504
95.58	0.02	94.96	0.00	93.18	0.09	95.07	0.00			94.40	0.00	97.41	0.00	98.44	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.2415782454
95.59	0.01	94.96	0.00	93.18	0.00	95.07	0.00			94.40	0.00	97.41	0.00	98.52	0.08	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3482067208
95.60	0.01	94.96	0.00	93.18	0.00	95.07	0.00			94.40	0.00	97.41	0.00	98.59	0.07	/workspace/coverage/cover_reg_top/21.xbar_random.2634013545
95.61	0.01	94.96	0.00	93.22	0.04	95.07	0.00			94.43	0.03	97.41	0.00	98.59	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1112600621
95.62	0.01	94.96	0.00	93.22	0.01	95.13	0.06			94.43	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.4272920298
95.64	0.01	94.97	0.01	93.29	0.06	95.13	0.00			94.43	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.3394940283
95.65	0.01	94.97	0.00	93.35	0.06	95.13	0.00			94.43	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/76.xbar_stress_all.4108014369
95.66	0.01	94.97	0.00	93.35	0.00	95.19	0.06			94.43	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.317777246
95.67	0.01	94.97	0.00	93.41	0.06	95.19	0.00			94.43	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.315245405
95.68	0.01	94.97	0.00	93.44	0.03	95.19	0.00			94.43	0.00	97.41	0.00	98.61	0.02	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1861407963
95.68	0.01	94.99	0.03	93.45	0.01	95.20	0.01			94.45	0.02	97.41	0.00	98.61	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.502491374
95.69	0.01	94.99	0.00	93.45	0.00	95.25	0.05			94.45	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.4194261588
95.70	0.01	94.99	0.00	93.45	0.00	95.25	0.00			94.45	0.00	97.41	0.00	98.66	0.05	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3950257410
95.71	0.01	94.99	0.00	93.45	0.00	95.30	0.04			94.45	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2850771381
95.72	0.01	95.02	0.03	93.45	0.00	95.30	0.01			94.45	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.4101559584
95.72	0.01	95.03	0.01	93.46	0.01	95.31	0.01			94.46	0.02	97.41	0.00	98.66	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.489867923
95.73	0.01	95.03	0.00	93.50	0.04	95.31	0.00			94.46	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.882503683
95.73	0.01	95.03	0.00	93.51	0.01	95.31	0.00			94.46	0.00	97.41	0.00	98.68	0.02	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.4273021374
95.74	0.01	95.03	0.00	93.51	0.00	95.31	0.00			94.46	0.00	97.41	0.00	98.72	0.04	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.852333952
95.75	0.01	95.03	0.00	93.53	0.02	95.31	0.00			94.46	0.00	97.41	0.00	98.73	0.01	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.4702793
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95.96	0.01	95.08	0.00	93.77	0.00	95.48	0.00			94.47	0.00	97.41	0.00	99.54	0.01	/workspace/coverage/default/92.chip_sw_all_escalation_resets.3929092259
95.96	0.01	95.08	0.00	93.78	0.01	95.48	0.00			94.47	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.3963546992
95.96	0.01	95.08	0.00	93.80	0.01	95.48	0.00			94.47	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1116109424
95.96	0.01	95.08	0.00	93.81	0.01	95.48	0.00			94.47	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3681516913
95.97	0.01	95.08	0.00	93.82	0.01	95.48	0.00			94.47	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_gpio.1716071671
95.97	0.01	95.08	0.00	93.83	0.01	95.48	0.00			94.47	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.3292338430
95.97	0.01	95.08	0.01	93.83	0.00	95.49	0.01			94.47	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/25.chip_sw_all_escalation_resets.841529811
95.97	0.01	95.08	0.00	93.83	0.00	95.50	0.01			94.47	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.2516368655
95.97	0.01	95.08	0.00	93.83	0.00	95.51	0.01			94.47	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1647654148
95.97	0.01	95.08	0.00	93.83	0.00	95.52	0.01			94.47	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1390884153
95.98	0.01	95.08	0.00	93.83	0.00	95.53	0.01			94.47	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.788242928
95.98	0.01	95.08	0.00	93.83	0.00	95.54	0.01			94.47	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3065096995
95.98	0.01	95.08	0.00	93.83	0.01	95.54	0.01			94.47	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1479446252
95.98	0.01	95.08	0.00	93.83	0.00	95.54	0.00			94.48	0.01	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.989923448
95.98	0.01	95.08	0.00	93.83	0.00	95.54	0.00			94.49	0.01	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2792673473
95.98	0.01	95.08	0.00	93.83	0.00	95.54	0.00			94.49	0.01	97.41	0.00	99.54	0.00	/workspace/coverage/default/3.chip_tap_straps_dev.3649005221
95.98	0.01	95.08	0.00	93.84	0.01	95.54	0.00			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3408287649
95.99	0.01	95.08	0.00	93.85	0.01	95.54	0.00			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.4157816130
95.99	0.01	95.08	0.00	93.85	0.01	95.54	0.00			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3181300306
95.99	0.01	95.08	0.01	93.86	0.01	95.54	0.00			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3358916880
95.99	0.01	95.09	0.01	93.86	0.00	95.54	0.00			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.3891566354
95.99	0.01	95.09	0.00	93.86	0.00	95.55	0.01			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3417247130
95.99	0.01	95.09	0.00	93.86	0.00	95.56	0.01			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.601300973
95.99	0.01	95.09	0.00	93.86	0.00	95.56	0.01			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_flash_init.4105809329
95.99	0.01	95.09	0.00	93.86	0.00	95.57	0.01			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1441450203
95.99	0.01	95.09	0.00	93.86	0.01	95.57	0.00			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.1976763652
95.99	0.01	95.09	0.00	93.86	0.01	95.57	0.00			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.3989544094
96.00	0.01	95.09	0.00	93.87	0.01	95.57	0.00			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.586897072
96.00	0.01	95.09	0.00	93.87	0.01	95.57	0.00			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.379944850
96.00	0.01	95.09	0.00	93.88	0.01	95.57	0.00			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2541923940
96.00	0.01	95.09	0.00	93.88	0.01	95.57	0.00			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.423184537
96.00	0.01	95.10	0.01	93.88	0.00	95.57	0.00			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.794375098
96.00	0.01	95.10	0.00	93.88	0.00	95.57	0.01			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1096553756
96.00	0.01	95.10	0.00	93.88	0.00	95.57	0.01			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3495548279
96.00	0.01	95.10	0.00	93.88	0.00	95.57	0.01			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1272888311
96.00	0.01	95.10	0.00	93.88	0.00	95.58	0.01			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1491467646
96.00	0.01	95.10	0.00	93.88	0.00	95.58	0.01			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.233253834
96.00	0.01	95.10	0.00	93.88	0.00	95.58	0.01			94.49	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1131827277

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.2584740359
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3984040720
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2163552305
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.515999516
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3428782314
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1714355024
/workspace/coverage/cover_reg_top/0.chip_tl_errors.3887164257
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1397089336
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.695551612
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3196079291
/workspace/coverage/cover_reg_top/0.xbar_error_random.356936270
/workspace/coverage/cover_reg_top/0.xbar_random.670010121
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3198344276
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1956956316
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1174758313
/workspace/coverage/cover_reg_top/0.xbar_same_source.2901654076
/workspace/coverage/cover_reg_top/0.xbar_smoke.4004003382
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1384811490
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2773515571
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1427369590
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2176605959
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3317216309
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1056204115
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3383145393
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2361543291
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2798515839
/workspace/coverage/cover_reg_top/1.chip_csr_rw.4221039714
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.408988473
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2150949032
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3532490395
/workspace/coverage/cover_reg_top/1.chip_tl_errors.3797441821
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.3753418087
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2261873617
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3760373249
/workspace/coverage/cover_reg_top/1.xbar_error_random.614040217
/workspace/coverage/cover_reg_top/1.xbar_random.1985983794
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2817274716
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3550624257
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.227193986
/workspace/coverage/cover_reg_top/1.xbar_same_source.2873259948
/workspace/coverage/cover_reg_top/1.xbar_smoke.3235467753
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1136037613
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3983735016
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1680155751
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3623018264
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.257284233
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1331874022
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.178103094
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2178680730
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2015891226
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3658381490
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2716160570
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1233488856
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1833710899
/workspace/coverage/cover_reg_top/10.xbar_error_random.2280622100
/workspace/coverage/cover_reg_top/10.xbar_random.1008237240
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3889141989
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2117659395
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.346213177
/workspace/coverage/cover_reg_top/10.xbar_same_source.2658293157
/workspace/coverage/cover_reg_top/10.xbar_smoke.2382085829
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1681780225
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2676455102
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.4084985558
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3833230605
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.924402347
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.797624554
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.424250613
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2217863344
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1419395367
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1870023282
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.710379689
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.634659842
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1340665879
/workspace/coverage/cover_reg_top/11.xbar_error_random.1205139568
/workspace/coverage/cover_reg_top/11.xbar_random.1143229514
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.187107461
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2954287669
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3073836320
/workspace/coverage/cover_reg_top/11.xbar_same_source.2287706854
/workspace/coverage/cover_reg_top/11.xbar_smoke.2100590113
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1453569786
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3458700666
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.309193179
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3095377491
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1781083879
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.621267306
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1848610323
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1980178378
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2756420243
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.259720496
/workspace/coverage/cover_reg_top/12.chip_tl_errors.105471043
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1730920067
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3512506082
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3814919424
/workspace/coverage/cover_reg_top/12.xbar_error_random.1443458143
/workspace/coverage/cover_reg_top/12.xbar_random.3006546168
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1800187457
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.691552703
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2257442490
/workspace/coverage/cover_reg_top/12.xbar_same_source.1430413103
/workspace/coverage/cover_reg_top/12.xbar_smoke.1070046942
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3629805439
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2314875348
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.628880251
/workspace/coverage/cover_reg_top/12.xbar_stress_all.4201293627
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.420111343
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2907489953
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1157093460
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2503739047
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2371018584
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1102270664
/workspace/coverage/cover_reg_top/13.chip_tl_errors.2614740133
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.4244038918
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.907892449
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2276401792
/workspace/coverage/cover_reg_top/13.xbar_error_random.714441441
/workspace/coverage/cover_reg_top/13.xbar_random.88181325
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.73408803
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3580332899
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3036878850
/workspace/coverage/cover_reg_top/13.xbar_same_source.3045834312
/workspace/coverage/cover_reg_top/13.xbar_smoke.995925560
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3614938193
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1025674576
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3223042095
/workspace/coverage/cover_reg_top/13.xbar_stress_all.3146568687
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3548034902
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2123043679
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.683217247
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1556226169
/workspace/coverage/cover_reg_top/14.chip_csr_rw.3587154079
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.283464513
/workspace/coverage/cover_reg_top/14.chip_tl_errors.3356016389
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.4223333484
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3991032431
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.800138083
/workspace/coverage/cover_reg_top/14.xbar_error_random.2280563780
/workspace/coverage/cover_reg_top/14.xbar_random.2694308195
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2128035058
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2000559790
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3117381141
/workspace/coverage/cover_reg_top/14.xbar_same_source.2628813810
/workspace/coverage/cover_reg_top/14.xbar_smoke.2683535822
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3301194967
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.3137577629
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1806225539
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.86136679
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3333912284
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.117434661
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3797690681
/workspace/coverage/cover_reg_top/15.chip_csr_rw.2406733944
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3182054478
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.3759877657
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3109057432
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/workspace/coverage/default/71.chip_sw_all_escalation_resets.3630856983
/workspace/coverage/default/72.chip_sw_all_escalation_resets.4005397398
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1312828344
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1649611888
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1155560795
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2849084989
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2243889134
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3673003923
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3102405880
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2137643236
/workspace/coverage/default/77.chip_sw_all_escalation_resets.4197549870
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2515869600
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1368429930
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3880096497
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.795943458
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2758993949
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3767126755
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2052902404
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1056769006
/workspace/coverage/default/80.chip_sw_all_escalation_resets.233905585
/workspace/coverage/default/81.chip_sw_all_escalation_resets.766609330
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1444290721
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1327622522
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1553445973
/workspace/coverage/default/83.chip_sw_all_escalation_resets.4150943465
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2306653833
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2992091004
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.176085098
/workspace/coverage/default/85.chip_sw_all_escalation_resets.1878675064
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2038281173
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1227964712
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2409074885
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.524409836
/workspace/coverage/default/88.chip_sw_all_escalation_resets.800087294
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.863259111
/workspace/coverage/default/89.chip_sw_all_escalation_resets.546063467
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.559865643
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2957072639
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3297759676
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3452311686
/workspace/coverage/default/90.chip_sw_all_escalation_resets.836308259
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1338897390
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1839437052
/workspace/coverage/default/96.chip_sw_all_escalation_resets.932486399
/workspace/coverage/default/97.chip_sw_all_escalation_resets.4229960847
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1803698959
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1872142277
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2256706719
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.4249612126
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2572058309
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2612300480
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1439676087
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1929707361
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1163722323
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1217340779

---

Total test records in report: 2783

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3955588974			May 12 03:28:26 PM PDT 24	May 12 03:42:39 PM PDT 24	7506304282 ps
T2	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3945834041			May 12 03:33:28 PM PDT 24	May 12 03:53:33 PM PDT 24	8468338580 ps
T3	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.444121363			May 12 03:32:48 PM PDT 24	May 12 03:43:04 PM PDT 24	4492733736 ps
T52	/workspace/coverage/default/2.chip_sw_rv_timer_irq.3287878749			May 12 03:34:44 PM PDT 24	May 12 03:38:18 PM PDT 24	3196264110 ps
T12	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.898882598			May 12 03:15:25 PM PDT 24	May 12 03:20:43 PM PDT 24	2543621064 ps
T56	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2402128476			May 12 03:41:12 PM PDT 24	May 12 03:49:17 PM PDT 24	7899166780 ps
T4	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.671430067			May 12 03:21:06 PM PDT 24	May 12 06:13:25 PM PDT 24	58922874204 ps
T84	/workspace/coverage/default/1.chip_sw_power_idle_load.1066809541			May 12 03:30:16 PM PDT 24	May 12 03:40:41 PM PDT 24	3945628550 ps
T85	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1258639527			May 12 03:44:51 PM PDT 24	May 12 03:51:09 PM PDT 24	3617036948 ps
T58	/workspace/coverage/default/69.chip_sw_all_escalation_resets.3838771843			May 12 03:48:40 PM PDT 24	May 12 03:57:54 PM PDT 24	5162376668 ps
T100	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2700110772			May 12 03:42:55 PM PDT 24	May 12 03:54:37 PM PDT 24	4232169936 ps
T59	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1130235276			May 12 03:44:15 PM PDT 24	May 12 03:54:44 PM PDT 24	4778673352 ps
T101	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1553445973			May 12 03:49:33 PM PDT 24	May 12 03:55:55 PM PDT 24	3647738640 ps
T102	/workspace/coverage/default/1.chip_sw_aes_entropy.3936356912			May 12 03:25:49 PM PDT 24	May 12 03:31:06 PM PDT 24	3341544534 ps
T332	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1929605942			May 12 03:49:46 PM PDT 24	May 12 03:57:00 PM PDT 24	3607591816 ps
T5	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.11458913			May 12 03:45:26 PM PDT 24	May 12 03:54:47 PM PDT 24	6184558557 ps
T291	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.60202438			May 12 03:21:17 PM PDT 24	May 12 03:34:51 PM PDT 24	3987675148 ps
T77	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.958490637			May 12 03:25:44 PM PDT 24	May 12 03:43:32 PM PDT 24	9723418580 ps
T13	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2009873244			May 12 03:20:47 PM PDT 24	May 12 03:30:17 PM PDT 24	3694337336 ps
T121	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.834659231			May 12 03:16:35 PM PDT 24	May 12 03:23:27 PM PDT 24	4603332968 ps
T38	/workspace/coverage/default/1.chip_sw_spi_device_tpm.1847864298			May 12 03:21:03 PM PDT 24	May 12 03:26:19 PM PDT 24	3188411716 ps
T103	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.201372668			May 12 03:25:12 PM PDT 24	May 12 03:33:36 PM PDT 24	17811717564 ps
T347	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.914860551			May 12 03:46:12 PM PDT 24	May 12 03:53:29 PM PDT 24	3643718056 ps
T348	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.2516368655			May 12 03:13:52 PM PDT 24	May 12 03:17:36 PM PDT 24	3102591984 ps
T44	/workspace/coverage/default/0.chip_tap_straps_rma.840623379			May 12 03:15:57 PM PDT 24	May 12 03:23:07 PM PDT 24	5595690376 ps
T114	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1336247713			May 12 03:29:27 PM PDT 24	May 12 03:38:53 PM PDT 24	4711476360 ps
T119	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2640948858			May 12 03:35:08 PM PDT 24	May 12 03:53:26 PM PDT 24	5501943690 ps
T349	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2556396430			May 12 03:46:14 PM PDT 24	May 12 03:52:15 PM PDT 24	3645592956 ps
T174	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3502583363			May 12 03:17:45 PM PDT 24	May 12 03:25:52 PM PDT 24	4374096760 ps
T220	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.4110891342			May 12 03:23:37 PM PDT 24	May 12 03:29:02 PM PDT 24	2812038450 ps
T175	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2052902404			May 12 03:42:33 PM PDT 24	May 12 04:09:20 PM PDT 24	7754013848 ps
T230	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1056769006			May 12 03:49:15 PM PDT 24	May 12 03:55:31 PM PDT 24	4144496992 ps
T140	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1546435892			May 12 03:39:43 PM PDT 24	May 12 03:43:45 PM PDT 24	2719656584 ps
T118	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3402110987			May 12 03:15:11 PM PDT 24	May 12 04:01:46 PM PDT 24	10747308806 ps
T41	/workspace/coverage/default/1.rom_e2e_smoke.888430883			May 12 03:36:01 PM PDT 24	May 12 04:50:33 PM PDT 24	17027468796 ps
T133	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.137902296			May 12 03:14:30 PM PDT 24	May 12 03:18:48 PM PDT 24	2716866778 ps
T14	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.923194005			May 12 03:32:41 PM PDT 24	May 12 03:37:12 PM PDT 24	3185001818 ps
T57	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.18721489			May 12 03:22:17 PM PDT 24	May 12 04:43:12 PM PDT 24	42808956767 ps
T109	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3950148752			May 12 03:29:15 PM PDT 24	May 12 03:51:17 PM PDT 24	7832116769 ps
T370	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3338126172			May 12 03:49:31 PM PDT 24	May 12 03:55:51 PM PDT 24	4128314644 ps
T60	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2526970480			May 12 03:24:49 PM PDT 24	May 12 03:51:10 PM PDT 24	9958359142 ps
T124	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.502491374			May 12 03:40:55 PM PDT 24	May 12 03:54:07 PM PDT 24	4936356150 ps
T210	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1298081674			May 12 03:44:03 PM PDT 24	May 12 03:51:55 PM PDT 24	5159714248 ps
T275	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1222710432			May 12 03:31:45 PM PDT 24	May 12 03:42:57 PM PDT 24	4879668156 ps
T315	/workspace/coverage/default/84.chip_sw_all_escalation_resets.2992091004			May 12 03:49:44 PM PDT 24	May 12 04:00:10 PM PDT 24	5157886560 ps
T112	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2057418853			May 12 03:13:53 PM PDT 24	May 12 03:16:17 PM PDT 24	2788142303 ps
T115	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4045117188			May 12 03:41:58 PM PDT 24	May 12 03:51:38 PM PDT 24	4503413052 ps
T182	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2126023205			May 12 03:27:28 PM PDT 24	May 12 04:29:59 PM PDT 24	14289130402 ps
T181	/workspace/coverage/default/33.chip_sw_all_escalation_resets.2891447877			May 12 03:46:29 PM PDT 24	May 12 03:57:08 PM PDT 24	4590497248 ps
T309	/workspace/coverage/default/96.chip_sw_all_escalation_resets.932486399			May 12 03:50:23 PM PDT 24	May 12 04:04:29 PM PDT 24	5702605400 ps
T801	/workspace/coverage/default/1.chip_sw_example_rom.3772781313			May 12 03:19:47 PM PDT 24	May 12 03:22:11 PM PDT 24	2298496678 ps
T417	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1967749665			May 12 03:12:38 PM PDT 24	May 12 03:20:41 PM PDT 24	7050033896 ps
T196	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2350611540			May 12 03:18:34 PM PDT 24	May 12 03:26:20 PM PDT 24	9142573094 ps
T39	/workspace/coverage/default/2.chip_sw_spi_device_tpm.2580563039			May 12 03:31:03 PM PDT 24	May 12 03:38:02 PM PDT 24	3756801253 ps
T120	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1201123272			May 12 03:24:02 PM PDT 24	May 12 03:34:10 PM PDT 24	6425568012 ps
T283	/workspace/coverage/default/67.chip_sw_all_escalation_resets.914803304			May 12 03:48:06 PM PDT 24	May 12 04:00:08 PM PDT 24	5965060028 ps
T304	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.365744293			May 12 03:41:11 PM PDT 24	May 12 03:52:30 PM PDT 24	4450450644 ps
T147	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3065096995			May 12 03:23:13 PM PDT 24	May 12 03:26:59 PM PDT 24	2334358806 ps
T63	/workspace/coverage/default/3.chip_tap_straps_rma.77256399			May 12 03:40:58 PM PDT 24	May 12 03:47:36 PM PDT 24	4357208805 ps
T71	/workspace/coverage/default/2.chip_jtag_csr_rw.2872822841			May 12 03:30:06 PM PDT 24	May 12 03:54:15 PM PDT 24	10524669800 ps
T9	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.360828500			May 12 03:32:50 PM PDT 24	May 12 03:43:21 PM PDT 24	4668785391 ps
T630	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1997716770			May 12 03:50:11 PM PDT 24	May 12 03:59:07 PM PDT 24	5321982532 ps
T401	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.428134321			May 12 03:50:54 PM PDT 24	May 12 03:58:17 PM PDT 24	3548405972 ps
T405	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3734956085			May 12 03:31:09 PM PDT 24	May 12 03:35:07 PM PDT 24	2383870276 ps
T138	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1386215204			May 12 03:35:35 PM PDT 24	May 12 04:39:03 PM PDT 24	17204227732 ps
T157	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1390884153			May 12 03:13:30 PM PDT 24	May 12 03:30:16 PM PDT 24	7005671726 ps
T107	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1272888311			May 12 03:16:22 PM PDT 24	May 12 04:34:43 PM PDT 24	24755262454 ps
T316	/workspace/coverage/default/93.chip_sw_all_escalation_resets.4040761736			May 12 03:52:26 PM PDT 24	May 12 04:01:54 PM PDT 24	5209191548 ps
T110	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.662400649			May 12 03:16:51 PM PDT 24	May 12 03:22:28 PM PDT 24	2903270935 ps
T400	/workspace/coverage/default/0.chip_sw_kmac_app_rom.1287982158			May 12 03:12:46 PM PDT 24	May 12 03:16:19 PM PDT 24	3211944308 ps
T211	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1624636219			May 12 03:23:47 PM PDT 24	May 12 03:34:11 PM PDT 24	6741910580 ps
T317	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2354826273			May 12 03:15:17 PM PDT 24	May 12 03:19:24 PM PDT 24	2468451481 ps
T625	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3832624297			May 12 03:48:07 PM PDT 24	May 12 03:56:27 PM PDT 24	3822246168 ps
T35	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.26573244			May 12 03:24:06 PM PDT 24	May 12 03:34:25 PM PDT 24	6757975832 ps
T274	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1731645554			May 12 03:13:05 PM PDT 24	May 12 03:24:32 PM PDT 24	4272597568 ps
T640	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2739644121			May 12 03:33:51 PM PDT 24	May 12 03:38:18 PM PDT 24	2563680869 ps
T631	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1833544768			May 12 03:17:07 PM PDT 24	May 12 03:21:40 PM PDT 24	3168591860 ps
T72	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1418557168			May 12 03:12:55 PM PDT 24	May 12 06:03:48 PM PDT 24	59004287500 ps
T284	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3809123627			May 12 03:44:34 PM PDT 24	May 12 03:52:40 PM PDT 24	3638195072 ps
T624	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.232798298			May 12 03:47:40 PM PDT 24	May 12 03:55:32 PM PDT 24	3939206766 ps
T310	/workspace/coverage/default/2.chip_sw_flash_crash_alert.293946652			May 12 03:38:39 PM PDT 24	May 12 03:52:52 PM PDT 24	4594502856 ps
T6	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.728855304			May 12 03:21:29 PM PDT 24	May 12 03:25:28 PM PDT 24	2919444586 ps
T622	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.926058107			May 12 03:47:51 PM PDT 24	May 12 03:55:08 PM PDT 24	4117413900 ps
T167	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3809307162			May 12 03:14:24 PM PDT 24	May 12 03:20:23 PM PDT 24	3601737010 ps
T113	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2484149847			May 12 03:43:47 PM PDT 24	May 12 03:59:06 PM PDT 24	9618631782 ps
T266	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.777103357			May 12 03:27:20 PM PDT 24	May 12 03:32:49 PM PDT 24	2919869989 ps
T267	/workspace/coverage/default/1.chip_sw_kmac_entropy.2346000091			May 12 03:22:27 PM PDT 24	May 12 03:26:20 PM PDT 24	2626073048 ps
T268	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2733354423			May 12 03:41:13 PM PDT 24	May 12 04:09:38 PM PDT 24	9206499192 ps
T269	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.423695329			May 12 03:37:40 PM PDT 24	May 12 03:50:05 PM PDT 24	8206705840 ps
T45	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2518702056			May 12 03:34:47 PM PDT 24	May 12 03:41:55 PM PDT 24	4560082520 ps
T270	/workspace/coverage/default/2.chip_sw_aes_masking_off.1660157651			May 12 03:35:34 PM PDT 24	May 12 03:39:44 PM PDT 24	2970472927 ps
T271	/workspace/coverage/default/58.chip_sw_all_escalation_resets.1976547928			May 12 03:47:12 PM PDT 24	May 12 03:58:11 PM PDT 24	5704809500 ps
T15	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4270887494			May 12 03:29:04 PM PDT 24	May 12 03:52:20 PM PDT 24	19106523986 ps
T160	/workspace/coverage/default/1.chip_sw_flash_init.4105809329			May 12 03:21:35 PM PDT 24	May 12 03:56:27 PM PDT 24	21618745466 ps
T144	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2501379648			May 12 03:13:15 PM PDT 24	May 12 03:46:32 PM PDT 24	10437348650 ps
T213	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3673003923			May 12 03:50:26 PM PDT 24	May 12 03:58:09 PM PDT 24	4578591732 ps
T257	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.863259111			May 12 03:50:22 PM PDT 24	May 12 03:56:48 PM PDT 24	3829632280 ps
T258	/workspace/coverage/default/34.chip_sw_all_escalation_resets.256064309			May 12 03:45:46 PM PDT 24	May 12 04:00:11 PM PDT 24	4948377620 ps
T153	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2086198930			May 12 03:17:57 PM PDT 24	May 12 03:28:20 PM PDT 24	4131125224 ps
T259	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1823873864			May 12 03:35:53 PM PDT 24	May 12 03:40:44 PM PDT 24	3159159860 ps
T24	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1112600621			May 12 03:19:54 PM PDT 24	May 12 03:23:54 PM PDT 24	2829519110 ps
T260	/workspace/coverage/default/42.chip_sw_all_escalation_resets.2577438552			May 12 03:47:10 PM PDT 24	May 12 03:57:09 PM PDT 24	4748888982 ps
T261	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.245054708			May 12 03:43:54 PM PDT 24	May 12 03:47:33 PM PDT 24	3281458680 ps
T262	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1649611888			May 12 03:48:48 PM PDT 24	May 12 03:55:23 PM PDT 24	3833365804 ps
T161	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3977509654			May 12 03:37:02 PM PDT 24	May 12 04:55:31 PM PDT 24	43558967774 ps
T225	/workspace/coverage/default/30.chip_sw_all_escalation_resets.2513938638			May 12 03:46:45 PM PDT 24	May 12 03:55:49 PM PDT 24	4494818232 ps
T78	/workspace/coverage/default/76.chip_sw_all_escalation_resets.3102405880			May 12 03:50:22 PM PDT 24	May 12 04:02:39 PM PDT 24	5987217120 ps
T90	/workspace/coverage/default/2.chip_sw_all_escalation_resets.369385537			May 12 03:32:34 PM PDT 24	May 12 03:41:47 PM PDT 24	4233294194 ps
T91	/workspace/coverage/default/7.chip_sw_all_escalation_resets.660052127			May 12 03:42:15 PM PDT 24	May 12 03:55:10 PM PDT 24	4847574680 ps
T92	/workspace/coverage/default/2.chip_sw_edn_kat.3881634380			May 12 03:34:49 PM PDT 24	May 12 03:44:22 PM PDT 24	3250021632 ps
T31	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3104223072			May 12 03:32:29 PM PDT 24	May 12 03:38:13 PM PDT 24	3658807896 ps
T93	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1166482764			May 12 03:34:29 PM PDT 24	May 12 03:45:00 PM PDT 24	5131264392 ps
T94	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2890231973			May 12 03:44:17 PM PDT 24	May 12 03:56:17 PM PDT 24	4793975220 ps
T95	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3058093493			May 12 03:35:16 PM PDT 24	May 12 03:56:35 PM PDT 24	5980552184 ps
T96	/workspace/coverage/default/24.chip_sw_all_escalation_resets.1037530103			May 12 03:45:20 PM PDT 24	May 12 03:55:37 PM PDT 24	6155392916 ps
T97	/workspace/coverage/default/81.chip_sw_all_escalation_resets.766609330			May 12 03:48:59 PM PDT 24	May 12 03:58:04 PM PDT 24	5156222984 ps
T104	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.4272920298			May 12 03:18:30 PM PDT 24	May 12 03:59:45 PM PDT 24	16374541430 ps
T212	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2262531017			May 12 03:13:12 PM PDT 24	May 12 03:22:00 PM PDT 24	4940329882 ps
T409	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2355871588			May 12 03:40:51 PM PDT 24	May 12 03:58:33 PM PDT 24	5112376230 ps
T278	/workspace/coverage/default/3.chip_sw_uart_tx_rx.2601475432			May 12 03:41:31 PM PDT 24	May 12 03:52:16 PM PDT 24	4524238350 ps
T802	/workspace/coverage/default/1.chip_sw_csrng_kat_test.624043260			May 12 03:25:57 PM PDT 24	May 12 03:29:24 PM PDT 24	2553082026 ps
T79	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.409595105			May 12 03:25:44 PM PDT 24	May 12 03:33:42 PM PDT 24	3546732030 ps
T224	/workspace/coverage/default/1.chip_sw_edn_boot_mode.3810672056			May 12 03:26:14 PM PDT 24	May 12 03:35:20 PM PDT 24	2938858454 ps
T285	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.507059066			May 12 03:26:00 PM PDT 24	May 12 03:44:35 PM PDT 24	6091229956 ps
T803	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1488660677			May 12 03:14:56 PM PDT 24	May 12 03:19:16 PM PDT 24	3312249683 ps
T500	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3789295970			May 12 03:14:15 PM PDT 24	May 12 03:28:38 PM PDT 24	7782331632 ps
T217	/workspace/coverage/default/2.chip_sw_plic_sw_irq.4079347767			May 12 03:35:48 PM PDT 24	May 12 03:41:00 PM PDT 24	2736654820 ps
T150	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.4272167195			May 12 03:33:57 PM PDT 24	May 12 03:53:12 PM PDT 24	11423631480 ps
T233	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3215857144			May 12 03:38:17 PM PDT 24	May 12 03:46:40 PM PDT 24	8665883007 ps
T804	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3552945766			May 12 03:41:04 PM PDT 24	May 12 03:52:46 PM PDT 24	4299528600 ps
T116	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2698609794			May 12 03:14:46 PM PDT 24	May 12 03:23:12 PM PDT 24	3769073120 ps
T318	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2030903663			May 12 03:30:33 PM PDT 24	May 12 03:35:18 PM PDT 24	2590619837 ps
T805	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2724703619			May 12 03:16:00 PM PDT 24	May 12 03:27:13 PM PDT 24	4596942672 ps
T324	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1246117147			May 12 03:26:22 PM PDT 24	May 12 04:18:07 PM PDT 24	33698056620 ps
T276	/workspace/coverage/default/0.chip_sw_power_idle_load.3119566762			May 12 03:16:30 PM PDT 24	May 12 03:25:40 PM PDT 24	4525360482 ps
T806	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1653683377			May 12 03:34:38 PM PDT 24	May 12 03:42:25 PM PDT 24	7264438116 ps
T177	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3528904641			May 12 03:47:29 PM PDT 24	May 12 03:53:49 PM PDT 24	3482465872 ps
T807	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3896677423			May 12 03:45:26 PM PDT 24	May 12 03:55:07 PM PDT 24	3970415400 ps
T321	/workspace/coverage/default/87.chip_sw_all_escalation_resets.2409074885			May 12 03:50:43 PM PDT 24	May 12 04:01:49 PM PDT 24	5769107020 ps
T141	/workspace/coverage/default/0.chip_plic_all_irqs_10.501026134			May 12 03:14:31 PM PDT 24	May 12 03:23:03 PM PDT 24	3308874456 ps
T139	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1408334004			May 12 03:31:26 PM PDT 24	May 12 06:29:14 PM PDT 24	58499911348 ps
T623	/workspace/coverage/default/89.chip_sw_all_escalation_resets.546063467			May 12 03:52:34 PM PDT 24	May 12 04:00:03 PM PDT 24	4970621260 ps
T146	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.821227238			May 12 03:45:58 PM PDT 24	May 12 03:52:15 PM PDT 24	3763639406 ps
T154	/workspace/coverage/default/2.chip_sival_flash_info_access.2568081109			May 12 03:36:30 PM PDT 24	May 12 03:40:38 PM PDT 24	2322253252 ps
T808	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3803556664			May 12 03:14:55 PM PDT 24	May 12 03:24:22 PM PDT 24	7655211972 ps
T809	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3616021680			May 12 03:28:33 PM PDT 24	May 12 03:34:16 PM PDT 24	6271389344 ps
T594	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.705128477			May 12 03:27:12 PM PDT 24	May 12 03:41:52 PM PDT 24	7382737562 ps
T151	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1295008620			May 12 03:23:12 PM PDT 24	May 12 03:25:27 PM PDT 24	2832526576 ps
T165	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3444733039			May 12 03:37:53 PM PDT 24	May 12 03:47:15 PM PDT 24	3807281120 ps
T251	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3127188356			May 12 03:41:18 PM PDT 24	May 12 04:09:39 PM PDT 24	8916277339 ps
T226	/workspace/coverage/default/25.chip_sw_all_escalation_resets.841529811			May 12 03:45:39 PM PDT 24	May 12 03:56:06 PM PDT 24	6006823940 ps
T152	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1647654148			May 12 03:21:19 PM PDT 24	May 12 03:22:59 PM PDT 24	2401546129 ps
T171	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2568848117			May 12 03:13:11 PM PDT 24	May 12 03:21:37 PM PDT 24	3943777008 ps
T252	/workspace/coverage/default/92.chip_sw_all_escalation_resets.3929092259			May 12 03:50:03 PM PDT 24	May 12 04:02:02 PM PDT 24	5099895492 ps
T80	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1145735891			May 12 03:35:42 PM PDT 24	May 12 03:41:02 PM PDT 24	3590127397 ps
T253	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3689133027			May 12 03:47:32 PM PDT 24	May 12 03:55:18 PM PDT 24	3409845176 ps
T254	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.528615560			May 12 03:45:00 PM PDT 24	May 12 03:57:30 PM PDT 24	3969353356 ps
T255	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3625157303			May 12 03:39:15 PM PDT 24	May 12 03:44:12 PM PDT 24	2809354424 ps
T340	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.827313714			May 12 03:33:26 PM PDT 24	May 12 03:40:27 PM PDT 24	3975838656 ps
T183	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.4136086838			May 12 03:32:17 PM PDT 24	May 12 03:53:54 PM PDT 24	7915926662 ps
T341	/workspace/coverage/default/19.chip_sw_all_escalation_resets.3500042514			May 12 03:44:14 PM PDT 24	May 12 03:54:57 PM PDT 24	5764011400 ps
T342	/workspace/coverage/default/0.chip_sw_example_rom.2226346439			May 12 03:14:50 PM PDT 24	May 12 03:17:02 PM PDT 24	2606251534 ps
T19	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.4213115015			May 12 03:25:12 PM PDT 24	May 12 04:25:12 PM PDT 24	20473672194 ps
T671	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3645148507			May 12 03:46:13 PM PDT 24	May 12 03:51:53 PM PDT 24	4153143608 ps
T693	/workspace/coverage/default/36.chip_sw_all_escalation_resets.3337788872			May 12 03:47:49 PM PDT 24	May 12 04:00:34 PM PDT 24	4486549512 ps
T810	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1402912130			May 12 03:34:12 PM PDT 24	May 12 03:39:19 PM PDT 24	3707203900 ps
T142	/workspace/coverage/default/2.chip_plic_all_irqs_10.2484100233			May 12 03:35:52 PM PDT 24	May 12 03:46:50 PM PDT 24	3449050688 ps
T294	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2942470667			May 12 03:39:04 PM PDT 24	May 12 03:50:01 PM PDT 24	4674426227 ps
T292	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3200551079			May 12 03:16:07 PM PDT 24	May 12 03:28:33 PM PDT 24	4010444575 ps
T297	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1013394044			May 12 03:15:31 PM PDT 24	May 12 03:26:50 PM PDT 24	5311720830 ps
T186	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.4116777986			May 12 03:14:34 PM PDT 24	May 12 03:24:32 PM PDT 24	5352506886 ps
T604	/workspace/coverage/default/2.chip_sw_edn_sw_mode.3416884285			May 12 03:34:38 PM PDT 24	May 12 04:10:01 PM PDT 24	8787071108 ps
T281	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3713159062			May 12 03:38:11 PM PDT 24	May 12 04:09:14 PM PDT 24	18374722230 ps
T811	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2166956803			May 12 03:14:32 PM PDT 24	May 12 03:32:42 PM PDT 24	7522929593 ps
T295	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1430774737			May 12 03:18:25 PM PDT 24	May 12 03:28:44 PM PDT 24	4209827126 ps
T406	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1122428551			May 12 03:31:25 PM PDT 24	May 12 03:35:32 PM PDT 24	2190536124 ps
T111	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1331086642			May 12 03:36:09 PM PDT 24	May 12 03:46:01 PM PDT 24	5278513084 ps
T134	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3140891323			May 12 03:12:54 PM PDT 24	May 12 03:20:17 PM PDT 24	8707349808 ps
T673	/workspace/coverage/default/59.chip_sw_all_escalation_resets.1219302048			May 12 03:47:49 PM PDT 24	May 12 03:57:31 PM PDT 24	5105836500 ps
T812	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1735104500			May 12 03:42:53 PM PDT 24	May 12 03:47:11 PM PDT 24	3512294560 ps
T813	/workspace/coverage/default/1.chip_sw_csrng_smoketest.2691709768			May 12 03:31:07 PM PDT 24	May 12 03:34:08 PM PDT 24	2901699540 ps
T814	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.1949855061			May 12 03:13:28 PM PDT 24	May 12 03:17:09 PM PDT 24	2976150772 ps
T64	/workspace/coverage/default/2.chip_tap_straps_dev.4050667137			May 12 03:38:22 PM PDT 24	May 12 03:58:36 PM PDT 24	12438166699 ps
T815	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.560661205			May 12 03:37:12 PM PDT 24	May 12 03:43:53 PM PDT 24	3941309550 ps
T198	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3685987568			May 12 03:38:36 PM PDT 24	May 12 04:14:17 PM PDT 24	25041114326 ps
T674	/workspace/coverage/default/4.chip_sw_all_escalation_resets.321074681			May 12 03:41:14 PM PDT 24	May 12 03:52:33 PM PDT 24	5374196302 ps
T288	/workspace/coverage/default/1.chip_plic_all_irqs_0.103714386			May 12 03:27:46 PM PDT 24	May 12 03:47:38 PM PDT 24	5902564806 ps
T816	/workspace/coverage/default/2.chip_sw_kmac_app_rom.3251114063			May 12 03:36:03 PM PDT 24	May 12 03:40:01 PM PDT 24	2392560564 ps
T686	/workspace/coverage/default/83.chip_sw_all_escalation_resets.4150943465			May 12 03:50:18 PM PDT 24	May 12 04:00:26 PM PDT 24	4886608440 ps
T714	/workspace/coverage/default/70.chip_sw_all_escalation_resets.1604502842			May 12 03:49:29 PM PDT 24	May 12 03:59:07 PM PDT 24	5591117220 ps
T817	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3980827769			May 12 03:14:09 PM PDT 24	May 12 04:19:05 PM PDT 24	16907899450 ps
T187	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4057089521			May 12 03:23:53 PM PDT 24	May 12 03:46:29 PM PDT 24	8981213792 ps
T108	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3834965954			May 12 03:18:39 PM PDT 24	May 12 04:23:32 PM PDT 24	20909465824 ps
T818	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2496202281			May 12 03:20:44 PM PDT 24	May 12 03:23:47 PM PDT 24	1889661632 ps
T293	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.4003050805			May 12 03:33:38 PM PDT 24	May 12 03:46:09 PM PDT 24	4451128041 ps
T53	/workspace/coverage/default/0.chip_sw_alert_test.2051366236			May 12 03:13:11 PM PDT 24	May 12 03:19:06 PM PDT 24	3274183386 ps
T117	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2821626325			May 12 03:15:09 PM PDT 24	May 12 03:26:02 PM PDT 24	5164909648 ps
T178	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.722215970			May 12 03:27:35 PM PDT 24	May 12 03:55:49 PM PDT 24	6566892886 ps
T279	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2795644955			May 12 03:32:15 PM PDT 24	May 12 07:17:11 PM PDT 24	77168412780 ps
T32	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.4101559584			May 12 03:21:25 PM PDT 24	May 12 03:26:18 PM PDT 24	3404083500 ps
T819	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.250495034			May 12 03:21:56 PM PDT 24	May 12 03:25:45 PM PDT 24	2446265590 ps
T676	/workspace/coverage/default/63.chip_sw_all_escalation_resets.2400404853			May 12 03:49:34 PM PDT 24	May 12 03:59:58 PM PDT 24	5251761996 ps
T665	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2306653833			May 12 03:50:25 PM PDT 24	May 12 03:57:43 PM PDT 24	3938570808 ps
T820	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1300124315			May 12 03:43:42 PM PDT 24	May 12 04:22:14 PM PDT 24	13394522484 ps
T199	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2732074537			May 12 03:18:01 PM PDT 24	May 12 03:46:38 PM PDT 24	24769835241 ps
T821	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.667119894			May 12 03:44:41 PM PDT 24	May 12 04:27:00 PM PDT 24	12965605444 ps
T822	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1431978810			May 12 03:23:58 PM PDT 24	May 12 03:30:50 PM PDT 24	4490322110 ps
T823	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2799418122			May 12 03:43:39 PM PDT 24	May 12 03:53:55 PM PDT 24	7512888720 ps
T218	/workspace/coverage/default/1.chip_sw_plic_sw_irq.3068442383			May 12 03:27:47 PM PDT 24	May 12 03:32:20 PM PDT 24	3042331090 ps
T824	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1844991527			May 12 03:20:13 PM PDT 24	May 12 03:35:48 PM PDT 24	6951034670 ps
T825	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2902907793			May 12 03:43:33 PM PDT 24	May 12 04:08:43 PM PDT 24	8242450000 ps
T826	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2856084882			May 12 03:24:03 PM PDT 24	May 12 03:37:16 PM PDT 24	9226568108 ps
T280	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1845604755			May 12 03:20:24 PM PDT 24	May 12 03:41:21 PM PDT 24	8383352932 ps
T338	/workspace/coverage/default/1.chip_sw_all_escalation_resets.3974811543			May 12 03:19:51 PM PDT 24	May 12 03:32:40 PM PDT 24	5898893858 ps
T363	/workspace/coverage/default/1.chip_sw_edn_auto_mode.2816610795			May 12 03:26:08 PM PDT 24	May 12 03:50:23 PM PDT 24	5633807196 ps
T402	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.139369374			May 12 03:49:19 PM PDT 24	May 12 03:55:42 PM PDT 24	3332098792 ps
T827	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.3558432648			May 12 03:38:47 PM PDT 24	May 12 03:44:39 PM PDT 24	3264061470 ps
T828	/workspace/coverage/default/1.chip_sw_example_flash.564242079			May 12 03:21:26 PM PDT 24	May 12 03:24:53 PM PDT 24	2735065886 ps
T829	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2785663883			May 12 03:13:40 PM PDT 24	May 12 06:34:48 PM PDT 24	64051701242 ps
T322	/workspace/coverage/default/49.chip_sw_all_escalation_resets.1374333333			May 12 03:47:12 PM PDT 24	May 12 03:57:09 PM PDT 24	4577265330 ps
T830	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3181300306			May 12 03:20:52 PM PDT 24	May 12 03:25:21 PM PDT 24	2602244440 ps
T155	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2364511342			May 12 03:15:16 PM PDT 24	May 12 03:23:45 PM PDT 24	6033892140 ps
T831	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1966495601			May 12 03:14:15 PM PDT 24	May 12 03:27:48 PM PDT 24	9374472680 ps
T668	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3363484783			May 12 03:13:36 PM PDT 24	May 12 03:32:29 PM PDT 24	7440770680 ps
T209	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1361634287			May 12 03:20:42 PM PDT 24	May 12 03:30:28 PM PDT 24	5446221244 ps
T143	/workspace/coverage/default/1.chip_plic_all_irqs_10.3957418472			May 12 03:31:47 PM PDT 24	May 12 03:39:45 PM PDT 24	3685213322 ps
T678	/workspace/coverage/default/31.chip_sw_all_escalation_resets.2096726096			May 12 03:45:44 PM PDT 24	May 12 03:58:33 PM PDT 24	4959425656 ps
T733	/workspace/coverage/default/20.chip_sw_all_escalation_resets.627125116			May 12 03:44:54 PM PDT 24	May 12 03:54:22 PM PDT 24	3904696406 ps
T20	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3226908939			May 12 03:14:58 PM PDT 24	May 12 04:20:20 PM PDT 24	20999049073 ps
T122	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2928046741			May 12 03:38:23 PM PDT 24	May 12 03:48:26 PM PDT 24	5175729452 ps
T647	/workspace/coverage/default/46.chip_sw_all_escalation_resets.3751170845			May 12 03:49:12 PM PDT 24	May 12 04:00:57 PM PDT 24	5897546776 ps
T832	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1919114752			May 12 03:28:21 PM PDT 24	May 12 03:39:24 PM PDT 24	5258271328 ps
T833	/workspace/coverage/default/1.chip_sw_edn_sw_mode.675219649			May 12 03:25:33 PM PDT 24	May 12 03:48:00 PM PDT 24	6391150812 ps
T156	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.4286886971			May 12 03:24:05 PM PDT 24	May 12 04:00:46 PM PDT 24	29656675972 ps
T632	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.4159515427			May 12 03:33:27 PM PDT 24	May 12 03:37:06 PM PDT 24	2276706674 ps
T834	/workspace/coverage/default/1.chip_sival_flash_info_access.4252886518			May 12 03:23:03 PM PDT 24	May 12 03:27:33 PM PDT 24	3403199508 ps
T835	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3267314714			May 12 03:13:27 PM PDT 24	May 12 03:24:43 PM PDT 24	4540238328 ps
T836	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.528676475			May 12 03:26:53 PM PDT 24	May 12 03:31:38 PM PDT 24	2369991160 ps
T298	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3691703987			May 12 03:21:32 PM PDT 24	May 12 03:33:34 PM PDT 24	4189075688 ps
T163	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2657908010			May 12 03:25:05 PM PDT 24	May 12 03:30:45 PM PDT 24	3664958004 ps
T710	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2194522985			May 12 03:49:20 PM PDT 24	May 12 03:55:24 PM PDT 24	3843791200 ps
T670	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3981052515			May 12 03:48:21 PM PDT 24	May 12 03:55:42 PM PDT 24	3589297908 ps
T667	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1482496199			May 12 03:47:26 PM PDT 24	May 12 03:55:05 PM PDT 24	3285883456 ps
T184	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2554954310			May 12 03:22:44 PM PDT 24	May 12 03:41:05 PM PDT 24	6881591872 ps
T16	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1863061179			May 12 03:29:43 PM PDT 24	May 12 03:38:20 PM PDT 24	7486550186 ps
T498	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2541923940			May 12 03:15:13 PM PDT 24	May 12 03:30:05 PM PDT 24	4635709118 ps
T837	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.4061304428			May 12 03:34:33 PM PDT 24	May 12 06:47:02 PM PDT 24	65880855975 ps
T838	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.580300494			May 12 03:27:21 PM PDT 24	May 12 03:30:48 PM PDT 24	2519176318 ps
T234	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.387510446			May 12 03:33:01 PM PDT 24	May 12 03:45:28 PM PDT 24	4478739446 ps
T185	/workspace/coverage/default/82.chip_sw_all_escalation_resets.1327622522			May 12 03:51:15 PM PDT 24	May 12 04:01:13 PM PDT 24	5113785072 ps