Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	165965	1			T68	5		T69	29		T70	13
values[2]	4548	1			T75	5		T412	2		T503	7
values[3]	2167	1			T422	25		T770	1		T609	7
values[4]	1761	1			T422	12		T609	9		T751	4
values[5]	1410	1			T422	30		T609	9		T751	2
values[6]	1215	1			T422	26		T609	9		T751	3
values[7]	1094	1			T422	17		T609	8		T751	1
values[8]	1022	1			T422	9		T609	13		T751	2
values[9]	997	1			T422	7		T609	8		T751	1
values[10]	831	1			T422	4		T609	10		T751	3
values[11]	737	1			T422	2		T609	15		T751	3
values[12]	589	1			T422	2		T609	14		T751	1
values[13]	612	1			T422	5		T609	6		T751	2
values[14]	543	1			T422	19		T609	6		T751	3
values[15]	565	1			T422	22		T609	12		T751	4
values[16]	487	1			T422	19		T609	18		T751	4
values[17]	427	1			T422	7		T609	12		T751	1
values[18]	314	1			T422	28		T609	7		T751	2
values[19]	257	1			T422	23		T609	2		T751	4
values[20]	244	1			T422	14		T609	9		T751	3
values[21]	190	1			T422	5		T609	2		T751	1
values[22]	157	1			T422	17		T609	3		T751	1
values[23]	178	1			T422	14		T609	4		T751	2
values[24]	147	1			T422	12		T609	2		T751	1
values[25]	146	1			T422	13		T609	2		T751	2
values[26]	130	1			T422	9		T609	3		T751	4
values[27]	98	1			T422	8		T609	1		T751	2
values[28]	85	1			T422	4		T609	2		T751	1
values[29]	71	1			T609	2		T751	4		T642	1
values[30]	88	1			T609	4		T751	3		T642	1
values[31]	61	1			T609	1		T751	2		T642	1
values[32]	86	1			T609	4		T751	8		T642	1
values[33]	67	1			T609	1		T751	2		T642	1
values[34]	98	1			T609	5		T751	2		T642	1
values[35]	97	1			T609	6		T751	1		T642	1
values[36]	101	1			T609	2		T751	6		T642	1
values[37]	84	1			T609	2		T751	2		T642	1
values[38]	60	1			T609	2		T751	3		T642	1
values[39]	70	1			T609	4		T751	1		T642	1
values[40]	77	1			T609	2		T751	2		T642	1
values[41]	80	1			T609	2		T751	2		T642	1
values[42]	79	1			T609	3		T751	1		T642	1
values[43]	55	1			T609	3		T751	3		T642	1
values[44]	46	1			T609	3		T751	1		T642	1
values[45]	56	1			T609	1		T751	2		T642	1
values[46]	57	1			T609	4		T751	4		T642	1
values[47]	64	1			T609	3		T751	5		T642	1
values[48]	44	1			T609	4		T751	2		T642	1
values[49]	43	1			T609	1		T751	2		T642	1
values[50]	50	1			T609	3		T751	1		T642	1
values[51]	45	1			T609	4		T751	1		T642	1
values[52]	45	1			T609	2		T751	5		T642	1
values[53]	45	1			T609	5		T751	5		T642	1
values[54]	42	1			T609	3		T751	4		T642	1
values[55]	51	1			T609	3		T751	1		T642	1
values[56]	48	1			T609	2		T751	3		T642	1
values[57]	46	1			T609	1		T751	1		T642	1
values[58]	54	1			T609	3		T751	3		T642	1
values[59]	62	1			T609	3		T751	1		T642	1
values[60]	57	1			T609	1		T751	2		T642	1
values[61]	58	1			T609	4		T751	7		T642	1
values[62]	42	1			T609	3		T751	1		T642	1
values[63]	46	1			T609	1		T751	2		T642	1
values[64]	47	1			T609	5		T751	3		T642	1
values[65]	46	1			T609	3		T751	1		T642	1
values[66]	48	1			T609	5		T751	3		T642	1
values[67]	51	1			T609	1		T751	3		T642	1
values[68]	48	1			T609	3		T751	1		T642	1
values[69]	45	1			T609	3		T751	1		T642	1
values[70]	48	1			T609	2		T751	1		T642	1
values[71]	56	1			T609	2		T751	2		T642	1
values[72]	61	1			T609	2		T751	1		T642	1
values[73]	56	1			T609	2		T751	3		T642	1
values[74]	62	1			T609	2		T751	6		T642	1
values[75]	75	1			T609	1		T751	1		T642	1
values[76]	59	1			T609	1		T751	1		T642	1
values[77]	63	1			T609	3		T751	2		T642	1
values[78]	73	1			T609	1		T751	2		T642	1
values[79]	85	1			T609	6		T751	3		T642	1
values[80]	49	1			T609	2		T751	1		T642	1
values[81]	55	1			T609	3		T751	3		T642	1
values[82]	62	1			T609	1		T751	2		T642	1
values[83]	71	1			T609	1		T751	7		T642	1
values[84]	65	1			T609	2		T751	1		T642	1
values[85]	69	1			T609	2		T751	2		T642	1
values[86]	65	1			T609	6		T751	1		T642	1
values[87]	74	1			T609	5		T751	2		T642	1
values[88]	77	1			T609	3		T751	1		T642	1
values[89]	68	1			T609	9		T751	3		T642	1
values[90]	64	1			T609	11		T751	2		T642	1
values[91]	53	1			T609	5		T751	1		T642	1
values[92]	70	1			T609	10		T751	2		T642	1
values[93]	63	1			T609	2		T751	1		T642	1
values[94]	63	1			T609	1		T751	1		T642	1
values[95]	54	1			T609	6		T751	6		T642	1
values[96]	65	1			T609	3		T751	1		T642	1
values[97]	63	1			T609	2		T751	6		T642	1
values[98]	72	1			T609	7		T751	2		T642	1
values[99]	66	1			T609	6		T751	3		T642	1
values[100]	60	1			T609	2		T751	5		T642	1
values[101]	67	1			T609	2		T751	5		T642	1
values[102]	71	1			T609	4		T751	2		T642	1
values[103]	68	1			T609	2		T751	5		T642	1
values[104]	67	1			T609	1		T751	2		T642	1
values[105]	63	1			T609	1		T751	6		T642	1
values[106]	75	1			T609	7		T751	8		T642	1
values[107]	65	1			T609	8		T751	2		T642	1
values[108]	69	1			T609	12		T751	2		T642	1
values[109]	57	1			T609	4		T751	1		T642	1
values[110]	62	1			T609	5		T751	1		T642	1
values[111]	70	1			T609	2		T751	6		T642	1
values[112]	67	1			T609	1		T751	1		T642	1
values[113]	77	1			T609	8		T751	4		T642	1
values[114]	78	1			T609	3		T751	1		T642	1
values[115]	87	1			T609	1		T751	2		T642	1
values[116]	68	1			T609	9		T751	3		T642	1
values[117]	85	1			T609	5		T751	2		T642	1
values[118]	102	1			T609	9		T751	5		T642	1
values[119]	91	1			T609	8		T751	2		T642	1
values[120]	95	1			T609	4		T751	5		T642	1
values[121]	104	1			T609	6		T751	4		T642	1
values[122]	101	1			T609	2		T751	2		T642	1
values[123]	120	1			T609	2		T751	6		T642	1
values[124]	151	1			T609	5		T751	14		T642	1
values[125]	318	1			T609	10		T751	29		T642	4
values[126]	690	1			T609	6		T751	52		T642	10
values[127]	1858	1			T609	2		T751	30		T642	84
values[128]	3053	1			T751	1		T642	209		T771	2