Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139784	1			T68	2		T69	22		T70	16
values[2]	9926	1			T76	3		T414	1		T412	3
values[3]	3817	1			T422	70		T441	1		T607	2
values[4]	2227	1			T422	48		T609	63		T484	23
values[5]	1510	1			T422	18		T609	37		T484	4
values[6]	1072	1			T422	7		T609	2		T484	1
values[7]	786	1			T422	14		T642	1		T757	73
values[8]	591	1			T422	14		T642	1		T757	15
values[9]	548	1			T422	30		T642	1		T757	4
values[10]	461	1			T422	17		T642	1		T643	3
values[11]	366	1			T422	5		T642	1		T643	11
values[12]	343	1			T422	3		T642	1		T643	6
values[13]	375	1			T422	9		T642	1		T643	3
values[14]	297	1			T642	1		T643	5		T424	1
values[15]	257	1			T642	1		T643	6		T424	1
values[16]	231	1			T642	1		T643	5		T424	1
values[17]	283	1			T642	1		T643	2		T424	1
values[18]	343	1			T642	1		T643	4		T424	1
values[19]	311	1			T642	1		T643	8		T424	1
values[20]	323	1			T642	1		T643	5		T424	1
values[21]	293	1			T642	1		T643	8		T424	1
values[22]	279	1			T642	1		T643	9		T424	1
values[23]	281	1			T642	1		T643	3		T424	1
values[24]	258	1			T642	1		T643	3		T424	1
values[25]	248	1			T642	1		T643	1		T424	1
values[26]	262	1			T642	1		T643	1		T424	1
values[27]	248	1			T642	1		T643	1		T424	1
values[28]	272	1			T642	1		T643	2		T424	1
values[29]	277	1			T642	1		T643	2		T424	1
values[30]	306	1			T642	1		T643	1		T424	1
values[31]	300	1			T642	1		T643	4		T424	1
values[32]	262	1			T642	1		T643	8		T424	1
values[33]	230	1			T642	1		T643	3		T424	1
values[34]	304	1			T642	1		T643	2		T424	1
values[35]	277	1			T642	1		T643	2		T424	1
values[36]	286	1			T642	1		T643	1		T424	1
values[37]	322	1			T642	1		T643	6		T424	1
values[38]	282	1			T642	1		T643	6		T424	1
values[39]	242	1			T642	1		T643	2		T424	2
values[40]	255	1			T642	1		T643	1		T424	1
values[41]	261	1			T642	1		T643	2		T424	1
values[42]	263	1			T642	1		T643	7		T424	1
values[43]	270	1			T642	1		T643	2		T424	1
values[44]	229	1			T642	1		T643	1		T424	1
values[45]	257	1			T642	1		T643	5		T424	1
values[46]	307	1			T642	1		T643	15		T424	1
values[47]	275	1			T642	1		T643	13		T424	1
values[48]	264	1			T642	1		T643	5		T424	1
values[49]	249	1			T642	1		T643	1		T424	1
values[50]	221	1			T642	1		T643	7		T424	1
values[51]	240	1			T642	1		T643	3		T424	1
values[52]	222	1			T642	1		T643	6		T424	1
values[53]	224	1			T642	1		T643	3		T424	1
values[54]	256	1			T642	1		T643	2		T424	1
values[55]	194	1			T642	1		T643	1		T424	1
values[56]	262	1			T642	1		T643	4		T424	1
values[57]	242	1			T642	1		T643	3		T424	1
values[58]	203	1			T642	1		T643	7		T424	1
values[59]	180	1			T642	1		T643	3		T424	1
values[60]	211	1			T642	1		T643	6		T424	1
values[61]	160	1			T642	1		T643	2		T424	1
values[62]	161	1			T642	1		T643	2		T424	1
values[63]	123	1			T642	1		T643	1		T424	1
values[64]	122	1			T642	1		T643	2		T424	1
values[65]	112	1			T642	1		T643	3		T424	1
values[66]	106	1			T642	1		T643	5		T424	1
values[67]	109	1			T642	1		T643	2		T424	1
values[68]	100	1			T642	1		T643	1		T424	1
values[69]	100	1			T642	1		T643	2		T424	1
values[70]	109	1			T642	1		T643	3		T424	1
values[71]	108	1			T642	1		T643	11		T424	1
values[72]	98	1			T642	1		T643	5		T424	1
values[73]	84	1			T642	1		T643	7		T424	1
values[74]	86	1			T642	1		T643	18		T424	1
values[75]	74	1			T642	1		T643	6		T424	1
values[76]	97	1			T642	1		T643	11		T424	1
values[77]	95	1			T642	1		T643	7		T424	1
values[78]	101	1			T642	2		T643	11		T424	1
values[79]	97	1			T642	1		T643	4		T424	1
values[80]	96	1			T642	1		T643	5		T424	1
values[81]	77	1			T642	1		T643	5		T424	1
values[82]	78	1			T642	1		T643	2		T424	1
values[83]	94	1			T642	1		T643	4		T424	1
values[84]	100	1			T642	1		T643	4		T424	1
values[85]	89	1			T642	1		T643	10		T424	1
values[86]	107	1			T642	1		T643	14		T424	1
values[87]	91	1			T642	1		T643	7		T424	1
values[88]	102	1			T642	1		T643	5		T424	1
values[89]	93	1			T642	1		T643	9		T424	1
values[90]	89	1			T642	1		T643	6		T424	1
values[91]	87	1			T642	1		T643	9		T424	1
values[92]	103	1			T642	1		T643	2		T424	3
values[93]	104	1			T642	1		T643	3		T424	7
values[94]	129	1			T642	6		T643	7		T424	2
values[95]	100	1			T642	2		T643	3		T424	4
values[96]	104	1			T642	1		T643	2		T424	1
values[97]	123	1			T642	2		T643	3		T424	6
values[98]	122	1			T642	6		T643	4		T424	3
values[99]	107	1			T642	1		T643	4		T424	1
values[100]	104	1			T642	3		T643	3		T424	1
values[101]	113	1			T642	2		T643	2		T424	1
values[102]	128	1			T642	5		T643	11		T424	5
values[103]	111	1			T642	1		T643	7		T424	1
values[104]	94	1			T642	3		T643	3		T424	2
values[105]	88	1			T642	1		T643	3		T424	4
values[106]	99	1			T642	2		T643	1		T424	3
values[107]	95	1			T642	2		T424	3		T476	7
values[108]	111	1			T642	2		T424	2		T476	20
values[109]	89	1			T642	2		T424	3		T476	12
values[110]	91	1			T642	2		T424	2		T476	5
values[111]	102	1			T642	1		T424	2		T752	1
values[112]	90	1			T642	1		T424	3		T752	3
values[113]	78	1			T642	1		T424	1		T752	3
values[114]	93	1			T642	3		T424	2		T752	1
values[115]	107	1			T642	3		T424	1		T752	5
values[116]	100	1			T642	1		T424	1		T752	1
values[117]	87	1			T642	2		T424	2		T752	1
values[118]	103	1			T642	1		T424	3		T752	2
values[119]	84	1			T642	1		T424	2		T752	4
values[120]	95	1			T642	2		T424	2		T752	3
values[121]	83	1			T642	1		T424	8		T752	2
values[122]	87	1			T642	1		T424	1		T752	3
values[123]	97	1			T642	7		T424	2		T752	1
values[124]	79	1			T642	3		T424	1		T752	2
values[125]	122	1			T642	3		T424	1		T752	2
values[126]	152	1			T642	4		T424	1		T752	1
values[127]	1106	1			T642	34		T424	29		T752	28
values[128]	9345	1			T642	337		T424	325		T752	297