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Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T502 1 T505 1 T507 1
small_delay 963 1 T70 1 T76 1 T75 1
zero 637 1 T68 1 T69 1 T345 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T76 1 T503 1 T502 1
small_delay 663 1 T70 1 T75 1 T412 1
zero 637 1 T68 1 T69 1 T345 1

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