Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	480	1			T75	1		T412	2		T512	1
all_values[1]	484	1			T512	2		T413	7		T509	1
all_values[2]	453	1			T75	2		T512	1		T413	6
all_values[3]	483	1			T75	3		T512	4		T413	5
all_values[4]	499	1			T75	3		T412	2		T512	2
all_values[5]	478	1			T75	2		T412	2		T512	2
all_values[6]	433	1			T75	4		T412	2		T512	1
all_values[7]	498	1			T75	1		T412	1		T512	3
all_values[8]	481	1			T75	4		T412	1		T512	3
all_values[9]	483	1			T75	1		T412	1		T512	2
all_values[10]	515	1			T75	1		T412	1		T512	1
all_values[11]	524	1			T75	1		T512	2		T413	2
all_values[12]	503	1			T75	1		T412	1		T413	5
all_values[13]	528	1			T75	1		T412	2		T512	1
all_values[14]	523	1			T75	1		T412	2		T512	1
all_values[15]	499	1			T75	1		T412	2		T512	3
all_values[16]	483	1			T75	5		T412	1		T512	1
all_values[17]	476	1			T75	1		T412	1		T512	1
all_values[18]	425	1			T75	1		T412	3		T512	1
all_values[19]	483	1			T75	2		T412	1		T512	3
all_values[20]	454	1			T75	2		T412	1		T512	3
all_values[21]	474	1			T75	1		T412	1		T512	2
all_values[22]	521	1			T412	1		T512	2		T413	9
all_values[23]	504	1			T412	3		T512	2		T413	2
all_values[24]	460	1			T75	2		T512	2		T413	7
all_values[25]	459	1			T512	1		T413	1		T422	1
all_values[26]	480	1			T75	2		T412	1		T512	2
all_values[27]	499	1			T75	6		T412	1		T512	1
all_values[28]	479	1			T75	3		T512	1		T413	3
all_values[29]	507	1			T412	1		T512	2		T413	1
all_values[30]	521	1			T75	4		T412	3		T512	1
all_values[31]	489	1			T75	2		T412	1		T512	2
all_values[32]	499	1			T512	2		T413	5		T422	1
all_values[33]	496	1			T75	1		T512	5		T413	4
all_values[34]	531	1			T75	3		T512	3		T413	1
all_values[35]	478	1			T75	3		T512	2		T413	3
all_values[36]	497	1			T75	1		T412	1		T512	1
all_values[37]	502	1			T75	2		T412	3		T512	1
all_values[38]	489	1			T75	1		T512	2		T413	6
all_values[39]	460	1			T75	1		T412	2		T512	3
all_values[40]	445	1			T75	2		T413	3		T509	2
all_values[41]	477	1			T75	2		T412	1		T413	3
all_values[42]	500	1			T75	2		T412	3		T413	3
all_values[43]	479	1			T75	2		T412	1		T413	5
all_values[44]	513	1			T75	1		T412	1		T413	3
all_values[45]	493	1			T75	3		T412	1		T512	2
all_values[46]	469	1			T75	3		T412	2		T512	3
all_values[47]	492	1			T75	1		T413	2		T509	4
all_values[48]	474	1			T75	1		T412	1		T413	7
all_values[49]	494	1			T75	2		T412	1		T413	2