Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3591	1			T75	19		T412	7		T512	7
all_values[1]	3592	1			T75	13		T412	10		T512	12
all_values[2]	3572	1			T75	16		T412	9		T512	13
all_values[3]	3569	1			T75	15		T412	3		T512	13
all_values[4]	3658	1			T75	10		T412	6		T512	7
all_values[5]	3643	1			T75	13		T412	10		T512	12
all_values[6]	3692	1			T75	25		T412	5		T512	13
all_values[7]	3536	1			T75	17		T412	10		T512	14
all_values[8]	3705	1			T75	19		T412	7		T512	13
all_values[9]	3650	1			T75	25		T412	10		T512	12
all_values[10]	3648	1			T75	4		T412	9		T512	14
all_values[11]	3593	1			T75	18		T412	4		T512	12
all_values[12]	3715	1			T75	19		T412	7		T512	13
all_values[13]	3675	1			T75	23		T412	9		T512	9
all_values[14]	3518	1			T75	15		T412	7		T512	15
all_values[15]	3616	1			T75	20		T412	17		T512	22
all_values[16]	3548	1			T75	13		T412	10		T512	11
all_values[17]	3590	1			T75	13		T412	7		T512	14
all_values[18]	3618	1			T75	13		T412	6		T512	13
all_values[19]	3644	1			T75	17		T412	7		T512	11
all_values[20]	3681	1			T75	23		T412	7		T512	8
all_values[21]	3663	1			T75	9		T412	9		T512	14
all_values[22]	3706	1			T75	19		T412	11		T512	10
all_values[23]	3600	1			T75	19		T412	6		T512	12
all_values[24]	3561	1			T75	20		T412	10		T512	13
all_values[25]	3542	1			T75	16		T412	6		T512	13
all_values[26]	3601	1			T75	16		T412	6		T512	17
all_values[27]	3682	1			T75	16		T412	7		T512	10
all_values[28]	3646	1			T75	16		T412	4		T512	10
all_values[29]	3591	1			T75	19		T412	7		T512	12
all_values[30]	3703	1			T75	17		T412	7		T512	7
all_values[31]	3575	1			T75	21		T412	11		T512	10
all_values[32]	3599	1			T75	18		T412	11		T512	4
all_values[33]	3629	1			T75	14		T412	5		T512	7
all_values[34]	3739	1			T75	21		T412	7		T512	7
all_values[35]	3546	1			T75	21		T412	6		T512	10
all_values[36]	3723	1			T75	17		T412	8		T512	6
all_values[37]	3645	1			T75	19		T412	11		T512	9
all_values[38]	3643	1			T75	20		T412	7		T512	12
all_values[39]	3718	1			T75	19		T412	7		T512	10
all_values[40]	3581	1			T75	22		T412	5		T512	7
all_values[41]	3645	1			T75	12		T412	8		T512	12
all_values[42]	3728	1			T75	11		T412	5		T512	12
all_values[43]	3643	1			T75	15		T412	10		T512	13
all_values[44]	3633	1			T75	21		T412	7		T512	12
all_values[45]	3633	1			T75	19		T412	7		T512	9
all_values[46]	3647	1			T75	18		T412	7		T512	8
all_values[47]	3656	1			T75	14		T412	4		T512	10
all_values[48]	3624	1			T75	24		T412	6		T512	11
all_values[49]	3660	1			T75	21		T412	3		T512	13
all_values[50]	3627	1			T75	9		T412	10		T512	12
all_values[51]	3538	1			T75	11		T412	11		T512	10
all_values[52]	3677	1			T75	16		T412	6		T512	9
all_values[53]	3730	1			T75	22		T412	13		T512	10
all_values[54]	3650	1			T75	13		T412	9		T512	14
all_values[55]	3735	1			T75	7		T412	5		T512	14
all_values[56]	3602	1			T75	18		T412	5		T512	11
all_values[57]	3607	1			T75	15		T412	5		T512	9
all_values[58]	3607	1			T75	16		T412	8		T512	14
all_values[59]	3597	1			T75	21		T412	9		T512	14
all_values[60]	3616	1			T75	15		T412	6		T512	9
all_values[61]	3640	1			T75	19		T412	6		T512	18
all_values[62]	3606	1			T75	18		T412	4		T512	9
all_values[63]	3669	1			T75	16		T412	10		T512	11