Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	147008	1			T63	3		T64	106		T70	6
values[2]	4155	1			T113	3		T399	3		T479	1
values[3]	2050	1			T403	1		T830	15		T831	1
values[4]	1417	1			T403	3		T830	48		T831	1
values[5]	1085	1			T403	1		T830	74		T831	1
values[6]	840	1			T403	2		T830	73		T831	1
values[7]	730	1			T403	8		T830	71		T831	1
values[8]	715	1			T403	2		T830	75		T831	1
values[9]	638	1			T403	3		T830	58		T831	1
values[10]	562	1			T403	2		T830	22		T831	1
values[11]	482	1			T403	2		T830	8		T831	1
values[12]	404	1			T403	4		T830	6		T831	1
values[13]	360	1			T403	4		T830	4		T831	1
values[14]	281	1			T403	2		T830	2		T831	1
values[15]	309	1			T403	2		T830	7		T831	1
values[16]	315	1			T403	7		T830	15		T831	2
values[17]	291	1			T403	4		T830	12		T831	1
values[18]	299	1			T403	2		T830	5		T831	1
values[19]	234	1			T403	2		T830	1		T831	1
values[20]	205	1			T403	2		T831	1		T855	1
values[21]	210	1			T403	3		T831	1		T855	1
values[22]	253	1			T403	2		T831	1		T855	1
values[23]	301	1			T403	7		T831	1		T855	1
values[24]	269	1			T403	4		T831	1		T855	1
values[25]	271	1			T403	1		T831	1		T855	1
values[26]	224	1			T403	6		T831	1		T855	1
values[27]	210	1			T403	1		T831	1		T855	1
values[28]	152	1			T403	1		T831	1		T855	1
values[29]	113	1			T403	1		T831	1		T855	1
values[30]	110	1			T403	3		T831	1		T855	1
values[31]	82	1			T403	6		T831	1		T855	1
values[32]	81	1			T403	1		T831	1		T855	1
values[33]	78	1			T403	3		T831	1		T855	1
values[34]	93	1			T403	4		T831	1		T855	1
values[35]	103	1			T403	3		T831	1		T855	1
values[36]	112	1			T403	3		T831	1		T855	1
values[37]	100	1			T403	1		T831	1		T855	1
values[38]	100	1			T403	1		T831	1		T855	1
values[39]	108	1			T403	2		T831	1		T855	1
values[40]	124	1			T403	5		T831	1		T855	1
values[41]	107	1			T403	4		T831	1		T855	1
values[42]	114	1			T403	2		T831	1		T855	1
values[43]	109	1			T403	1		T831	1		T855	1
values[44]	82	1			T403	3		T831	1		T855	1
values[45]	88	1			T403	1		T831	1		T855	1
values[46]	89	1			T403	2		T831	1		T855	1
values[47]	85	1			T403	1		T831	1		T855	1
values[48]	76	1			T403	2		T831	1		T855	1
values[49]	77	1			T403	1		T831	1		T855	1
values[50]	75	1			T403	2		T831	1		T855	1
values[51]	79	1			T403	5		T831	1		T855	1
values[52]	58	1			T403	1		T831	1		T855	1
values[53]	57	1			T403	1		T831	1		T855	1
values[54]	62	1			T403	1		T831	1		T855	1
values[55]	67	1			T403	4		T831	1		T855	1
values[56]	74	1			T403	4		T831	1		T855	1
values[57]	61	1			T403	7		T831	1		T855	1
values[58]	61	1			T403	2		T831	1		T855	1
values[59]	58	1			T403	1		T831	1		T855	1
values[60]	61	1			T403	7		T831	1		T855	1
values[61]	68	1			T403	3		T831	1		T855	1
values[62]	60	1			T403	2		T831	1		T855	1
values[63]	57	1			T403	2		T831	1		T855	1
values[64]	74	1			T403	1		T831	1		T855	1
values[65]	76	1			T403	5		T831	1		T855	1
values[66]	61	1			T403	3		T831	1		T855	1
values[67]	71	1			T403	5		T831	1		T855	1
values[68]	63	1			T403	2		T831	1		T855	1
values[69]	60	1			T403	1		T831	1		T855	1
values[70]	64	1			T403	2		T831	1		T855	1
values[71]	67	1			T403	3		T831	1		T855	1
values[72]	62	1			T403	1		T831	1		T855	1
values[73]	71	1			T403	3		T831	1		T855	1
values[74]	66	1			T403	2		T831	1		T855	1
values[75]	64	1			T403	4		T831	1		T855	1
values[76]	73	1			T403	2		T831	1		T855	1
values[77]	75	1			T403	2		T831	1		T855	1
values[78]	71	1			T403	1		T831	1		T855	1
values[79]	84	1			T403	3		T831	1		T855	1
values[80]	77	1			T403	1		T831	1		T855	1
values[81]	72	1			T403	6		T831	1		T855	1
values[82]	80	1			T403	5		T831	1		T855	1
values[83]	72	1			T403	2		T831	1		T855	1
values[84]	67	1			T403	1		T831	1		T855	1
values[85]	83	1			T403	4		T831	1		T855	1
values[86]	84	1			T403	2		T831	1		T855	1
values[87]	79	1			T403	4		T831	1		T855	1
values[88]	91	1			T403	2		T831	1		T855	1
values[89]	102	1			T403	3		T831	3		T855	1
values[90]	114	1			T403	10		T831	3		T855	1
values[91]	100	1			T403	2		T831	6		T855	2
values[92]	97	1			T403	5		T831	6		T855	1
values[93]	96	1			T403	2		T831	3		T855	1
values[94]	120	1			T403	2		T831	6		T855	1
values[95]	102	1			T403	4		T831	13		T855	1
values[96]	96	1			T403	3		T831	5		T855	1
values[97]	103	1			T403	5		T831	1		T855	1
values[98]	122	1			T403	5		T831	2		T855	1
values[99]	122	1			T403	2		T831	2		T855	1
values[100]	99	1			T403	2		T831	1		T855	1
values[101]	82	1			T403	4		T831	3		T855	1
values[102]	102	1			T403	2		T831	2		T855	1
values[103]	102	1			T403	4		T831	3		T855	1
values[104]	105	1			T403	2		T831	4		T855	1
values[105]	100	1			T403	6		T831	2		T855	1
values[106]	96	1			T403	1		T831	4		T855	1
values[107]	112	1			T403	3		T831	2		T855	1
values[108]	108	1			T403	3		T831	1		T855	1
values[109]	111	1			T403	1		T831	2		T855	1
values[110]	104	1			T403	4		T831	3		T855	1
values[111]	120	1			T403	11		T831	2		T855	1
values[112]	108	1			T403	6		T831	1		T855	1
values[113]	106	1			T403	3		T831	4		T855	1
values[114]	91	1			T403	2		T831	4		T855	1
values[115]	133	1			T403	5		T831	3		T855	1
values[116]	135	1			T403	10		T831	1		T855	1
values[117]	114	1			T403	5		T831	2		T855	1
values[118]	106	1			T403	2		T831	1		T855	1
values[119]	101	1			T403	7		T831	3		T855	1
values[120]	126	1			T403	6		T831	2		T855	1
values[121]	149	1			T403	12		T831	2		T855	1
values[122]	110	1			T403	1		T831	2		T855	1
values[123]	139	1			T403	4		T831	4		T855	2
values[124]	227	1			T403	7		T831	2		T855	2
values[125]	396	1			T403	11		T831	5		T855	3
values[126]	734	1			T403	17		T831	17		T855	16
values[127]	3047	1			T403	3		T831	97		T855	111
values[128]	5959	1			T403	1		T831	233		T855	236