Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.41	95.32	93.80	91.97		94.43	97.38	99.54

Total tests in report: 2731

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
38.77	38.77	39.15	39.15	39.38	39.38	36.66	36.66			55.76	55.76	61.48	61.48	0.19	0.19	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3275796893
48.76	9.99	44.85	5.70	54.93	15.56	37.35	0.69			65.98	10.22	88.15	26.67	1.32	1.13	/workspace/coverage/cover_reg_top/14.chip_csr_rw.3261450755
56.22	7.46	56.50	11.65	57.73	2.80	44.55	7.20			67.06	1.08	88.15	0.00	23.36	22.04	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.684582504
60.73	4.50	66.46	9.97	64.11	6.38	46.70	2.15			75.58	8.52	88.15	0.00	23.36	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.76316538
64.46	3.73	66.46	0.00	64.11	0.00	46.70	0.00			75.58	0.00	88.15	0.00	45.76	22.41	/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.800965259
67.99	3.53	71.48	5.02	68.88	4.77	53.03	6.33			77.44	1.85	89.07	0.93	48.03	2.27	/workspace/coverage/default/1.chip_sw_alert_test.1776455629
71.14	3.15	71.48	0.00	68.88	0.00	53.03	0.00			77.44	0.00	89.07	0.00	66.95	18.92	/workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.537989509
73.81	2.67	77.38	5.90	73.06	4.18	56.93	3.90			79.45	2.02	89.07	0.00	66.95	0.00	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3818854162
76.09	2.28	77.38	0.00	73.06	0.00	70.60	13.67			79.45	0.00	89.07	0.00	66.95	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.457958405
77.95	1.86	77.38	0.00	73.41	0.35	70.60	0.00			79.52	0.07	89.07	0.00	77.70	10.75	/workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2594393142
79.69	1.74	80.20	2.82	77.04	3.63	71.24	0.65			82.69	3.17	89.26	0.19	77.70	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4124818394
81.29	1.60	82.66	2.46	78.63	1.59	73.88	2.63			84.88	2.19	90.00	0.74	77.70	0.00	/workspace/coverage/default/53.chip_sw_all_escalation_resets.686595432
82.60	1.31	84.86	2.21	80.63	2.00	75.16	1.29			87.26	2.39	90.00	0.00	77.70	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1723396424
83.65	1.05	86.43	1.56	81.78	1.15	75.71	0.55			88.61	1.34	91.67	1.67	77.70	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1431804265
84.68	1.03	86.43	0.00	82.81	1.03	75.71	0.00			88.81	0.20	91.67	0.00	82.65	4.95	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.344526933
85.55	0.87	87.19	0.76	82.98	0.17	75.74	0.02			89.03	0.22	95.74	4.07	82.65	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1822556038
86.37	0.82	87.19	0.00	83.09	0.11	75.74	0.00			89.03	0.00	95.74	0.00	87.44	4.79	/workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1568960880
87.02	0.64	88.57	1.37	84.07	0.99	76.23	0.50			89.85	0.82	95.93	0.19	87.44	0.00	/workspace/coverage/default/2.chip_sw_gpio.3014992094
87.61	0.60	88.60	0.03	84.07	0.00	79.78	3.55			89.85	0.00	95.93	0.00	87.44	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3615426889
88.12	0.51	88.68	0.08	84.27	0.20	81.29	1.51			89.85	0.00	95.93	0.00	88.69	1.25	/workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.529990990
88.60	0.48	89.55	0.88	84.82	0.55	81.93	0.63			90.70	0.84	95.93	0.00	88.69	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2884372705
89.08	0.48	89.55	0.00	84.82	0.00	81.93	0.00			90.70	0.00	95.93	0.00	91.54	2.86	/workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.2417437710
89.54	0.46	89.56	0.01	87.16	2.34	81.93	0.01			90.70	0.00	95.93	0.00	91.94	0.40	/workspace/coverage/cover_reg_top/20.chip_tl_errors.1782267781
89.99	0.46	89.56	0.00	87.16	0.00	81.93	0.00			90.70	0.00	95.93	0.00	94.68	2.74	/workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2780828908
90.35	0.36	89.79	0.22	87.24	0.08	83.57	1.64			90.89	0.19	95.93	0.00	94.68	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.3899040653
90.70	0.35	90.32	0.53	87.75	0.51	84.14	0.57			91.38	0.49	95.93	0.00	94.68	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.30288798
91.03	0.33	90.72	0.40	88.59	0.84	84.53	0.39			91.73	0.35	95.93	0.00	94.68	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3994835792
91.33	0.30	91.66	0.94	88.99	0.40	84.72	0.19			91.98	0.25	95.93	0.00	94.68	0.00	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2258411653
91.60	0.27	92.15	0.49	89.34	0.35	84.94	0.22			92.56	0.57	95.93	0.00	94.68	0.00	/workspace/coverage/default/2.chip_sw_otbn_randomness.3733267150
91.87	0.27	92.89	0.74	89.34	0.00	85.17	0.23			92.56	0.00	95.93	0.00	95.30	0.62	/workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.2717052639
92.13	0.26	92.89	0.00	89.34	0.00	85.17	0.00			92.56	0.00	95.93	0.00	96.87	1.57	/workspace/coverage/cover_reg_top/51.xbar_stress_all.1706274892
92.35	0.22	92.97	0.07	89.37	0.03	86.36	1.19			92.59	0.03	95.93	0.00	96.87	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.390579072
92.56	0.21	92.97	0.00	89.37	0.00	87.64	1.28			92.59	0.00	95.93	0.00	96.87	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2892311647
92.74	0.18	93.07	0.10	89.82	0.44	87.68	0.05			93.05	0.46	95.93	0.00	96.87	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1239697528
92.88	0.15	93.07	0.00	89.82	0.00	88.35	0.67			93.05	0.00	96.11	0.19	96.91	0.04	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.513899474
93.03	0.14	93.32	0.25	90.06	0.24	88.40	0.05			93.35	0.30	96.11	0.00	96.91	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1765402221
93.16	0.14	93.47	0.15	90.19	0.13	88.80	0.40			93.50	0.15	96.11	0.00	96.92	0.01	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1913286690
93.30	0.13	93.47	0.00	90.25	0.06	88.80	0.00			93.50	0.00	96.11	0.00	97.65	0.73	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.1842969400
93.41	0.11	93.47	0.00	90.25	0.00	89.47	0.68			93.50	0.00	96.11	0.00	97.65	0.00	/workspace/coverage/cover_reg_top/2.chip_prim_tl_access.1593773968
93.51	0.11	93.47	0.00	90.26	0.02	89.47	0.00			93.50	0.00	96.11	0.00	98.27	0.62	/workspace/coverage/cover_reg_top/56.xbar_random_large_delays.3312196593
93.61	0.10	93.58	0.11	90.42	0.16	89.72	0.25			93.57	0.07	96.11	0.00	98.27	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3534839642
93.71	0.10	93.75	0.17	90.68	0.26	89.88	0.16			93.57	0.00	96.11	0.00	98.27	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1442856049
93.81	0.10	93.76	0.01	90.75	0.06	90.18	0.30			93.60	0.02	96.30	0.19	98.27	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3894190123
93.89	0.08	93.81	0.05	90.95	0.20	90.19	0.02			93.82	0.22	96.30	0.00	98.27	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3581000121
93.96	0.08	93.81	0.00	91.39	0.44	90.19	0.00			93.82	0.00	96.30	0.00	98.28	0.01	/workspace/coverage/cover_reg_top/12.chip_tl_errors.2992968008
94.04	0.07	93.93	0.12	91.63	0.24	90.21	0.02			93.87	0.05	96.30	0.00	98.28	0.00	/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1880576169
94.10	0.07	94.05	0.12	91.73	0.10	90.28	0.07			93.98	0.11	96.30	0.00	98.28	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.281007648
94.17	0.07	94.05	0.00	91.73	0.00	90.67	0.39			93.98	0.00	96.30	0.00	98.28	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.732348657
94.22	0.06	94.18	0.13	91.76	0.04	90.81	0.14			94.00	0.02	96.30	0.00	98.28	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.2907983401
94.28	0.05	94.25	0.07	91.92	0.15	90.81	0.00			94.10	0.10	96.30	0.00	98.28	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3374251857
94.32	0.05	94.28	0.03	91.94	0.03	90.82	0.01			94.12	0.02	96.48	0.19	98.30	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.4098519337
94.36	0.04	94.29	0.01	91.96	0.01	90.82	0.00			94.15	0.02	96.67	0.19	98.31	0.01	/workspace/coverage/default/35.chip_sw_all_escalation_resets.3038039186
94.40	0.04	94.30	0.01	91.97	0.02	90.82	0.00			94.16	0.01	96.85	0.19	98.32	0.01	/workspace/coverage/default/84.chip_sw_all_escalation_resets.2846549826
94.44	0.04	94.30	0.01	91.99	0.01	90.82	0.01			94.16	0.01	97.04	0.19	98.33	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1540355315
94.48	0.04	94.30	0.01	92.00	0.01	90.83	0.01			94.17	0.01	97.22	0.19	98.34	0.01	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1595744592
94.51	0.03	94.36	0.06	92.04	0.04	90.90	0.07			94.20	0.02	97.22	0.00	98.36	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1873244257
94.55	0.03	94.36	0.00	92.24	0.20	90.90	0.00			94.20	0.00	97.22	0.00	98.36	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.2729666181
94.58	0.03	94.36	0.00	92.24	0.00	90.90	0.00			94.20	0.00	97.41	0.19	98.36	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1658540381
94.61	0.03	94.36	0.00	92.41	0.18	90.90	0.00			94.20	0.00	97.41	0.00	98.36	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2598563005
94.63	0.03	94.36	0.00	92.41	0.00	91.07	0.16			94.20	0.00	97.41	0.00	98.36	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3605256739
94.66	0.03	94.43	0.07	92.48	0.06	91.07	0.01			94.22	0.02	97.41	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.839771768
94.69	0.03	94.44	0.01	92.49	0.01	91.20	0.14			94.22	0.00	97.41	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.3405034085
94.71	0.02	94.44	0.00	92.56	0.07	91.20	0.00			94.24	0.02	97.41	0.00	98.40	0.05	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3113901523
94.73	0.02	94.44	0.00	92.66	0.10	91.20	0.00			94.27	0.03	97.41	0.00	98.40	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.711192028
94.75	0.02	94.51	0.07	92.70	0.05	91.20	0.00			94.29	0.02	97.41	0.00	98.40	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1898526416
94.77	0.02	94.51	0.00	92.75	0.05	91.20	0.00			94.29	0.00	97.41	0.00	98.48	0.08	/workspace/coverage/cover_reg_top/80.xbar_stress_all.3015270119
94.79	0.02	94.51	0.00	92.75	0.00	91.33	0.13			94.29	0.00	97.41	0.00	98.48	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3154505994
94.81	0.02	94.54	0.03	92.80	0.05	91.34	0.01			94.31	0.02	97.41	0.00	98.48	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.975056439
94.83	0.02	94.55	0.01	92.87	0.07	91.34	0.00			94.33	0.02	97.41	0.00	98.50	0.01	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1082518213
94.85	0.02	94.57	0.02	92.88	0.01	91.41	0.07			94.34	0.02	97.41	0.00	98.50	0.00	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3081820188
94.86	0.02	94.57	0.00	92.95	0.08	91.41	0.00			94.36	0.02	97.41	0.00	98.50	0.00	/workspace/coverage/cover_reg_top/95.xbar_stress_all.3088576068
94.88	0.01	94.57	0.00	93.04	0.09	91.41	0.00			94.36	0.00	97.41	0.00	98.50	0.00	/workspace/coverage/cover_reg_top/18.chip_tl_errors.398393128
94.89	0.01	94.60	0.04	93.06	0.01	91.44	0.03			94.37	0.01	97.41	0.00	98.50	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.2521219555
94.91	0.01	94.62	0.01	93.08	0.03	91.46	0.02			94.39	0.02	97.41	0.00	98.50	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3518027479
94.92	0.01	94.62	0.00	93.17	0.08	91.46	0.00			94.39	0.00	97.41	0.00	98.50	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.4095073122
94.93	0.01	94.63	0.02	93.19	0.03	91.49	0.03			94.39	0.00	97.41	0.00	98.50	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.4005402106
94.95	0.01	94.63	0.00	93.19	0.00	91.49	0.00			94.39	0.00	97.41	0.00	98.57	0.07	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2098528982
94.96	0.01	94.63	0.00	93.21	0.02	91.49	0.00			94.39	0.00	97.41	0.00	98.61	0.05	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3074613965
94.97	0.01	94.65	0.02	93.21	0.00	91.53	0.04			94.39	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_power_sleep_load.4215769758
94.98	0.01	94.65	0.00	93.21	0.00	91.59	0.06			94.39	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.332597644
94.99	0.01	94.65	0.00	93.25	0.04	91.59	0.00			94.40	0.02	97.41	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2910952660
95.00	0.01	94.65	0.00	93.27	0.02	91.63	0.04			94.40	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/1.rom_e2e_smoke.3608872319
95.01	0.01	94.65	0.00	93.29	0.02	91.66	0.03			94.40	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.729310342
95.01	0.01	94.65	0.00	93.31	0.02	91.66	0.00			94.40	0.00	97.41	0.00	98.64	0.02	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3925325116
95.02	0.01	94.65	0.00	93.35	0.04	91.66	0.00			94.40	0.00	97.41	0.00	98.64	0.00	/workspace/coverage/cover_reg_top/14.chip_tl_errors.4144013940
95.03	0.01	94.65	0.00	93.39	0.04	91.66	0.00			94.40	0.00	97.41	0.00	98.64	0.00	/workspace/coverage/cover_reg_top/66.xbar_stress_all.1483661338
95.03	0.01	94.68	0.02	93.40	0.01	91.67	0.01			94.40	0.00	97.41	0.00	98.64	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.618312776
95.04	0.01	94.68	0.00	93.43	0.04	91.67	0.00			94.40	0.00	97.41	0.00	98.64	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.1276937523
95.04	0.01	94.68	0.00	93.44	0.01	91.70	0.03			94.40	0.00	97.41	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3247872985
95.05	0.01	94.68	0.00	93.44	0.00	91.70	0.00			94.40	0.00	97.41	0.00	98.67	0.04	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2985515945
95.05	0.01	94.68	0.00	93.44	0.00	91.73	0.04			94.40	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.372673755
95.06	0.01	94.68	0.01	93.46	0.02	91.75	0.01			94.40	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.655515109
95.07	0.01	94.68	0.00	93.46	0.00	91.78	0.03			94.40	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_flash_init.735078525
95.07	0.01	94.68	0.00	93.49	0.03	91.78	0.00			94.40	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2218559825
95.08	0.01	94.68	0.00	93.52	0.03	91.78	0.01			94.40	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.4150609538
95.08	0.01	94.68	0.00	93.52	0.00	91.81	0.03			94.40	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.621918679
95.09	0.01	94.68	0.00	93.55	0.03	91.81	0.00			94.40	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/cover_reg_top/10.xbar_stress_all.597586336
95.09	0.01	94.68	0.00	93.55	0.01	91.81	0.00			94.40	0.00	97.41	0.00	98.70	0.02	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1318524698
95.10	0.01	94.68	0.00	93.56	0.01	91.81	0.00			94.40	0.00	97.41	0.00	98.71	0.01	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.621322267
95.10	0.01	94.68	0.00	93.59	0.03	91.81	0.00			94.40	0.00	97.41	0.00	98.71	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3255061684
95.10	0.01	94.69	0.01	93.60	0.01	91.82	0.01			94.40	0.00	97.41	0.00	98.71	0.00	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.649776273
95.11	0.01	94.69	0.00	93.60	0.00	91.82	0.00			94.40	0.00	97.41	0.00	98.73	0.02	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.1926487801
95.11	0.01	94.69	0.00	93.60	0.00	91.82	0.00			94.40	0.00	97.41	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1749064938
95.11	0.01	94.69	0.00	93.60	0.01	91.82	0.00			94.42	0.02	97.41	0.00	98.75	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1624907741
95.12	0.01	94.69	0.00	93.60	0.00	91.84	0.02			94.42	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/2.chip_sw_flash_init.4140085152
95.12	0.01	94.69	0.00	93.62	0.02	91.84	0.00			94.42	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.4023626330
95.12	0.01	94.69	0.00	93.62	0.01	91.85	0.01			94.42	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.3164813723
95.13	0.01	94.69	0.00	93.62	0.00	91.86	0.01			94.42	0.00	97.41	0.00	98.77	0.01	/workspace/coverage/default/59.chip_sw_all_escalation_resets.4224735521
95.13	0.01	94.70	0.01	93.62	0.00	91.86	0.01			94.42	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.3946219326
95.13	0.01	94.70	0.00	93.62	0.01	91.86	0.00			94.42	0.00	97.41	0.00	98.78	0.01	/workspace/coverage/cover_reg_top/0.xbar_stress_all.3655230404
95.13	0.01	94.70	0.00	93.64	0.01	91.86	0.00			94.42	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/40.xbar_access_same_device.445531347
95.14	0.01	94.70	0.00	93.65	0.01	91.86	0.00			94.42	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2297829131
95.14	0.01	94.70	0.00	93.66	0.01	91.87	0.01			94.42	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.711005549
95.14	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.79	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1291351138
95.14	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.80	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.1934884405
95.14	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.81	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1467850434
95.15	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.83	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2215669376
95.15	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.84	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.451365344
95.15	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.85	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2368379407
95.15	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.86	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2356946689
95.15	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.87	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1454811793
95.16	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.88	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1148628307
95.16	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.90	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.823049259
95.16	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.91	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2598948483
95.16	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.92	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3001210917
95.16	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.93	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.503113613
95.17	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.94	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1407918101
95.17	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.95	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2992407270
95.17	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.97	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1673582268
95.17	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.98	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.3831068290
95.17	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	98.99	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.255163059
95.18	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.00	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3852747537
95.18	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.01	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.525447550
95.18	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.02	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2350760667
95.18	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.04	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.1599643220
95.18	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.05	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1996612902
95.19	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.06	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.1384128233
95.19	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.07	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1607529364
95.19	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.08	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1562425676
95.19	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.10	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.100487673
95.19	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.11	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.1168704827
95.20	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.12	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.395745072
95.20	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.13	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.1550088079
95.20	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.14	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.970046680
95.20	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.15	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.805092864
95.20	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.17	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860912260
95.21	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.18	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.3215477831
95.21	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.19	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2364886895
95.21	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.20	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.522018729
95.21	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.21	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3454869491
95.21	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.22	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.301339847
95.22	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.24	0.01	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.629052547
95.22	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.25	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3845754352
95.22	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.26	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.6510157
95.22	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.27	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2036191007
95.22	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.28	0.01	/workspace/coverage/default/38.chip_sw_all_escalation_resets.2764618917
95.22	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.30	0.01	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.4013150219
95.23	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.31	0.01	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2963375532
95.23	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.32	0.01	/workspace/coverage/default/41.chip_sw_all_escalation_resets.2583778363
95.23	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.33	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.4258525762
95.23	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.34	0.01	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.747197834
95.23	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.35	0.01	/workspace/coverage/default/44.chip_sw_all_escalation_resets.2972521155
95.24	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.37	0.01	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.326582438
95.24	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.38	0.01	/workspace/coverage/default/45.chip_sw_all_escalation_resets.345831957
95.24	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.39	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.2881579989
95.24	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.40	0.01	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3819880153
95.24	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.41	0.01	/workspace/coverage/default/52.chip_sw_all_escalation_resets.1866709232
95.25	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.42	0.01	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1481503703
95.25	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.44	0.01	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1486100839
95.25	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.45	0.01	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1005866704
95.25	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.46	0.01	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.31732570
95.25	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.47	0.01	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3629853433
95.26	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.48	0.01	/workspace/coverage/default/63.chip_sw_all_escalation_resets.1081698688
95.26	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/65.chip_sw_all_escalation_resets.2566897085
95.26	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.962298874
95.26	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.24614173
95.26	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2913875108
95.27	0.01	94.70	0.00	93.66	0.00	91.87	0.00			94.42	0.00	97.41	0.00	99.54	0.01	/workspace/coverage/default/85.chip_sw_all_escalation_resets.1480827624
95.27	0.01	94.70	0.00	93.66	0.00	91.88	0.01			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_kmac_entropy.883950787
95.27	0.01	94.70	0.00	93.67	0.01	91.88	0.00			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2841034511
95.27	0.01	94.70	0.00	93.68	0.01	91.88	0.00			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3215096170
95.27	0.01	94.70	0.00	93.69	0.01	91.88	0.00			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/15.chip_tl_errors.3334227921
95.28	0.01	94.70	0.00	93.70	0.01	91.88	0.00			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/68.xbar_stress_all.3682146744
95.28	0.01	94.70	0.00	93.71	0.01	91.88	0.00			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.375806184
95.28	0.01	94.70	0.00	93.72	0.01	91.88	0.00			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3657512641
95.28	0.01	94.71	0.01	93.72	0.01	91.88	0.00			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.241744779
95.28	0.01	94.71	0.01	93.72	0.00	91.89	0.01			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1399411451
95.28	0.01	94.71	0.01	93.72	0.00	91.90	0.01			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/17.chip_sw_all_escalation_resets.398952471
95.29	0.01	94.71	0.00	93.72	0.00	91.91	0.01			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.187658834
95.29	0.01	94.71	0.00	93.72	0.00	91.92	0.01			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2138285117
95.29	0.01	94.71	0.00	93.72	0.00	91.93	0.01			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1336636187
95.29	0.01	94.71	0.00	93.72	0.00	91.93	0.01			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2015880085
95.29	0.01	94.72	0.01	93.72	0.00	91.94	0.01			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.1139148612
95.29	0.01	94.72	0.00	93.72	0.00	91.95	0.01			94.42	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3280272649
95.29	0.01	94.72	0.00	93.72	0.00	91.95	0.00			94.43	0.01	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2565685607
95.30	0.01	94.72	0.00	93.72	0.00	91.95	0.00			94.43	0.01	97.41	0.00	99.54	0.00	/workspace/coverage/default/2.chip_tap_straps_dev.4095124637
95.30	0.01	94.72	0.00	93.73	0.01	91.95	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.648833592
95.30	0.01	94.72	0.00	93.74	0.01	91.95	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/24.chip_tl_errors.4246661655
95.30	0.01	94.72	0.00	93.75	0.01	91.95	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.240118562
95.30	0.01	94.73	0.01	93.75	0.00	91.95	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2179707358
95.30	0.01	94.73	0.01	93.75	0.00	91.95	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.2930470318
95.30	0.01	94.73	0.00	93.75	0.00	91.95	0.01			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.690259009
95.30	0.01	94.73	0.00	93.75	0.00	91.96	0.01			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2848695334
95.30	0.01	94.73	0.00	93.75	0.00	91.96	0.01			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3191181863
95.31	0.01	94.73	0.00	93.75	0.00	91.97	0.01			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2529469786
95.31	0.01	94.73	0.00	93.75	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_rw.3313811567
95.31	0.01	94.73	0.00	93.75	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.882570576
95.31	0.01	94.73	0.00	93.76	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.439707023
95.31	0.01	94.73	0.00	93.76	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.996232786
95.31	0.01	94.73	0.00	93.76	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.335033085
95.31	0.01	94.73	0.00	93.77	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3529171178
95.31	0.01	94.73	0.00	93.77	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.2701354688
95.31	0.01	94.73	0.00	93.78	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3819766414
95.31	0.01	94.73	0.00	93.78	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3127345792
95.31	0.01	94.73	0.00	93.78	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.2285096269
95.31	0.01	94.73	0.00	93.79	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.1555316792
95.31	0.01	94.73	0.00	93.79	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.1524571620
95.31	0.01	94.73	0.00	93.79	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.3593962831
95.31	0.01	94.73	0.00	93.80	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2794410189
95.31	0.01	94.73	0.00	93.80	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4252895134
95.31	0.01	94.73	0.00	93.80	0.01	91.97	0.00			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_gpio.2779300877
95.32	0.01	94.73	0.00	93.80	0.00	91.97	0.01			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1903404922
95.32	0.01	94.73	0.00	93.80	0.00	91.97	0.01			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3793808609
95.32	0.01	94.73	0.00	93.80	0.00	91.97	0.01			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2522077187
95.32	0.01	94.73	0.00	93.80	0.00	91.97	0.01			94.43	0.00	97.41	0.00	99.54	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2016858483

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3801299384
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3498928180
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.798643823
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3782569497
/workspace/coverage/cover_reg_top/0.chip_tl_errors.2186577774
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.606496459
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2526469100
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3399820283
/workspace/coverage/cover_reg_top/0.xbar_error_random.3572840726
/workspace/coverage/cover_reg_top/0.xbar_random.689730130
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3448922637
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.176108097
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2883473692
/workspace/coverage/cover_reg_top/0.xbar_same_source.2367996011
/workspace/coverage/cover_reg_top/0.xbar_smoke.1218235118
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3931318537
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1462705640
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.275141238
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3397689092
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2677663571
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3554119487
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.4183436962
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.435707662
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1141913891
/workspace/coverage/cover_reg_top/1.chip_csr_rw.595956672
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1000793216
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3940661348
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.3087871258
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.613549597
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.188690467
/workspace/coverage/cover_reg_top/1.xbar_error_random.2153973147
/workspace/coverage/cover_reg_top/1.xbar_random.2139651906
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.169660476
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.4179050515
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.561350322
/workspace/coverage/cover_reg_top/1.xbar_same_source.2273062008
/workspace/coverage/cover_reg_top/1.xbar_smoke.489950362
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3122045014
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2166603360
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1814687570
/workspace/coverage/cover_reg_top/1.xbar_stress_all.4130661650
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2683931910
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3013429309
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2447435849
/workspace/coverage/cover_reg_top/10.chip_csr_rw.750030465
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2608640909
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1642673824
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.265642393
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1040921671
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.784727147
/workspace/coverage/cover_reg_top/10.xbar_error_random.622614293
/workspace/coverage/cover_reg_top/10.xbar_random.1461908451
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.709530048
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.818562785
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.420468812
/workspace/coverage/cover_reg_top/10.xbar_same_source.2151673674
/workspace/coverage/cover_reg_top/10.xbar_smoke.3741508570
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2121186825
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2507773965
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.4021901229
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.364076750
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.177663553
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2014984779
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.778510696
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2160119719
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.4173998787
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2049326717
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3465991999
/workspace/coverage/cover_reg_top/11.xbar_error_random.3945777620
/workspace/coverage/cover_reg_top/11.xbar_random.43813
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.4086839544
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2503567109
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3875945504
/workspace/coverage/cover_reg_top/11.xbar_same_source.372710884
/workspace/coverage/cover_reg_top/11.xbar_smoke.3535876386
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2813325567
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1812343643
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2373760027
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3495272983
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1234020331
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2910008303
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.55679544
/workspace/coverage/cover_reg_top/12.chip_csr_rw.780871816
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.42093064
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.123112275
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3937518509
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.724609995
/workspace/coverage/cover_reg_top/12.xbar_error_random.1270351635
/workspace/coverage/cover_reg_top/12.xbar_random.3624480167
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2857119896
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1408388749
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1679781465
/workspace/coverage/cover_reg_top/12.xbar_same_source.56724931
/workspace/coverage/cover_reg_top/12.xbar_smoke.697707292
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2613832462
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2883693095
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.435479928
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1344482906
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2788698261
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.98419639
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3686748993
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3543477387
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3737645507
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2283449183
/workspace/coverage/cover_reg_top/13.chip_tl_errors.1466527566
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.176709468
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.4033977941
/workspace/coverage/cover_reg_top/13.xbar_error_random.864078755
/workspace/coverage/cover_reg_top/13.xbar_random.604305632
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1689312907
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1218768375
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1720416298
/workspace/coverage/cover_reg_top/13.xbar_same_source.1314474882
/workspace/coverage/cover_reg_top/13.xbar_smoke.3118092151
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.1694159271
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1622285326
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.746836870
/workspace/coverage/cover_reg_top/13.xbar_stress_all.208602697
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1778580657
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.983130112
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.506594893
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1833346589
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.3247241450
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1818407461
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2022526701
/workspace/coverage/cover_reg_top/14.xbar_error_random.966080826
/workspace/coverage/cover_reg_top/14.xbar_random.1218811050
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2977201637
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.972471870
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.84616252
/workspace/coverage/cover_reg_top/14.xbar_same_source.1051577879
/workspace/coverage/cover_reg_top/14.xbar_smoke.2165410079
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/workspace/coverage/default/90.chip_sw_all_escalation_resets.511583342
/workspace/coverage/default/91.chip_sw_all_escalation_resets.34332841
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3848058458
/workspace/coverage/default/93.chip_sw_all_escalation_resets.883313791
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2667678035
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2826552303
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3272284670
/workspace/coverage/default/97.chip_sw_all_escalation_resets.795457690
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2635414067
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2369639656
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1468715666
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2299206234
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2043014127
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3738744551
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2792240686
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3458900146
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.312531125
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.734492695

---

Total test records in report: 2731

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.4030530267			May 14 03:40:49 PM PDT 24	May 14 03:49:13 PM PDT 24	3612210210 ps
T2	/workspace/coverage/default/0.chip_sw_example_flash.853029097			May 14 03:31:00 PM PDT 24	May 14 03:35:18 PM PDT 24	2543402596 ps
T3	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2884372705			May 14 03:31:01 PM PDT 24	May 14 03:41:14 PM PDT 24	4082310360 ps
T59	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2179707358			May 14 03:34:33 PM PDT 24	May 14 03:49:11 PM PDT 24	5451144982 ps
T29	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1064054337			May 14 03:38:45 PM PDT 24	May 14 03:47:54 PM PDT 24	4693217800 ps
T94	/workspace/coverage/default/2.chip_sw_otbn_smoketest.3839442004			May 14 03:51:47 PM PDT 24	May 14 04:15:53 PM PDT 24	6619229640 ps
T30	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3275796893			May 14 03:36:06 PM PDT 24	May 14 03:55:29 PM PDT 24	7738443308 ps
T60	/workspace/coverage/default/2.chip_sw_otbn_randomness.3733267150			May 14 03:46:09 PM PDT 24	May 14 04:03:23 PM PDT 24	5715051590 ps
T100	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.4101302256			May 14 03:32:58 PM PDT 24	May 14 03:52:27 PM PDT 24	5492420634 ps
T116	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2848695334			May 14 03:34:50 PM PDT 24	May 14 03:44:11 PM PDT 24	3031747808 ps
T34	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1442505457			May 14 03:46:39 PM PDT 24	May 14 03:53:15 PM PDT 24	5740384052 ps
T31	/workspace/coverage/default/53.chip_sw_all_escalation_resets.686595432			May 14 03:57:28 PM PDT 24	May 14 04:07:25 PM PDT 24	4649732920 ps
T61	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2783143034			May 14 03:32:23 PM PDT 24	May 14 03:43:14 PM PDT 24	4748624796 ps
T194	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.649776273			May 14 03:34:50 PM PDT 24	May 14 03:50:08 PM PDT 24	4720207658 ps
T106	/workspace/coverage/default/0.chip_sw_power_sleep_load.4215769758			May 14 03:35:32 PM PDT 24	May 14 03:47:03 PM PDT 24	11529875386 ps
T237	/workspace/coverage/default/2.chip_sw_aon_timer_irq.4229226726			May 14 03:46:09 PM PDT 24	May 14 03:53:59 PM PDT 24	3930459452 ps
T46	/workspace/coverage/default/0.chip_tap_straps_rma.3899040653			May 14 03:31:39 PM PDT 24	May 14 03:33:55 PM PDT 24	2094094996 ps
T62	/workspace/coverage/default/1.chip_sw_alert_test.1776455629			May 14 03:36:35 PM PDT 24	May 14 03:41:55 PM PDT 24	2879265480 ps
T88	/workspace/coverage/default/59.chip_sw_all_escalation_resets.4224735521			May 14 03:57:28 PM PDT 24	May 14 04:08:39 PM PDT 24	4650259348 ps
T339	/workspace/coverage/default/0.chip_sw_hmac_smoketest.1757946056			May 14 03:33:47 PM PDT 24	May 14 03:39:23 PM PDT 24	3963669560 ps
T4	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2070887713			May 14 03:45:19 PM PDT 24	May 14 04:38:04 PM PDT 24	35750448671 ps
T89	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.2907983401			May 14 03:32:27 PM PDT 24	May 14 03:42:54 PM PDT 24	4960483832 ps
T35	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.486419381			May 14 03:35:45 PM PDT 24	May 14 03:45:13 PM PDT 24	5619211860 ps
T193	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4256192314			May 14 03:43:28 PM PDT 24	May 14 03:54:22 PM PDT 24	5151482500 ps
T99	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1913286690			May 14 03:45:59 PM PDT 24	May 14 04:17:36 PM PDT 24	23043912993 ps
T98	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.457958405			May 14 03:32:52 PM PDT 24	May 14 04:25:58 PM PDT 24	14998942830 ps
T259	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.971761174			May 14 03:33:04 PM PDT 24	May 14 03:45:54 PM PDT 24	5003592858 ps
T47	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3081820188			May 14 03:49:48 PM PDT 24	May 14 03:58:09 PM PDT 24	3778714850 ps
T162	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2300343319			May 14 03:32:24 PM PDT 24	May 14 03:37:05 PM PDT 24	2721290429 ps
T18	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3976199098			May 14 03:47:43 PM PDT 24	May 14 04:42:23 PM PDT 24	20118622350 ps
T260	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3649514718			May 14 03:33:44 PM PDT 24	May 14 03:51:24 PM PDT 24	6561878255 ps
T144	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2258411653			May 14 03:54:57 PM PDT 24	May 14 04:01:07 PM PDT 24	4188308428 ps
T215	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2052827854			May 14 03:37:33 PM PDT 24	May 14 03:44:50 PM PDT 24	3745648720 ps
T15	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1126910043			May 14 03:49:56 PM PDT 24	May 14 04:13:05 PM PDT 24	19855957800 ps
T129	/workspace/coverage/default/0.chip_sw_aes_entropy.1795586950			May 14 03:33:15 PM PDT 24	May 14 03:38:52 PM PDT 24	2820886910 ps
T48	/workspace/coverage/default/3.chip_tap_straps_prod.1882125951			May 14 03:52:57 PM PDT 24	May 14 03:56:07 PM PDT 24	2605730882 ps
T130	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2036191007			May 14 03:59:12 PM PDT 24	May 14 04:05:17 PM PDT 24	3801685944 ps
T131	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1873244257			May 14 03:52:13 PM PDT 24	May 14 04:03:18 PM PDT 24	5568604188 ps
T132	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.597592047			May 14 03:32:37 PM PDT 24	May 14 03:48:18 PM PDT 24	5030137848 ps
T133	/workspace/coverage/default/0.chip_sw_edn_sw_mode.1313271974			May 14 03:32:55 PM PDT 24	May 14 04:08:18 PM PDT 24	9124109248 ps
T134	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2173339229			May 14 03:37:15 PM PDT 24	May 14 03:54:12 PM PDT 24	5226507164 ps
T135	/workspace/coverage/default/72.chip_sw_all_escalation_resets.205725322			May 14 04:00:04 PM PDT 24	May 14 04:10:43 PM PDT 24	4772824100 ps
T136	/workspace/coverage/default/39.chip_sw_all_escalation_resets.1181956566			May 14 03:58:51 PM PDT 24	May 14 04:07:55 PM PDT 24	4368357736 ps
T311	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1562134419			May 14 03:36:40 PM PDT 24	May 14 04:09:54 PM PDT 24	9935858156 ps
T145	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.145684278			May 14 03:56:21 PM PDT 24	May 14 04:03:22 PM PDT 24	4165027024 ps
T82	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2899762949			May 14 03:48:59 PM PDT 24	May 14 04:00:53 PM PDT 24	4386984300 ps
T696	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.281596311			May 14 03:58:25 PM PDT 24	May 14 04:07:18 PM PDT 24	3606418666 ps
T323	/workspace/coverage/default/70.chip_sw_all_escalation_resets.1281844306			May 14 04:00:47 PM PDT 24	May 14 04:11:12 PM PDT 24	5072447976 ps
T359	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.913362074			May 14 03:40:01 PM PDT 24	May 14 03:59:04 PM PDT 24	6248033814 ps
T893	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2249384452			May 14 03:50:28 PM PDT 24	May 14 03:54:44 PM PDT 24	3092930523 ps
T208	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.210754534			May 14 03:53:41 PM PDT 24	May 14 04:20:25 PM PDT 24	7767212400 ps
T693	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2992407270			May 14 03:55:16 PM PDT 24	May 14 04:02:02 PM PDT 24	3988099500 ps
T312	/workspace/coverage/default/12.chip_sw_all_escalation_resets.332418698			May 14 03:54:07 PM PDT 24	May 14 04:04:55 PM PDT 24	6131963040 ps
T73	/workspace/coverage/default/0.chip_sival_flash_info_access.2079641221			May 14 03:33:20 PM PDT 24	May 14 03:38:41 PM PDT 24	2562242484 ps
T137	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.380194141			May 14 03:36:17 PM PDT 24	May 14 04:40:16 PM PDT 24	18429098371 ps
T324	/workspace/coverage/default/89.chip_sw_all_escalation_resets.306001526			May 14 03:59:24 PM PDT 24	May 14 04:10:02 PM PDT 24	5578819534 ps
T77	/workspace/coverage/default/0.rom_keymgr_functest.1127377580			May 14 03:34:46 PM PDT 24	May 14 03:42:43 PM PDT 24	4556708570 ps
T199	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.913480827			May 14 03:48:09 PM PDT 24	May 14 04:48:24 PM PDT 24	15051627640 ps
T168	/workspace/coverage/default/0.chip_sw_edn_auto_mode.732348657			May 14 03:32:49 PM PDT 24	May 14 03:53:07 PM PDT 24	4923355464 ps
T5	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3615426889			May 14 03:38:46 PM PDT 24	May 14 03:54:22 PM PDT 24	6500614222 ps
T174	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1442856049			May 14 03:35:16 PM PDT 24	May 14 03:43:23 PM PDT 24	5463532660 ps
T894	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3463542572			May 14 03:51:02 PM PDT 24	May 14 04:01:04 PM PDT 24	3593749540 ps
T321	/workspace/coverage/default/77.chip_sw_all_escalation_resets.282498302			May 14 04:01:15 PM PDT 24	May 14 04:12:25 PM PDT 24	6012001038 ps
T206	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2115961110			May 14 03:47:28 PM PDT 24	May 14 03:58:52 PM PDT 24	4738291244 ps
T364	/workspace/coverage/default/73.chip_sw_all_escalation_resets.1909580074			May 14 04:00:35 PM PDT 24	May 14 04:12:23 PM PDT 24	6220576632 ps
T6	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.4071585113			May 14 03:46:11 PM PDT 24	May 14 03:55:21 PM PDT 24	6612257574 ps
T314	/workspace/coverage/default/95.chip_sw_all_escalation_resets.2826552303			May 14 03:59:41 PM PDT 24	May 14 04:09:22 PM PDT 24	4446795000 ps
T213	/workspace/coverage/default/1.chip_sw_pattgen_ios.2930470318			May 14 03:32:21 PM PDT 24	May 14 03:36:50 PM PDT 24	3153258280 ps
T238	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1442552016			May 14 03:49:19 PM PDT 24	May 14 05:14:15 PM PDT 24	21355543960 ps
T895	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2988593014			May 14 03:45:35 PM PDT 24	May 14 03:50:06 PM PDT 24	2843805660 ps
T313	/workspace/coverage/default/48.chip_sw_all_escalation_resets.214382911			May 14 03:57:01 PM PDT 24	May 14 04:07:45 PM PDT 24	4338758320 ps
T896	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.774947953			May 14 03:35:30 PM PDT 24	May 14 03:44:15 PM PDT 24	4774547646 ps
T225	/workspace/coverage/default/22.chip_sw_all_escalation_resets.4098519337			May 14 03:55:06 PM PDT 24	May 14 04:04:38 PM PDT 24	3904348360 ps
T16	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1431804265			May 14 03:33:40 PM PDT 24	May 14 04:02:20 PM PDT 24	21176954320 ps
T83	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2812784617			May 14 03:47:23 PM PDT 24	May 14 03:53:41 PM PDT 24	3985909084 ps
T242	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.728775538			May 14 03:34:26 PM PDT 24	May 14 03:42:25 PM PDT 24	4136960400 ps
T243	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.407107381			May 14 03:32:34 PM PDT 24	May 14 03:43:20 PM PDT 24	4754818144 ps
T224	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.4086132988			May 14 03:51:23 PM PDT 24	May 14 04:03:37 PM PDT 24	5679489384 ps
T157	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2659086025			May 14 03:32:16 PM PDT 24	May 14 03:43:08 PM PDT 24	4500607056 ps
T207	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3371148030			May 14 03:36:52 PM PDT 24	May 14 03:42:03 PM PDT 24	3288279679 ps
T167	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3951928871			May 14 03:46:41 PM PDT 24	May 14 03:59:41 PM PDT 24	19355790630 ps
T43	/workspace/coverage/default/2.chip_tap_straps_rma.1058350861			May 14 03:50:03 PM PDT 24	May 14 03:55:41 PM PDT 24	4127078442 ps
T365	/workspace/coverage/default/91.chip_sw_all_escalation_resets.34332841			May 14 04:00:06 PM PDT 24	May 14 04:09:41 PM PDT 24	4209432868 ps
T214	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3567103172			May 14 03:35:52 PM PDT 24	May 14 03:44:09 PM PDT 24	3931578340 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.3651541771			May 14 03:32:44 PM PDT 24	May 14 03:42:58 PM PDT 24	4091945580 ps
T897	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3378293326			May 14 03:41:46 PM PDT 24	May 14 03:45:07 PM PDT 24	2729470268 ps
T347	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3912048890			May 14 03:49:41 PM PDT 24	May 14 04:09:51 PM PDT 24	7428011652 ps
T694	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3629853433			May 14 03:58:05 PM PDT 24	May 14 04:04:19 PM PDT 24	4100035736 ps
T175	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1765402221			May 14 03:34:41 PM PDT 24	May 14 03:50:19 PM PDT 24	7036903852 ps
T898	/workspace/coverage/default/0.chip_sw_csrng_smoketest.3832884296			May 14 03:34:00 PM PDT 24	May 14 03:38:23 PM PDT 24	3005104026 ps
T743	/workspace/coverage/default/79.chip_sw_all_escalation_resets.1447869598			May 14 04:00:56 PM PDT 24	May 14 04:10:08 PM PDT 24	6261582180 ps
T360	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3454869491			May 14 03:57:07 PM PDT 24	May 14 04:03:30 PM PDT 24	3618896428 ps
T148	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.4278286556			May 14 03:36:05 PM PDT 24	May 14 03:48:37 PM PDT 24	8334487234 ps
T149	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.855489321			May 14 03:49:42 PM PDT 24	May 14 04:00:59 PM PDT 24	7756165668 ps
T820	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2718667068			May 14 04:00:01 PM PDT 24	May 14 04:05:34 PM PDT 24	3294626114 ps
T44	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3838289843			May 14 03:34:12 PM PDT 24	May 14 03:42:26 PM PDT 24	4889642138 ps
T138	/workspace/coverage/default/0.chip_sw_otbn_smoketest.1817200443			May 14 03:34:53 PM PDT 24	May 14 04:16:00 PM PDT 24	10640626592 ps
T899	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1498005521			May 14 03:36:12 PM PDT 24	May 14 03:39:33 PM PDT 24	2505865008 ps
T294	/workspace/coverage/default/2.chip_sival_flash_info_access.3970229559			May 14 03:45:13 PM PDT 24	May 14 03:50:13 PM PDT 24	3545397420 ps
T235	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2064420595			May 14 03:34:34 PM PDT 24	May 14 03:37:36 PM PDT 24	2650006472 ps
T192	/workspace/coverage/default/1.chip_tap_straps_dev.4289015901			May 14 03:38:39 PM PDT 24	May 14 03:43:45 PM PDT 24	4265686151 ps
T900	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3172617955			May 14 03:38:38 PM PDT 24	May 14 03:42:26 PM PDT 24	2720250774 ps
T78	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.890951262			May 14 03:38:11 PM PDT 24	May 14 03:47:50 PM PDT 24	9177955376 ps
T697	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1481503703			May 14 03:59:02 PM PDT 24	May 14 04:07:36 PM PDT 24	3993427520 ps
T10	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2304894048			May 14 03:34:37 PM PDT 24	May 14 03:38:32 PM PDT 24	2477606248 ps
T791	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.4093882381			May 14 03:59:28 PM PDT 24	May 14 04:05:57 PM PDT 24	4113666354 ps
T317	/workspace/coverage/default/2.chip_sw_hmac_enc.4023023359			May 14 03:49:08 PM PDT 24	May 14 03:53:44 PM PDT 24	2449134170 ps
T150	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1822556038			May 14 03:34:37 PM PDT 24	May 14 03:39:04 PM PDT 24	2499211000 ps
T271	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3836323082			May 14 03:34:07 PM PDT 24	May 14 03:44:19 PM PDT 24	4365451094 ps
T185	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2198055670			May 14 03:53:33 PM PDT 24	May 14 04:36:43 PM PDT 24	13817049200 ps
T272	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1243551898			May 14 03:45:25 PM PDT 24	May 14 04:06:43 PM PDT 24	10700057898 ps
T273	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3589550455			May 14 03:45:53 PM PDT 24	May 14 04:13:05 PM PDT 24	17207551415 ps
T7	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4124818394			May 14 03:45:17 PM PDT 24	May 14 03:50:01 PM PDT 24	2756894491 ps
T105	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3669417721			May 14 03:41:20 PM PDT 24	May 14 03:48:35 PM PDT 24	4277938616 ps
T216	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3921752506			May 14 03:53:42 PM PDT 24	May 14 04:32:48 PM PDT 24	13692892308 ps
T212	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3413965489			May 14 03:45:23 PM PDT 24	May 14 03:51:05 PM PDT 24	3249156925 ps
T274	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3008376816			May 14 03:46:45 PM PDT 24	May 14 03:51:55 PM PDT 24	2677148640 ps
T901	/workspace/coverage/default/2.chip_sw_csrng_kat_test.3948252926			May 14 03:47:26 PM PDT 24	May 14 03:51:30 PM PDT 24	2711257424 ps
T342	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3364562905			May 14 04:00:17 PM PDT 24	May 14 04:07:28 PM PDT 24	4396022758 ps
T11	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.563559919			May 14 03:34:13 PM PDT 24	May 14 03:45:31 PM PDT 24	7157474794 ps
T49	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1624907741			May 14 03:34:06 PM PDT 24	May 14 03:41:40 PM PDT 24	5392423588 ps
T197	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1150438501			May 14 03:37:41 PM PDT 24	May 14 03:44:24 PM PDT 24	3828822490 ps
T277	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1540355315			May 14 03:54:57 PM PDT 24	May 14 04:01:27 PM PDT 24	3803577076 ps
T279	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2225479684			May 14 03:34:13 PM PDT 24	May 14 03:40:15 PM PDT 24	4736919198 ps
T154	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1636010489			May 14 03:40:03 PM PDT 24	May 14 03:43:41 PM PDT 24	2686107816 ps
T280	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1222744972			May 14 03:38:58 PM PDT 24	May 14 03:41:43 PM PDT 24	2321761960 ps
T281	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3391466820			May 14 03:57:37 PM PDT 24	May 14 04:14:07 PM PDT 24	5981495350 ps
T282	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.591723474			May 14 03:35:49 PM PDT 24	May 14 03:44:39 PM PDT 24	5248371320 ps
T37	/workspace/coverage/default/2.chip_sw_spi_device_tpm.1561043836			May 14 03:43:20 PM PDT 24	May 14 03:48:22 PM PDT 24	2656002203 ps
T198	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1601463042			May 14 03:47:24 PM PDT 24	May 14 04:13:35 PM PDT 24	8818585798 ps
T283	/workspace/coverage/default/62.chip_sw_all_escalation_resets.228946570			May 14 03:58:50 PM PDT 24	May 14 04:07:07 PM PDT 24	5390795980 ps
T236	/workspace/coverage/default/1.chip_sw_rv_timer_irq.2315205946			May 14 03:37:18 PM PDT 24	May 14 03:41:21 PM PDT 24	2782113588 ps
T200	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.11635200			May 14 03:36:20 PM PDT 24	May 14 03:55:02 PM PDT 24	6872001616 ps
T172	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3458901845			May 14 03:34:36 PM PDT 24	May 14 04:42:26 PM PDT 24	18596328759 ps
T304	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3978194478			May 14 03:51:35 PM PDT 24	May 14 03:55:32 PM PDT 24	2812514080 ps
T902	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.675027315			May 14 03:36:13 PM PDT 24	May 14 03:45:10 PM PDT 24	4682591016 ps
T903	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2112423590			May 14 03:34:07 PM PDT 24	May 14 03:47:49 PM PDT 24	7296515828 ps
T681	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.103528553			May 14 03:47:11 PM PDT 24	May 14 03:54:04 PM PDT 24	3403401480 ps
T159	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2900548610			May 14 03:33:03 PM PDT 24	May 14 03:37:04 PM PDT 24	2447581752 ps
T209	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.4005402106			May 14 03:52:41 PM PDT 24	May 14 04:02:21 PM PDT 24	4391408156 ps
T101	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1937941042			May 14 03:34:41 PM PDT 24	May 14 03:59:11 PM PDT 24	7883141658 ps
T904	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3434772128			May 14 03:32:43 PM PDT 24	May 14 03:36:16 PM PDT 24	3376754964 ps
T905	/workspace/coverage/default/2.rom_keymgr_functest.2286995318			May 14 03:52:42 PM PDT 24	May 14 04:02:07 PM PDT 24	4408261176 ps
T143	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3657512641			May 14 03:35:33 PM PDT 24	May 14 04:01:02 PM PDT 24	11403136392 ps
T698	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2683167179			May 14 03:57:20 PM PDT 24	May 14 04:02:09 PM PDT 24	3103575974 ps
T50	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.571369135			May 14 03:49:47 PM PDT 24	May 14 04:19:16 PM PDT 24	21304643802 ps
T158	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1188512676			May 14 03:36:23 PM PDT 24	May 14 03:49:16 PM PDT 24	4170888838 ps
T906	/workspace/coverage/default/1.chip_sw_example_concurrency.979846379			May 14 03:34:41 PM PDT 24	May 14 03:39:09 PM PDT 24	3380555112 ps
T907	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.453697575			May 14 03:53:12 PM PDT 24	May 14 04:01:47 PM PDT 24	6242947234 ps
T908	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.4092174538			May 14 03:48:01 PM PDT 24	May 14 03:51:46 PM PDT 24	2723108243 ps
T164	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3170457256			May 14 03:44:58 PM PDT 24	May 14 03:53:59 PM PDT 24	4372930218 ps
T36	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2320067449			May 14 03:41:20 PM PDT 24	May 14 03:48:11 PM PDT 24	4943827608 ps
T318	/workspace/coverage/default/1.chip_sw_hmac_enc.2865275201			May 14 03:36:55 PM PDT 24	May 14 03:42:50 PM PDT 24	3512925260 ps
T226	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1436328009			May 14 03:35:18 PM PDT 24	May 14 03:50:00 PM PDT 24	7587502096 ps
T909	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1532837796			May 14 03:51:34 PM PDT 24	May 14 03:55:59 PM PDT 24	2522084208 ps
T87	/workspace/coverage/default/21.chip_sw_all_escalation_resets.1384128233			May 14 03:56:12 PM PDT 24	May 14 04:07:04 PM PDT 24	5482255528 ps
T201	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2125197252			May 14 03:37:03 PM PDT 24	May 14 03:59:07 PM PDT 24	6853898458 ps
T244	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2465435674			May 14 03:35:30 PM PDT 24	May 14 03:43:02 PM PDT 24	9613446212 ps
T210	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.498254783			May 14 03:52:34 PM PDT 24	May 14 04:01:31 PM PDT 24	3064719421 ps
T8	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1239697528			May 14 03:32:49 PM PDT 24	May 14 03:37:34 PM PDT 24	3559143883 ps
T202	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.773398296			May 14 03:35:38 PM PDT 24	May 14 03:39:15 PM PDT 24	2411987310 ps
T13	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3177279108			May 14 03:37:29 PM PDT 24	May 14 03:46:09 PM PDT 24	4116288062 ps
T682	/workspace/coverage/default/26.chip_sw_all_escalation_resets.970046680			May 14 03:55:35 PM PDT 24	May 14 04:03:14 PM PDT 24	4411941312 ps
T71	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.372673755			May 14 03:34:45 PM PDT 24	May 14 03:57:07 PM PDT 24	8090929300 ps
T683	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.292645953			May 14 03:59:16 PM PDT 24	May 14 04:06:14 PM PDT 24	3649934954 ps
T297	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.241744779			May 14 03:32:51 PM PDT 24	May 14 03:48:53 PM PDT 24	5995533710 ps
T910	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1336938880			May 14 03:34:16 PM PDT 24	May 14 03:48:28 PM PDT 24	4615978620 ps
T695	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1799857481			May 14 03:59:44 PM PDT 24	May 14 04:07:03 PM PDT 24	4039880568 ps
T84	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.490653090			May 14 03:32:11 PM PDT 24	May 14 03:36:39 PM PDT 24	3184101216 ps
T911	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.24491793			May 14 03:37:19 PM PDT 24	May 14 03:48:19 PM PDT 24	5511255466 ps
T179	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3145549374			May 14 03:31:19 PM PDT 24	May 14 03:37:32 PM PDT 24	5778769880 ps
T736	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1784064434			May 14 03:57:52 PM PDT 24	May 14 04:03:42 PM PDT 24	4033868056 ps
T90	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.390579072			May 14 03:34:40 PM PDT 24	May 14 03:44:37 PM PDT 24	5323228868 ps
T344	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1162344250			May 14 03:33:43 PM PDT 24	May 14 03:37:12 PM PDT 24	2697906934 ps
T290	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.4150609538			May 14 03:32:04 PM PDT 24	May 14 03:42:32 PM PDT 24	4412831494 ps
T740	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2917501517			May 14 04:00:04 PM PDT 24	May 14 04:06:47 PM PDT 24	3925822144 ps
T744	/workspace/coverage/default/74.chip_sw_all_escalation_resets.3738871791			May 14 04:00:00 PM PDT 24	May 14 04:10:01 PM PDT 24	4357364608 ps
T912	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2353168841			May 14 03:41:17 PM PDT 24	May 14 03:58:56 PM PDT 24	7648616938 ps
T741	/workspace/coverage/default/69.chip_sw_all_escalation_resets.564802535			May 14 04:00:23 PM PDT 24	May 14 04:10:41 PM PDT 24	5126851364 ps
T176	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3017833983			May 14 03:54:21 PM PDT 24	May 14 04:06:02 PM PDT 24	5758088870 ps
T778	/workspace/coverage/default/37.chip_sw_all_escalation_resets.113409254			May 14 03:57:48 PM PDT 24	May 14 04:08:12 PM PDT 24	5829090972 ps
T14	/workspace/coverage/default/2.chip_sw_gpio_smoketest.984375430			May 14 03:50:33 PM PDT 24	May 14 03:54:09 PM PDT 24	2960518981 ps
T186	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2795334721			May 14 03:54:06 PM PDT 24	May 14 04:21:38 PM PDT 24	7831490836 ps
T745	/workspace/coverage/default/98.chip_sw_all_escalation_resets.2635414067			May 14 04:00:27 PM PDT 24	May 14 04:08:58 PM PDT 24	4781964408 ps
T913	/workspace/coverage/default/1.chip_sw_example_rom.483661870			May 14 03:31:03 PM PDT 24	May 14 03:33:28 PM PDT 24	2218929540 ps
T110	/workspace/coverage/default/2.chip_tap_straps_prod.754312061			May 14 03:49:13 PM PDT 24	May 14 04:15:19 PM PDT 24	13923093685 ps
T914	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3880308290			May 14 03:33:39 PM PDT 24	May 14 03:39:21 PM PDT 24	4030865614 ps
T789	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.522018729			May 14 03:55:21 PM PDT 24	May 14 04:03:02 PM PDT 24	3830869560 ps
T76	/workspace/coverage/default/2.chip_sw_alert_test.1948220837			May 14 03:51:36 PM PDT 24	May 14 03:56:42 PM PDT 24	2671501248 ps
T329	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.561634361			May 14 03:58:03 PM PDT 24	May 14 04:06:38 PM PDT 24	3918328900 ps
T333	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.4264596060			May 14 03:32:10 PM PDT 24	May 14 03:36:15 PM PDT 24	2165635856 ps
T334	/workspace/coverage/default/0.chip_sw_example_rom.1841094041			May 14 03:31:39 PM PDT 24	May 14 03:34:01 PM PDT 24	2944827460 ps
T322	/workspace/coverage/default/61.chip_sw_all_escalation_resets.2026835638			May 14 03:58:22 PM PDT 24	May 14 04:09:16 PM PDT 24	6113992424 ps
T117	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1595744592			May 14 03:58:20 PM PDT 24	May 14 04:06:20 PM PDT 24	3975505180 ps
T118	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1712754919			May 14 03:49:12 PM PDT 24	May 14 04:11:22 PM PDT 24	7621058944 ps
T119	/workspace/coverage/default/2.chip_sw_example_manufacturer.3461759535			May 14 03:43:26 PM PDT 24	May 14 03:46:57 PM PDT 24	2290633920 ps
T120	/workspace/coverage/default/0.chip_sw_hmac_enc.3405034085			May 14 03:33:40 PM PDT 24	May 14 03:38:54 PM PDT 24	2649141760 ps
T121	/workspace/coverage/default/1.chip_sival_flash_info_access.551519436			May 14 03:34:53 PM PDT 24	May 14 03:40:20 PM PDT 24	2870573760 ps
T122	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1673582268			May 14 03:54:54 PM PDT 24	May 14 04:02:03 PM PDT 24	4089780926 ps
T123	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1535980377			May 14 03:43:10 PM PDT 24	May 14 04:17:37 PM PDT 24	8459638417 ps
T124	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3906969635			May 14 03:56:02 PM PDT 24	May 14 04:38:15 PM PDT 24	13269615384 ps
T125	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3929077000			May 14 03:35:42 PM PDT 24	May 14 03:45:21 PM PDT 24	5088864576 ps
T126	/workspace/coverage/default/2.chip_sw_edn_sw_mode.1668685225			May 14 03:47:32 PM PDT 24	May 14 04:07:11 PM PDT 24	6490590218 ps
T165	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3154505994			May 14 03:38:50 PM PDT 24	May 14 03:50:10 PM PDT 24	4780362978 ps
T798	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.326582438			May 14 03:58:31 PM PDT 24	May 14 04:04:46 PM PDT 24	3703669690 ps
T330	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2272674149			May 14 03:58:24 PM PDT 24	May 14 04:04:41 PM PDT 24	3775479094 ps
T825	/workspace/coverage/default/30.chip_sw_all_escalation_resets.1823706908			May 14 03:55:15 PM PDT 24	May 14 04:05:29 PM PDT 24	4841242320 ps
T915	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2277504113			May 14 03:38:39 PM PDT 24	May 14 03:44:00 PM PDT 24	3641694427 ps
T916	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2974976375			May 14 03:41:22 PM PDT 24	May 14 03:59:37 PM PDT 24	6245793320 ps
T180	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2523356317			May 14 03:49:45 PM PDT 24	May 14 04:03:27 PM PDT 24	6524528382 ps
T103	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3361176929			May 14 03:31:49 PM PDT 24	May 14 03:39:46 PM PDT 24	3313704504 ps
T917	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2925303530			May 14 03:49:35 PM PDT 24	May 14 03:57:42 PM PDT 24	3285779692 ps
T361	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.370871721			May 14 03:34:27 PM PDT 24	May 14 03:53:18 PM PDT 24	5075250744 ps
T753	/workspace/coverage/default/85.chip_sw_all_escalation_resets.1480827624			May 14 04:03:58 PM PDT 24	May 14 04:18:07 PM PDT 24	5466409600 ps
T739	/workspace/coverage/default/18.chip_sw_all_escalation_resets.3831068290			May 14 03:55:06 PM PDT 24	May 14 04:06:19 PM PDT 24	6116523040 ps
T814	/workspace/coverage/default/67.chip_sw_all_escalation_resets.461873010			May 14 04:00:24 PM PDT 24	May 14 04:09:11 PM PDT 24	4653508158 ps
T160	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.678352370			May 14 03:45:13 PM PDT 24	May 14 03:55:07 PM PDT 24	8246312920 ps
T12	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3534839642			May 14 03:45:31 PM PDT 24	May 14 03:53:36 PM PDT 24	4356604892 ps
T918	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.3271275151			May 14 03:44:43 PM PDT 24	May 14 04:01:21 PM PDT 24	5432263000 ps
T85	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.513899474			May 14 03:35:55 PM PDT 24	May 14 03:53:31 PM PDT 24	9418081018 ps
T228	/workspace/coverage/default/84.chip_sw_all_escalation_resets.2846549826			May 14 04:03:16 PM PDT 24	May 14 04:11:26 PM PDT 24	5563325892 ps
T86	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2581424974			May 14 03:47:00 PM PDT 24	May 14 07:24:23 PM PDT 24	255818308424 ps
T261	/workspace/coverage/default/68.chip_sw_all_escalation_resets.2748853380			May 14 03:59:12 PM PDT 24	May 14 04:08:36 PM PDT 24	5158826096 ps
T262	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1565590019			May 14 03:30:30 PM PDT 24	May 14 03:34:43 PM PDT 24	3013437512 ps
T151	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.4245375373			May 14 03:49:29 PM PDT 24	May 14 03:53:57 PM PDT 24	3176227998 ps
T263	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1999942638			May 14 03:39:55 PM PDT 24	May 14 03:44:08 PM PDT 24	3013937470 ps
T264	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.1979343094			May 14 03:39:15 PM PDT 24	May 14 03:42:16 PM PDT 24	2037502740 ps
T265	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3985958963			May 14 03:39:35 PM PDT 24	May 14 03:58:55 PM PDT 24	5079280400 ps
T266	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2215669376			May 14 03:32:32 PM PDT 24	May 14 03:40:20 PM PDT 24	5903864292 ps
T267	/workspace/coverage/default/1.chip_sw_kmac_entropy.883950787			May 14 03:36:15 PM PDT 24	May 14 03:40:08 PM PDT 24	2692753640 ps
T823	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2735908542			May 14 03:59:18 PM PDT 24	May 14 04:06:33 PM PDT 24	4315530780 ps
T919	/workspace/coverage/default/1.rom_keymgr_functest.3371808324			May 14 03:42:02 PM PDT 24	May 14 03:51:06 PM PDT 24	5110732562 ps
T306	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3020583842			May 14 03:55:09 PM PDT 24	May 14 04:05:34 PM PDT 24	4588731160 ps
T920	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2655228487			May 14 03:34:15 PM PDT 24	May 14 03:47:06 PM PDT 24	4069062260 ps
T921	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2919061279			May 14 03:47:02 PM PDT 24	May 14 03:51:54 PM PDT 24	2557313730 ps
T680	/workspace/coverage/default/1.chip_sw_aes_masking_off.1130091170			May 14 03:35:44 PM PDT 24	May 14 03:40:09 PM PDT 24	2402651186 ps
T45	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1024224579			May 14 03:37:18 PM PDT 24	May 14 03:46:17 PM PDT 24	6069706740 ps
T799	/workspace/coverage/default/5.chip_sw_all_escalation_resets.1173339455			May 14 03:53:34 PM PDT 24	May 14 04:03:20 PM PDT 24	4611359948 ps
T922	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1900792497			May 14 03:35:16 PM PDT 24	May 14 03:40:06 PM PDT 24	3014729231 ps
T114	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2523285125			May 14 03:35:24 PM PDT 24	May 14 06:48:49 PM PDT 24	256128953590 ps
T752	/workspace/coverage/default/36.chip_sw_all_escalation_resets.6510157			May 14 03:58:58 PM PDT 24	May 14 04:09:34 PM PDT 24	5924626496 ps
T923	/workspace/coverage/default/16.chip_sw_all_escalation_resets.999030600			May 14 03:56:30 PM PDT 24	May 14 04:04:50 PM PDT 24	5386381652 ps
T286	/workspace/coverage/default/0.chip_plic_all_irqs_20.76316538			May 14 03:34:35 PM PDT 24	May 14 03:49:23 PM PDT 24	5289417570 ps
T305	/workspace/coverage/default/8.chip_sw_all_escalation_resets.272963413			May 14 03:53:05 PM PDT 24	May 14 04:01:40 PM PDT 24	5237531208 ps
T307	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1791851257			May 14 03:54:07 PM PDT 24	May 14 04:06:11 PM PDT 24	4625678208 ps
T924	/workspace/coverage/default/2.chip_sw_example_concurrency.159938560			May 14 03:42:46 PM PDT 24	May 14 03:46:32 PM PDT 24	3383451860 ps
T177	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3028064472			May 14 03:48:46 PM PDT 24	May 14 03:56:12 PM PDT 24	5235233120 ps
T816	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1454811793			May 14 03:54:56 PM PDT 24	May 14 04:00:48 PM PDT 24	3465544976 ps
T366	/workspace/coverage/default/2.chip_sw_kmac_app_rom.1250560690			May 14 03:47:55 PM PDT 24	May 14 03:52:33 PM PDT 24	2126210088 ps
T692	/workspace/coverage/default/1.chip_tap_straps_prod.4079114132			May 14 03:38:51 PM PDT 24	May 14 03:41:45 PM PDT 24	3292485075 ps