Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117720 |
1 |
|
|
T63 |
3 |
|
T64 |
74 |
|
T70 |
5 |
| auto[1] |
60356 |
1 |
|
|
T63 |
2 |
|
T64 |
11 |
|
T79 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
45348 |
1 |
|
|
T63 |
3 |
|
T64 |
30 |
|
T70 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
125227 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
52849 |
1 |
|
|
T64 |
26 |
|
T70 |
1 |
|
T113 |
15 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14095 |
1 |
|
|
T64 |
6 |
|
T113 |
3 |
|
T399 |
7 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119788 |
1 |
|
|
T63 |
3 |
|
T64 |
70 |
|
T70 |
2 |
| auto[1] |
62782 |
1 |
|
|
T63 |
1 |
|
T64 |
16 |
|
T70 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
45874 |
1 |
|
|
T63 |
3 |
|
T64 |
26 |
|
T70 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
128599 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
53971 |
1 |
|
|
T64 |
21 |
|
T70 |
2 |
|
T79 |
4 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14175 |
1 |
|
|
T64 |
8 |
|
T70 |
1 |
|
T79 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
114411 |
1 |
|
|
T63 |
1 |
|
T64 |
68 |
|
T65 |
160 |
| auto[1] |
64814 |
1 |
|
|
T63 |
1 |
|
T64 |
20 |
|
T65 |
350 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
43981 |
1 |
|
|
T63 |
1 |
|
T64 |
37 |
|
T65 |
147 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
126553 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
52672 |
1 |
|
|
T63 |
1 |
|
T64 |
25 |
|
T65 |
170 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
13719 |
1 |
|
|
T63 |
1 |
|
T64 |
9 |
|
T65 |
54 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119073 |
1 |
|
|
T63 |
5 |
|
T64 |
47 |
|
T70 |
5 |
| auto[1] |
60177 |
1 |
|
|
T63 |
4 |
|
T64 |
73 |
|
T70 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
45010 |
1 |
|
|
T63 |
5 |
|
T64 |
38 |
|
T70 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
126435 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
52815 |
1 |
|
|
T63 |
4 |
|
T64 |
34 |
|
T70 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
13947 |
1 |
|
|
T63 |
3 |
|
T64 |
9 |
|
T70 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
114314 |
1 |
|
|
T63 |
1 |
|
T64 |
82 |
|
T70 |
6 |
| auto[1] |
66593 |
1 |
|
|
T63 |
1 |
|
T64 |
3 |
|
T79 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
45230 |
1 |
|
|
T63 |
1 |
|
T64 |
25 |
|
T70 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
127582 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
53325 |
1 |
|
|
T63 |
1 |
|
T64 |
25 |
|
T70 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14104 |
1 |
|
|
T63 |
1 |
|
T64 |
7 |
|
T79 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
118085 |
1 |
|
|
T63 |
5 |
|
T64 |
69 |
|
T70 |
5 |
| auto[1] |
65635 |
1 |
|
|
T64 |
27 |
|
T70 |
1 |
|
T79 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
45852 |
1 |
|
|
T63 |
2 |
|
T64 |
36 |
|
T70 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
129581 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
54139 |
1 |
|
|
T63 |
2 |
|
T64 |
31 |
|
T79 |
5 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14040 |
1 |
|
|
T63 |
1 |
|
T64 |
12 |
|
T113 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122792 |
1 |
|
|
T63 |
3 |
|
T64 |
35 |
|
T65 |
396 |
| auto[1] |
63495 |
1 |
|
|
T63 |
1 |
|
T64 |
60 |
|
T65 |
40 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
46981 |
1 |
|
|
T64 |
37 |
|
T65 |
145 |
|
T70 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
131322 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
54965 |
1 |
|
|
T63 |
2 |
|
T64 |
26 |
|
T65 |
148 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14605 |
1 |
|
|
T64 |
10 |
|
T65 |
51 |
|
T79 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124049 |
1 |
|
|
T63 |
2 |
|
T64 |
49 |
|
T70 |
1 |
| auto[1] |
62260 |
1 |
|
|
T64 |
27 |
|
T70 |
5 |
|
T79 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
46693 |
1 |
|
|
T63 |
1 |
|
T64 |
22 |
|
T70 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
131053 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
55256 |
1 |
|
|
T64 |
17 |
|
T79 |
2 |
|
T113 |
12 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14596 |
1 |
|
|
T64 |
6 |
|
T79 |
1 |
|
T113 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127528 |
1 |
|
|
T63 |
3 |
|
T64 |
36 |
|
T70 |
7 |
| auto[1] |
69138 |
1 |
|
|
T64 |
59 |
|
T70 |
7 |
|
T79 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
48680 |
1 |
|
|
T63 |
2 |
|
T64 |
33 |
|
T70 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
139004 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57662 |
1 |
|
|
T63 |
2 |
|
T64 |
30 |
|
T70 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15051 |
1 |
|
|
T63 |
2 |
|
T64 |
11 |
|
T79 |
3 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131136 |
1 |
|
|
T63 |
6 |
|
T64 |
32 |
|
T70 |
2 |
| auto[1] |
66991 |
1 |
|
|
T64 |
58 |
|
T70 |
2 |
|
T79 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49387 |
1 |
|
|
T63 |
2 |
|
T64 |
34 |
|
T79 |
7 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
139750 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58377 |
1 |
|
|
T63 |
1 |
|
T64 |
39 |
|
T70 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15282 |
1 |
|
|
T63 |
1 |
|
T64 |
14 |
|
T79 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122805 |
1 |
|
|
T63 |
5 |
|
T64 |
80 |
|
T70 |
5 |
| auto[1] |
70576 |
1 |
|
|
T63 |
1 |
|
T64 |
43 |
|
T70 |
6 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
48011 |
1 |
|
|
T63 |
1 |
|
T64 |
48 |
|
T70 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
136158 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57223 |
1 |
|
|
T63 |
2 |
|
T64 |
44 |
|
T70 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15043 |
1 |
|
|
T64 |
17 |
|
T399 |
7 |
|
T482 |
3 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
964952 |
1 |
|
|
T63 |
30 |
|
T64 |
596 |
|
T65 |
257 |
| auto[1] |
481175 |
1 |
|
|
T64 |
158 |
|
T65 |
317 |
|
T70 |
21 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
364251 |
1 |
|
|
T63 |
10 |
|
T64 |
260 |
|
T65 |
194 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
1007319 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
438808 |
1 |
|
|
T63 |
9 |
|
T64 |
254 |
|
T65 |
194 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
115640 |
1 |
|
|
T63 |
4 |
|
T64 |
84 |
|
T65 |
67 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121676 |
1 |
|
|
T63 |
5 |
|
T64 |
36 |
|
T70 |
3 |
| auto[1] |
65102 |
1 |
|
|
T63 |
2 |
|
T64 |
58 |
|
T70 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
46208 |
1 |
|
|
T63 |
2 |
|
T64 |
30 |
|
T70 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
131520 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
55258 |
1 |
|
|
T64 |
36 |
|
T70 |
2 |
|
T79 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14397 |
1 |
|
|
T64 |
13 |
|
T70 |
2 |
|
T79 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127252 |
1 |
|
|
T63 |
3 |
|
T64 |
71 |
|
T65 |
453 |
| auto[1] |
62784 |
1 |
|
|
T64 |
33 |
|
T65 |
92 |
|
T79 |
3 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
47323 |
1 |
|
|
T63 |
1 |
|
T64 |
30 |
|
T65 |
198 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
133756 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
56280 |
1 |
|
|
T63 |
1 |
|
T64 |
26 |
|
T65 |
180 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14823 |
1 |
|
|
T64 |
11 |
|
T65 |
62 |
|
T113 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120478 |
1 |
|
|
T63 |
4 |
|
T64 |
59 |
|
T70 |
2 |
| auto[1] |
65665 |
1 |
|
|
T63 |
1 |
|
T64 |
34 |
|
T70 |
3 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
47858 |
1 |
|
|
T63 |
1 |
|
T64 |
29 |
|
T70 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
129370 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
56773 |
1 |
|
|
T63 |
1 |
|
T64 |
33 |
|
T70 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15132 |
1 |
|
|
T64 |
5 |
|
T79 |
26 |
|
T113 |
3 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120253 |
1 |
|
|
T63 |
5 |
|
T64 |
73 |
|
T65 |
331 |
| auto[1] |
65450 |
1 |
|
|
T64 |
25 |
|
T65 |
197 |
|
T70 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
46342 |
1 |
|
|
T63 |
3 |
|
T64 |
33 |
|
T65 |
183 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
131058 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
54645 |
1 |
|
|
T63 |
2 |
|
T64 |
34 |
|
T65 |
173 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14362 |
1 |
|
|
T63 |
2 |
|
T64 |
9 |
|
T65 |
65 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124747 |
1 |
|
|
T63 |
3 |
|
T64 |
43 |
|
T70 |
4 |
| auto[1] |
59315 |
1 |
|
|
T64 |
47 |
|
T70 |
5 |
|
T79 |
5 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
44817 |
1 |
|
|
T64 |
29 |
|
T70 |
3 |
|
T79 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
129733 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
54329 |
1 |
|
|
T64 |
25 |
|
T70 |
3 |
|
T79 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
13790 |
1 |
|
|
T64 |
9 |
|
T70 |
2 |
|
T79 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121799 |
1 |
|
|
T63 |
7 |
|
T64 |
83 |
|
T70 |
3 |
| auto[1] |
64821 |
1 |
|
|
T64 |
14 |
|
T70 |
1 |
|
T79 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
48117 |
1 |
|
|
T63 |
2 |
|
T64 |
35 |
|
T70 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
130663 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
55957 |
1 |
|
|
T63 |
3 |
|
T64 |
28 |
|
T70 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15165 |
1 |
|
|
T63 |
1 |
|
T64 |
10 |
|
T70 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129300 |
1 |
|
|
T63 |
3 |
|
T64 |
109 |
|
T79 |
6 |
| auto[1] |
67708 |
1 |
|
|
T64 |
3 |
|
T70 |
6 |
|
T79 |
5 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49173 |
1 |
|
|
T63 |
1 |
|
T64 |
30 |
|
T79 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
139114 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57894 |
1 |
|
|
T63 |
1 |
|
T64 |
35 |
|
T70 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15133 |
1 |
|
|
T63 |
1 |
|
T64 |
9 |
|
T113 |
5 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116915 |
1 |
|
|
T63 |
2 |
|
T64 |
92 |
|
T70 |
5 |
| auto[1] |
67320 |
1 |
|
|
T63 |
2 |
|
T70 |
2 |
|
T79 |
5 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
45589 |
1 |
|
|
T63 |
1 |
|
T64 |
26 |
|
T70 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
128839 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
55396 |
1 |
|
|
T63 |
3 |
|
T64 |
26 |
|
T70 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14160 |
1 |
|
|
T63 |
1 |
|
T64 |
7 |
|
T79 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116772 |
1 |
|
|
T63 |
2 |
|
T64 |
70 |
|
T70 |
3 |
| auto[1] |
64858 |
1 |
|
|
T63 |
2 |
|
T64 |
45 |
|
T70 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
45823 |
1 |
|
|
T63 |
2 |
|
T64 |
40 |
|
T70 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
128225 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
53405 |
1 |
|
|
T63 |
3 |
|
T64 |
39 |
|
T70 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14049 |
1 |
|
|
T63 |
1 |
|
T64 |
12 |
|
T70 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129831 |
1 |
|
|
T63 |
2 |
|
T64 |
69 |
|
T70 |
1 |
| auto[1] |
67865 |
1 |
|
|
T63 |
1 |
|
T64 |
48 |
|
T70 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49769 |
1 |
|
|
T63 |
1 |
|
T64 |
39 |
|
T70 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137724 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
59972 |
1 |
|
|
T64 |
35 |
|
T79 |
4 |
|
T113 |
14 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15762 |
1 |
|
|
T64 |
16 |
|
T79 |
1 |
|
T113 |
3 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120590 |
1 |
|
|
T63 |
1 |
|
T64 |
62 |
|
T65 |
313 |
| auto[1] |
65832 |
1 |
|
|
T63 |
1 |
|
T64 |
28 |
|
T65 |
178 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
47543 |
1 |
|
|
T64 |
19 |
|
T65 |
157 |
|
T70 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
129672 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
56750 |
1 |
|
|
T63 |
1 |
|
T64 |
32 |
|
T65 |
171 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15151 |
1 |
|
|
T64 |
5 |
|
T65 |
55 |
|
T70 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117315 |
1 |
|
|
T63 |
4 |
|
T64 |
52 |
|
T70 |
3 |
| auto[1] |
64206 |
1 |
|
|
T63 |
3 |
|
T64 |
63 |
|
T70 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
45348 |
1 |
|
|
T63 |
3 |
|
T64 |
32 |
|
T70 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
127878 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
53643 |
1 |
|
|
T63 |
1 |
|
T64 |
41 |
|
T70 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14053 |
1 |
|
|
T63 |
1 |
|
T64 |
11 |
|
T70 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121416 |
1 |
|
|
T63 |
4 |
|
T64 |
49 |
|
T70 |
8 |
| auto[1] |
64433 |
1 |
|
|
T63 |
1 |
|
T64 |
45 |
|
T70 |
3 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
47844 |
1 |
|
|
T64 |
22 |
|
T70 |
4 |
|
T79 |
7 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
130795 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
55054 |
1 |
|
|
T63 |
4 |
|
T64 |
32 |
|
T70 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14663 |
1 |
|
|
T64 |
7 |
|
T70 |
1 |
|
T79 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121083 |
1 |
|
|
T63 |
2 |
|
T64 |
43 |
|
T70 |
3 |
| auto[1] |
63937 |
1 |
|
|
T63 |
5 |
|
T64 |
49 |
|
T70 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
47182 |
1 |
|
|
T63 |
3 |
|
T64 |
37 |
|
T70 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
128503 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
56517 |
1 |
|
|
T64 |
36 |
|
T70 |
2 |
|
T113 |
14 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15076 |
1 |
|
|
T64 |
16 |
|
T70 |
1 |
|
T113 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121006 |
1 |
|
|
T63 |
1 |
|
T64 |
68 |
|
T70 |
5 |
| auto[1] |
66493 |
1 |
|
|
T64 |
23 |
|
T70 |
2 |
|
T79 |
2 |