Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 50 0 50 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 50 0 50 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 50 0 50 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 463 1 T399 2 T746 1 T379 1
all_values[1] 487 1 T79 2 T399 2 T400 1
all_values[2] 440 1 T79 1 T399 2 T400 1
all_values[3] 455 1 T399 6 T400 1 T379 1
all_values[4] 421 1 T399 3 T400 3 T412 3
all_values[5] 449 1 T65 2 T79 1 T399 3
all_values[6] 429 1 T79 2 T399 5 T379 2
all_values[7] 460 1 T399 4 T379 1 T892 1
all_values[8] 456 1 T79 1 T399 4 T412 2
all_values[9] 422 1 T79 1 T399 2 T400 2
all_values[10] 477 1 T79 3 T399 1 T379 1
all_values[11] 413 1 T79 1 T399 6 T379 1
all_values[12] 465 1 T399 2 T379 5 T477 1
all_values[13] 491 1 T79 2 T399 6 T379 2
all_values[14] 469 1 T65 1 T79 3 T399 6
all_values[15] 462 1 T79 5 T399 6 T400 2
all_values[16] 478 1 T79 1 T399 8 T400 1
all_values[17] 467 1 T79 2 T399 7 T400 1
all_values[18] 495 1 T79 3 T399 5 T400 2
all_values[19] 449 1 T79 4 T399 4 T400 3
all_values[20] 423 1 T79 1 T399 2 T379 4
all_values[21] 472 1 T65 1 T79 1 T399 7
all_values[22] 485 1 T79 2 T399 5 T400 1
all_values[23] 437 1 T79 3 T399 7 T400 2
all_values[24] 446 1 T399 4 T477 1 T412 3
all_values[25] 445 1 T79 4 T399 5 T379 1
all_values[26] 487 1 T65 1 T79 2 T399 2
all_values[27] 468 1 T65 1 T79 1 T399 10
all_values[28] 448 1 T79 1 T399 6 T379 2
all_values[29] 449 1 T79 1 T399 5 T379 2
all_values[30] 449 1 T399 12 T400 1 T379 2
all_values[31] 430 1 T79 2 T399 7 T400 1
all_values[32] 472 1 T65 1 T79 1 T399 6
all_values[33] 493 1 T399 1 T379 3 T477 1
all_values[34] 450 1 T79 2 T399 5 T400 1
all_values[35] 494 1 T79 2 T399 5 T400 1
all_values[36] 447 1 T79 2 T399 1 T379 4
all_values[37] 440 1 T399 7 T477 1 T412 1
all_values[38] 428 1 T79 3 T399 4 T379 1
all_values[39] 484 1 T65 1 T79 1 T399 4
all_values[40] 448 1 T79 3 T399 5 T400 1
all_values[41] 429 1 T79 1 T399 4 T400 1
all_values[42] 488 1 T399 2 T379 7 T477 2
all_values[43] 481 1 T65 1 T79 2 T399 3
all_values[44] 460 1 T79 3 T399 6 T400 1
all_values[45] 460 1 T79 2 T399 3 T379 3
all_values[46] 449 1 T79 2 T399 5 T379 2
all_values[47] 463 1 T79 2 T399 6 T400 2
all_values[48] 465 1 T79 4 T399 7 T400 1
all_values[49] 418 1 T79 2 T399 7 T400 1

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