Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3465	1			T79	16		T399	33		T400	3
all_values[1]	3336	1			T79	20		T399	39		T400	8
all_values[2]	3451	1			T79	14		T399	40		T400	12
all_values[3]	3477	1			T79	13		T399	36		T400	7
all_values[4]	3333	1			T79	14		T399	40		T400	7
all_values[5]	3246	1			T79	11		T399	33		T400	8
all_values[6]	3315	1			T79	16		T399	22		T400	4
all_values[7]	3410	1			T79	15		T399	42		T400	10
all_values[8]	3471	1			T79	16		T399	36		T400	9
all_values[9]	3307	1			T79	16		T399	37		T400	7
all_values[10]	3238	1			T79	12		T399	33		T400	10
all_values[11]	3425	1			T79	15		T399	36		T400	4
all_values[12]	3395	1			T79	20		T399	37		T400	5
all_values[13]	3381	1			T79	18		T399	38		T400	7
all_values[14]	3424	1			T79	12		T399	31		T400	4
all_values[15]	3420	1			T79	25		T399	41		T400	5
all_values[16]	3305	1			T79	13		T399	37		T400	5
all_values[17]	3348	1			T79	17		T399	38		T400	4
all_values[18]	3428	1			T79	11		T399	28		T400	6
all_values[19]	3476	1			T79	22		T399	31		T400	8
all_values[20]	3434	1			T79	16		T399	43		T400	5
all_values[21]	3461	1			T79	14		T399	33		T400	6
all_values[22]	3367	1			T79	16		T399	32		T400	1
all_values[23]	3270	1			T79	14		T399	32		T400	7
all_values[24]	3416	1			T79	11		T399	39		T400	6
all_values[25]	3355	1			T79	12		T399	38		T400	7
all_values[26]	3339	1			T79	16		T399	34		T400	10
all_values[27]	3382	1			T79	12		T399	35		T400	3
all_values[28]	3438	1			T79	22		T399	34		T400	7
all_values[29]	3469	1			T79	10		T399	34		T400	4
all_values[30]	3395	1			T79	19		T399	28		T400	6
all_values[31]	3304	1			T79	10		T399	34		T400	6
all_values[32]	3428	1			T79	11		T399	35		T400	2
all_values[33]	3287	1			T79	5		T399	40		T400	6
all_values[34]	3393	1			T79	12		T399	44		T400	8
all_values[35]	3273	1			T79	16		T399	33		T400	10
all_values[36]	3379	1			T79	14		T399	35		T400	7
all_values[37]	3351	1			T79	13		T399	33		T400	7
all_values[38]	3447	1			T79	18		T399	36		T400	7
all_values[39]	3358	1			T79	18		T399	44		T400	6
all_values[40]	3350	1			T79	11		T399	35		T400	3
all_values[41]	3371	1			T79	17		T399	41		T400	10
all_values[42]	3453	1			T79	8		T399	29		T400	5
all_values[43]	3473	1			T79	24		T399	27		T400	10
all_values[44]	3365	1			T79	19		T399	32		T400	9
all_values[45]	3435	1			T79	10		T399	35		T400	7
all_values[46]	3375	1			T79	7		T399	39		T400	5
all_values[47]	3474	1			T79	14		T399	37		T400	4
all_values[48]	3432	1			T79	18		T399	34		T400	6
all_values[49]	3422	1			T79	27		T399	39		T400	5
all_values[50]	3568	1			T79	23		T399	42		T400	4
all_values[51]	3259	1			T79	21		T399	28		T400	8
all_values[52]	3266	1			T79	12		T399	31		T400	3
all_values[53]	3260	1			T79	16		T399	25		T400	2
all_values[54]	3384	1			T79	21		T399	29		T400	4
all_values[55]	3333	1			T79	15		T399	34		T400	6
all_values[56]	3340	1			T79	8		T399	39		T400	8
all_values[57]	3312	1			T79	15		T399	40		T400	9
all_values[58]	3369	1			T79	10		T399	34		T400	5
all_values[59]	3379	1			T79	20		T399	43		T400	5
all_values[60]	3372	1			T79	16		T399	41		T400	3
all_values[61]	3386	1			T79	17		T399	42		T400	5
all_values[62]	3347	1			T79	19		T399	36		T400	8
all_values[63]	3363	1			T79	20		T399	28		T400	7