CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 373123 | 1 | T64 | 188 | T242 | 476 | T240 | 1 | ||||
rising | 373205 | 1 | T64 | 187 | T242 | 476 | T240 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1051189 | 1 | T64 | 700 | T242 | 1420 | T240 | 2 | ||||
auto[1] | 9525986 | 1 | T62 | 3826 | T63 | 1004 | T64 | 860 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 329421 | 1 | T62 | 2 | T64 | 168 | T242 | 425 | ||||
rising | 329495 | 1 | T62 | 2 | T64 | 169 | T242 | 425 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1171847 | 1 | T62 | 4 | T64 | 692 | T242 | 1578 | ||||
auto[1] | 10271216 | 1 | T62 | 3986 | T63 | 738 | T64 | 738 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 659560 | 1 | T62 | 2 | T64 | 358 | T242 | 1094 | ||||
rising | 659631 | 1 | T62 | 2 | T64 | 358 | T242 | 1094 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1065704 | 1 | T62 | 2 | T64 | 724 | T242 | 1442 | ||||
auto[1] | 9612524 | 1 | T62 | 3298 | T63 | 814 | T64 | 840 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7025 | 1 | T242 | 1 | T241 | 1 | T483 | 2 | ||||
rising | 7072 | 1 | T242 | 1 | T241 | 1 | T483 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 168269 | 1 | T62 | 69 | T63 | 20 | T64 | 14 | ||||
auto[1] | 13773 | 1 | T242 | 1 | T241 | 1 | T483 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5420 | 1 | T241 | 1 | T483 | 6 | T490 | 2 | ||||
rising | 5453 | 1 | T241 | 1 | T483 | 6 | T490 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 189571 | 1 | T62 | 59 | T63 | 18 | T64 | 11 | ||||
auto[1] | 8332 | 1 | T241 | 1 | T483 | 6 | T490 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 3208 | 1 | T493 | 1 | T488 | 1 | T486 | 1 | ||||
rising | 3231 | 1 | T493 | 1 | T488 | 1 | T486 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 184048 | 1 | T62 | 70 | T63 | 16 | T64 | 15 | ||||
auto[1] | 3493 | 1 | T493 | 1 | T488 | 1 | T486 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7921 | 1 | T497 | 48 | T483 | 1 | T396 | 1 | ||||
rising | 7979 | 1 | T497 | 49 | T483 | 1 | T396 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 165310 | 1 | T62 | 65 | T63 | 17 | T64 | 21 | ||||
auto[1] | 24666 | 1 | T497 | 370 | T483 | 1 | T396 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 3543 | 1 | T63 | 1 | T64 | 1 | T242 | 1 | ||||
rising | 3569 | 1 | T63 | 1 | T64 | 1 | T242 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 174839 | 1 | T62 | 67 | T63 | 16 | T64 | 19 | ||||
auto[1] | 3983 | 1 | T63 | 1 | T64 | 1 | T242 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7253 | 1 | T240 | 6 | T241 | 1 | T485 | 1 | ||||
rising | 7295 | 1 | T240 | 6 | T241 | 1 | T485 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 173478 | 1 | T62 | 73 | T63 | 12 | T64 | 18 | ||||
auto[1] | 14716 | 1 | T240 | 6 | T241 | 1 | T485 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5967 | 1 | T63 | 2 | T241 | 1 | T486 | 2 | ||||
rising | 6003 | 1 | T63 | 3 | T241 | 1 | T486 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 185947 | 1 | T62 | 78 | T63 | 18 | T64 | 17 | ||||
auto[1] | 12342 | 1 | T63 | 3 | T241 | 1 | T486 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4727 | 1 | T241 | 1 | T485 | 2 | T483 | 1 | ||||
rising | 4764 | 1 | T241 | 1 | T485 | 2 | T483 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 179665 | 1 | T62 | 65 | T63 | 15 | T64 | 15 | ||||
auto[1] | 9952 | 1 | T241 | 1 | T485 | 2 | T483 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5530 | 1 | T485 | 2 | T486 | 1 | T479 | 46 | ||||
rising | 5564 | 1 | T485 | 2 | T486 | 1 | T479 | 46 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 182500 | 1 | T62 | 75 | T63 | 18 | T64 | 12 | ||||
auto[1] | 12404 | 1 | T485 | 4 | T486 | 1 | T479 | 60 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6105 | 1 | T483 | 1 | T490 | 1 | T388 | 2 | ||||
rising | 6145 | 1 | T483 | 1 | T490 | 1 | T388 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 190616 | 1 | T62 | 66 | T63 | 20 | T64 | 14 | ||||
auto[1] | 9641 | 1 | T483 | 1 | T490 | 1 | T388 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4487 | 1 | T240 | 29 | T493 | 1 | T483 | 2 | ||||
rising | 4520 | 1 | T240 | 29 | T493 | 1 | T483 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 184331 | 1 | T62 | 66 | T63 | 8 | T64 | 22 | ||||
auto[1] | 5746 | 1 | T240 | 32 | T493 | 1 | T483 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 15413 | 1 | T63 | 4 | T240 | 46 | T241 | 4 | ||||
rising | 15434 | 1 | T63 | 4 | T240 | 46 | T241 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1470850 | 1 | T62 | 586 | T63 | 109 | T64 | 115 | ||||
auto[1] | 16094 | 1 | T63 | 4 | T240 | 47 | T241 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5526 | 1 | T63 | 2 | T485 | 1 | T483 | 1 | ||||
rising | 5560 | 1 | T63 | 2 | T485 | 1 | T483 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 179957 | 1 | T62 | 66 | T63 | 13 | T64 | 17 | ||||
auto[1] | 12252 | 1 | T63 | 2 | T485 | 1 | T483 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6050 | 1 | T62 | 1 | T63 | 1 | T240 | 96 | ||||
rising | 6096 | 1 | T62 | 1 | T63 | 1 | T240 | 96 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 166609 | 1 | T62 | 65 | T63 | 17 | T64 | 27 | ||||
auto[1] | 17406 | 1 | T62 | 1 | T63 | 1 | T240 | 300 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2269 | 1 | T63 | 4 | T240 | 21 | T483 | 2 | ||||
rising | 2291 | 1 | T63 | 4 | T240 | 21 | T483 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 183474 | 1 | T62 | 59 | T63 | 21 | T64 | 22 | ||||
auto[1] | 2428 | 1 | T63 | 4 | T240 | 22 | T483 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6468 | 1 | T62 | 1 | T241 | 1 | T483 | 1 | ||||
rising | 6510 | 1 | T62 | 1 | T241 | 1 | T483 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 164554 | 1 | T62 | 67 | T63 | 17 | T64 | 17 | ||||
auto[1] | 12368 | 1 | T62 | 1 | T241 | 1 | T483 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 8618 | 1 | T497 | 99 | T490 | 1 | T388 | 2 | ||||
rising | 8662 | 1 | T497 | 99 | T490 | 1 | T388 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 180223 | 1 | T62 | 65 | T63 | 27 | T64 | 9 | ||||
auto[1] | 17058 | 1 | T497 | 326 | T490 | 1 | T388 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 8251 | 1 | T62 | 1 | T63 | 1 | T241 | 1 | ||||
rising | 8300 | 1 | T62 | 1 | T63 | 1 | T241 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 173828 | 1 | T62 | 66 | T63 | 19 | T64 | 23 | ||||
auto[1] | 17122 | 1 | T62 | 1 | T63 | 2 | T241 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5142 | 1 | T63 | 2 | T241 | 2 | T497 | 115 | ||||
rising | 5179 | 1 | T63 | 2 | T241 | 2 | T497 | 116 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 196197 | 1 | T62 | 81 | T63 | 17 | T64 | 15 | ||||
auto[1] | 7783 | 1 | T63 | 2 | T241 | 2 | T497 | 206 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2200 | 1 | T240 | 19 | T486 | 1 | T483 | 5 | ||||
rising | 2217 | 1 | T240 | 19 | T486 | 1 | T483 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 182277 | 1 | T62 | 67 | T63 | 13 | T64 | 12 | ||||
auto[1] | 2361 | 1 | T240 | 20 | T486 | 1 | T483 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6736 | 1 | T242 | 1 | T240 | 29 | T241 | 1 | ||||
rising | 6770 | 1 | T242 | 1 | T240 | 29 | T241 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 180114 | 1 | T62 | 92 | T63 | 18 | T64 | 14 | ||||
auto[1] | 9822 | 1 | T242 | 1 | T240 | 30 | T241 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 40917 | 1 | T499 | 1615 | T500 | 802 | T501 | 2424 | ||||
rising | 40924 | 1 | T499 | 1616 | T500 | 803 | T501 | 2424 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 89199 | 1 | T499 | 3442 | T500 | 1883 | T501 | 5212 | ||||
auto[1] | 79414 | 1 | T499 | 3221 | T500 | 1556 | T501 | 4637 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 23513 | 1 | T499 | 910 | T500 | 518 | T501 | 1388 | ||||
rising | 23510 | 1 | T499 | 910 | T500 | 519 | T501 | 1387 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 139313 | 1 | T499 | 5535 | T500 | 2764 | T501 | 8154 | ||||
auto[1] | 29300 | 1 | T499 | 1128 | T500 | 675 | T501 | 1695 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 23513 | 1 | T499 | 910 | T500 | 518 | T501 | 1388 | ||||
rising | 23510 | 1 | T499 | 910 | T500 | 519 | T501 | 1387 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 139313 | 1 | T499 | 5535 | T500 | 2764 | T501 | 8154 | ||||
auto[1] | 29300 | 1 | T499 | 1128 | T500 | 675 | T501 | 1695 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4105 | 1 | T499 | 100 | T500 | 157 | T501 | 223 | ||||
rising | 4096 | 1 | T499 | 100 | T500 | 157 | T501 | 222 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 162578 | 1 | T499 | 6506 | T500 | 3194 | T501 | 9513 | ||||
auto[1] | 6035 | 1 | T499 | 157 | T500 | 245 | T501 | 336 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 101880 | 1 | T499 | 2 | T500 | 3 | T177 | 476 | ||||
rising | 101897 | 1 | T499 | 2 | T500 | 3 | T177 | 476 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 23351066 | 1 | T1 | 43663 | T2 | 69218 | T3 | 144059 | ||||
auto[1] | 576870 | 1 | T499 | 2 | T500 | 3 | T177 | 627 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 41335 | 1 | T499 | 1629 | T500 | 835 | T501 | 2428 | ||||
rising | 41343 | 1 | T499 | 1628 | T500 | 834 | T501 | 2429 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 88913 | 1 | T499 | 3561 | T500 | 1927 | T501 | 5244 | ||||
auto[1] | 79700 | 1 | T499 | 3102 | T500 | 1512 | T501 | 4605 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 35494 | 1 | T499 | 1423 | T500 | 746 | T501 | 2118 | ||||
rising | 35490 | 1 | T499 | 1424 | T500 | 747 | T501 | 2118 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 117977 | 1 | T499 | 4625 | T500 | 2391 | T501 | 6829 | ||||
auto[1] | 50636 | 1 | T499 | 2038 | T500 | 1048 | T501 | 3020 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2104 | 1 | T63 | 1 | T240 | 11 | T486 | 1 | ||||
rising | 2130 | 1 | T63 | 1 | T240 | 11 | T486 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 192992 | 1 | T62 | 87 | T63 | 22 | T64 | 20 | ||||
auto[1] | 2232 | 1 | T63 | 1 | T240 | 13 | T486 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2956 | 1 | T192 | 1 | T240 | 36 | T483 | 2 | ||||
rising | 2980 | 1 | T192 | 1 | T240 | 36 | T483 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 190432 | 1 | T62 | 72 | T63 | 19 | T64 | 16 | ||||
auto[1] | 3136 | 1 | T192 | 1 | T240 | 37 | T483 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7334 | 1 | T63 | 1 | T241 | 1 | T479 | 51 | ||||
rising | 7393 | 1 | T63 | 1 | T241 | 1 | T479 | 51 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 168199 | 1 | T62 | 65 | T63 | 23 | T64 | 16 | ||||
auto[1] | 31006 | 1 | T63 | 1 | T241 | 1 | T479 | 61 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6447 | 1 | T63 | 1 | T483 | 2 | T396 | 1 | ||||
rising | 6484 | 1 | T63 | 2 | T483 | 2 | T396 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 166520 | 1 | T62 | 67 | T63 | 16 | T64 | 19 | ||||
auto[1] | 16991 | 1 | T63 | 2 | T483 | 2 | T396 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2848 | 1 | T242 | 1 | T240 | 10 | T486 | 1 | ||||
rising | 2866 | 1 | T242 | 1 | T240 | 10 | T486 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 182031 | 1 | T62 | 72 | T63 | 17 | T64 | 16 | ||||
auto[1] | 3021 | 1 | T242 | 1 | T240 | 10 | T486 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6922 | 1 | T62 | 1 | T240 | 34 | T483 | 2 | ||||
rising | 6960 | 1 | T62 | 1 | T240 | 34 | T483 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 170289 | 1 | T62 | 63 | T63 | 11 | T64 | 16 | ||||
auto[1] | 14421 | 1 | T62 | 1 | T240 | 34 | T483 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7987 | 1 | T63 | 2 | T493 | 1 | T483 | 3 | ||||
rising | 8017 | 1 | T63 | 2 | T493 | 1 | T483 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 169695 | 1 | T62 | 91 | T63 | 16 | T64 | 10 | ||||
auto[1] | 16506 | 1 | T63 | 2 | T493 | 1 | T483 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5820 | 1 | T63 | 1 | T241 | 2 | T488 | 2 | ||||
rising | 5866 | 1 | T63 | 1 | T241 | 2 | T488 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 184712 | 1 | T62 | 85 | T63 | 23 | T64 | 14 | ||||
auto[1] | 12329 | 1 | T63 | 1 | T241 | 2 | T488 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 21549 | 1 | T62 | 7 | T63 | 5 | T64 | 2 | ||||
rising | 21581 | 1 | T62 | 7 | T63 | 5 | T64 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1439510 | 1 | T62 | 562 | T63 | 127 | T64 | 126 | ||||
auto[1] | 22525 | 1 | T62 | 9 | T63 | 5 | T64 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 8831 | 1 | T63 | 1 | T486 | 1 | T479 | 7 | ||||
rising | 8880 | 1 | T63 | 1 | T486 | 1 | T479 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 181737 | 1 | T62 | 82 | T63 | 18 | T64 | 17 | ||||
auto[1] | 17948 | 1 | T63 | 1 | T486 | 1 | T479 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5184 | 1 | T63 | 1 | T241 | 2 | T486 | 1 | ||||
rising | 5215 | 1 | T63 | 1 | T241 | 2 | T486 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 180951 | 1 | T62 | 82 | T63 | 15 | T64 | 9 | ||||
auto[1] | 8021 | 1 | T63 | 1 | T241 | 3 | T486 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 193466 | 1 | T62 | 166 | T242 | 342 | T396 | 668 | ||||
rising | 193446 | 1 | T62 | 166 | T242 | 342 | T396 | 668 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1740190 | 1 | T62 | 1626 | T242 | 2867 | T396 | 6425 | ||||
auto[1] | 217641 | 1 | T62 | 197 | T242 | 382 | T396 | 756 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 480288 | 1 | T62 | 432 | T242 | 802 | T396 | 1763 | ||||
rising | 480303 | 1 | T62 | 432 | T242 | 802 | T396 | 1762 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 868372 | 1 | T62 | 777 | T242 | 1466 | T396 | 3193 | ||||
auto[1] | 1089459 | 1 | T62 | 1046 | T242 | 1783 | T396 | 3988 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 480288 | 1 | T62 | 432 | T242 | 802 | T396 | 1763 | ||||
rising | 480303 | 1 | T62 | 432 | T242 | 802 | T396 | 1762 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 868372 | 1 | T62 | 777 | T242 | 1466 | T396 | 3193 | ||||
auto[1] | 1089459 | 1 | T62 | 1046 | T242 | 1783 | T396 | 3988 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |