Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.67	95.60	94.48	91.84		95.40	97.20	99.53

Total tests in report: 2735

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.64	39.64	45.97	45.97	44.98	44.98	25.45	25.45			58.84	58.84	62.41	62.41	0.19	0.19	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1669726097
49.10	9.46	53.87	7.90	54.14	9.16	29.02	3.57			66.98	8.14	90.19	27.78	0.39	0.20	/workspace/coverage/default/1.chip_jtag_csr_rw.2929812798
54.16	5.06	62.48	8.61	57.94	3.80	31.39	2.37			67.56	0.58	90.19	0.00	15.42	15.03	/workspace/coverage/cover_reg_top/54.xbar_access_same_device.1588295551
58.76	4.60	73.55	11.07	64.68	6.74	31.54	0.15			77.22	9.66	90.19	0.00	15.42	0.00	/workspace/coverage/default/1.chip_sw_plic_sw_irq.2832830223
62.23	3.46	73.55	0.00	64.69	0.01	51.90	20.36			77.23	0.01	90.56	0.37	15.43	0.01	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2570650983
65.52	3.30	73.55	0.00	65.77	1.09	51.90	0.00			77.57	0.34	90.56	0.00	33.78	18.35	/workspace/coverage/cover_reg_top/16.xbar_stress_all.2644341868
68.22	2.70	76.59	3.04	72.36	6.58	52.45	0.55			82.47	4.90	90.56	0.00	34.92	1.14	/workspace/coverage/cover_reg_top/12.chip_csr_rw.1948155660
70.91	2.69	82.47	5.88	76.57	4.21	56.45	4.00			84.51	2.04	90.56	0.00	34.92	0.00	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1776969669
73.53	2.61	82.47	0.00	76.74	0.17	56.45	0.00			84.58	0.07	90.56	0.00	50.36	15.44	/workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3799847386
75.62	2.09	84.64	2.16	77.39	0.64	61.42	4.97			84.68	0.10	90.56	0.00	55.05	4.69	/workspace/coverage/cover_reg_top/23.xbar_error_random.3967381454
77.46	1.84	84.64	0.00	77.39	0.00	61.42	0.00			84.68	0.00	90.56	0.00	66.10	11.06	/workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.4034516467
78.95	1.48	86.77	2.13	79.54	2.16	63.62	2.19			87.11	2.43	90.56	0.00	66.10	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.704247709
80.19	1.24	86.77	0.00	79.54	0.00	63.62	0.00			87.11	0.00	90.56	0.00	73.53	7.43	/workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1866676975
81.40	1.22	86.81	0.05	80.86	1.32	63.62	0.00			87.33	0.22	90.56	0.00	79.24	5.71	/workspace/coverage/cover_reg_top/94.xbar_stress_all.3271017573
82.43	1.03	87.17	0.36	81.20	0.33	68.08	4.46			87.60	0.27	91.11	0.56	79.44	0.20	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.219871251
83.43	0.99	88.70	1.52	83.35	2.16	68.44	0.36			89.53	1.93	91.11	0.00	79.44	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4069756532
84.39	0.96	88.84	0.14	83.51	0.16	71.82	3.39			89.56	0.03	91.30	0.19	81.31	1.87	/workspace/coverage/default/0.chip_sw_alert_test.2140227488
85.15	0.76	89.11	0.27	83.61	0.09	71.84	0.01			89.66	0.10	95.37	4.07	81.31	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1605916351
85.90	0.75	89.11	0.00	83.70	0.09	71.84	0.00			89.67	0.02	95.37	0.00	85.69	4.38	/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.89839314
86.61	0.71	90.31	1.20	84.68	0.98	72.78	0.94			90.83	1.15	95.37	0.00	85.69	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.1816174282
87.29	0.68	91.25	0.94	85.46	0.78	73.72	0.94			91.69	0.87	95.93	0.56	85.69	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2381716845
87.86	0.57	91.25	0.00	85.46	0.00	77.16	3.44			91.69	0.00	95.93	0.00	85.69	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.213731678
88.41	0.55	91.25	0.00	85.46	0.00	77.16	0.00			91.69	0.00	95.93	0.00	88.97	3.28	/workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1144048358
88.90	0.49	91.28	0.03	85.46	0.00	80.09	2.93			91.69	0.00	95.93	0.00	88.97	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3192342746
89.39	0.49	91.28	0.00	85.46	0.00	80.09	0.00			91.69	0.00	95.93	0.00	91.90	2.94	/workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.462942317
89.86	0.47	92.04	0.75	86.33	0.87	80.55	0.46			92.43	0.74	95.93	0.00	91.90	0.00	/workspace/coverage/default/1.chip_sw_gpio.4125255449
90.29	0.43	92.05	0.01	88.37	2.04	80.66	0.11			92.43	0.00	95.93	0.00	92.32	0.41	/workspace/coverage/cover_reg_top/28.chip_tl_errors.2289520994
90.66	0.37	92.39	0.35	88.56	0.19	82.04	1.38			92.53	0.10	96.11	0.19	92.32	0.00	/workspace/coverage/default/1.rom_e2e_smoke.2543958899
91.02	0.36	92.39	0.00	88.56	0.00	82.04	0.00			92.53	0.00	96.11	0.00	94.50	2.19	/workspace/coverage/cover_reg_top/74.xbar_access_same_device.551626798
91.37	0.34	92.93	0.53	89.04	0.48	82.61	0.56			93.02	0.49	96.11	0.00	94.50	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3513219471
91.68	0.31	92.94	0.01	89.04	0.01	84.42	1.81			93.02	0.00	96.11	0.00	94.55	0.05	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.310952380
91.94	0.26	92.94	0.00	89.09	0.04	84.42	0.00			93.03	0.02	96.11	0.00	96.04	1.49	/workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.3668686107
92.17	0.23	93.22	0.28	89.35	0.27	84.91	0.49			93.39	0.35	96.11	0.00	96.04	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.2109852422
92.39	0.22	93.49	0.28	89.56	0.21	85.53	0.61			93.59	0.20	96.11	0.00	96.05	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.2777095745
92.59	0.20	93.49	0.00	89.56	0.00	86.70	1.17			93.59	0.00	96.11	0.00	96.05	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3235622504
92.78	0.20	93.57	0.08	90.07	0.51	86.79	0.09			94.08	0.49	96.11	0.00	96.05	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.2772763535
92.93	0.15	93.79	0.22	90.71	0.63	86.82	0.03			94.13	0.05	96.11	0.00	96.05	0.00	/workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.1430675720
93.08	0.15	93.79	0.00	90.71	0.00	87.71	0.89			94.13	0.00	96.11	0.00	96.05	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3056951484
93.23	0.15	94.00	0.21	91.03	0.32	88.06	0.35			94.13	0.00	96.11	0.00	96.05	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2600194819
93.37	0.14	94.00	0.00	91.04	0.01	88.06	0.00			94.13	0.00	96.11	0.00	96.90	0.85	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.951221221
93.50	0.12	94.00	0.00	91.04	0.00	88.80	0.74			94.13	0.00	96.11	0.00	96.90	0.00	/workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3062445204
93.62	0.12	94.01	0.01	91.04	0.00	89.52	0.71			94.13	0.00	96.11	0.00	96.90	0.00	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3788428892
93.73	0.11	94.01	0.00	91.04	0.01	89.52	0.01			94.13	0.00	96.11	0.00	97.56	0.66	/workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.2743462780
93.84	0.11	94.01	0.00	91.68	0.64	89.52	0.00			94.13	0.00	96.11	0.00	97.56	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.1875304443
93.94	0.10	94.03	0.01	91.98	0.30	89.52	0.00			94.45	0.32	96.11	0.00	97.56	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1317498222
94.04	0.10	94.15	0.12	92.11	0.14	89.70	0.18			94.60	0.15	96.11	0.00	97.56	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.153909373
94.12	0.08	94.16	0.01	92.16	0.05	90.09	0.39			94.62	0.02	96.11	0.00	97.56	0.00	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1869817042
94.19	0.07	94.23	0.07	92.33	0.17	90.21	0.11			94.70	0.08	96.11	0.00	97.56	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1752370966
94.25	0.07	94.36	0.13	92.43	0.10	90.27	0.06			94.80	0.10	96.11	0.00	97.56	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1916388379
94.32	0.06	94.36	0.00	92.43	0.01	90.27	0.00			94.80	0.00	96.11	0.00	97.92	0.36	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.1062504255
94.37	0.05	94.36	0.00	92.73	0.30	90.27	0.00			94.80	0.00	96.11	0.00	97.92	0.00	/workspace/coverage/cover_reg_top/8.chip_tl_errors.1663954355
94.41	0.05	94.49	0.13	92.73	0.00	90.41	0.14			94.82	0.02	96.11	0.00	97.92	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.3593348288
94.46	0.05	94.49	0.00	92.86	0.13	90.41	0.01			94.96	0.15	96.11	0.00	97.92	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1105627862
94.51	0.05	94.49	0.00	92.87	0.01	90.41	0.00			94.96	0.00	96.11	0.00	98.19	0.27	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.346361011
94.55	0.04	94.54	0.05	92.95	0.08	90.48	0.07			95.01	0.05	96.11	0.00	98.19	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1926170748
94.59	0.04	94.55	0.01	92.97	0.02	90.52	0.04			95.01	0.00	96.30	0.19	98.19	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2885767662
94.63	0.04	94.56	0.01	92.98	0.01	90.52	0.00			95.04	0.02	96.48	0.19	98.20	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.452034685
94.67	0.04	94.61	0.05	93.11	0.12	90.52	0.00			95.10	0.07	96.48	0.00	98.20	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.4128081796
94.71	0.04	94.61	0.00	93.11	0.00	90.77	0.24			95.10	0.00	96.48	0.00	98.20	0.00	/workspace/coverage/default/2.chip_sw_kmac_idle.3989517157
94.75	0.04	94.64	0.03	93.11	0.01	90.77	0.01			95.11	0.01	96.67	0.19	98.21	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.1627023504
94.79	0.04	94.65	0.01	93.12	0.01	90.77	0.01			95.12	0.01	96.85	0.19	98.23	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.69912425
94.83	0.04	94.65	0.01	93.13	0.01	90.78	0.01			95.13	0.01	97.04	0.19	98.24	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.334412107
94.86	0.03	94.65	0.00	93.13	0.00	90.97	0.20			95.13	0.00	97.04	0.00	98.24	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2435236996
94.89	0.03	94.65	0.00	93.14	0.01	90.98	0.01			95.13	0.00	97.22	0.19	98.24	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2803423852
94.92	0.03	94.65	0.00	93.26	0.12	90.98	0.00			95.18	0.05	97.22	0.00	98.24	0.00	/workspace/coverage/cover_reg_top/43.xbar_stress_all.2235331307
94.95	0.03	94.72	0.07	93.28	0.03	90.99	0.01			95.23	0.05	97.22	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1560307039
94.97	0.02	94.72	0.00	93.28	0.00	91.13	0.14			95.23	0.00	97.22	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.1945869695
94.99	0.02	94.75	0.03	93.32	0.04	91.16	0.03			95.25	0.02	97.22	0.00	98.24	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1237443664
95.01	0.02	94.80	0.05	93.37	0.05	91.16	0.00			95.27	0.02	97.22	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.4102931027
95.03	0.02	94.80	0.00	93.48	0.11	91.16	0.00			95.27	0.00	97.22	0.00	98.24	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.4185778273
95.05	0.02	94.80	0.00	93.48	0.00	91.16	0.00			95.27	0.00	97.22	0.00	98.34	0.11	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3083757125
95.06	0.02	94.80	0.00	93.58	0.10	91.16	0.00			95.27	0.00	97.22	0.00	98.34	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.3351713413
95.08	0.02	94.81	0.01	93.58	0.00	91.25	0.08			95.27	0.01	97.22	0.00	98.34	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.52945392
95.10	0.02	94.81	0.00	93.58	0.00	91.25	0.00			95.27	0.00	97.22	0.00	98.44	0.09	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.1512808298
95.11	0.02	94.81	0.00	93.58	0.00	91.25	0.00			95.27	0.00	97.22	0.00	98.53	0.09	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.3376444204
95.13	0.02	94.83	0.02	93.60	0.02	91.26	0.01			95.30	0.02	97.22	0.00	98.54	0.01	/workspace/coverage/default/76.chip_sw_all_escalation_resets.2207537570
95.14	0.02	94.83	0.01	93.64	0.04	91.31	0.05			95.30	0.00	97.22	0.00	98.54	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2506958808
95.16	0.02	94.84	0.01	93.66	0.01	91.37	0.06			95.31	0.01	97.22	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/5.chip_csr_rw.3216228172
95.17	0.01	94.84	0.00	93.74	0.09	91.37	0.00			95.31	0.00	97.22	0.00	98.54	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1094637404
95.18	0.01	94.85	0.01	93.78	0.03	91.39	0.02			95.32	0.02	97.22	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.830438519
95.20	0.01	94.85	0.00	93.78	0.00	91.46	0.07			95.32	0.00	97.22	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_flash_init.3086435503
95.21	0.01	94.85	0.00	93.78	0.00	91.53	0.07			95.32	0.00	97.22	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1679095629
95.22	0.01	94.85	0.00	93.80	0.02	91.53	0.00			95.32	0.00	97.22	0.00	98.59	0.05	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.895327612
95.23	0.01	94.85	0.00	93.86	0.07	91.53	0.00			95.32	0.00	97.22	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/47.xbar_access_same_device.4119219031
95.24	0.01	94.89	0.03	93.89	0.02	91.53	0.00			95.33	0.01	97.22	0.00	98.59	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1870692269
95.25	0.01	94.89	0.00	93.95	0.06	91.53	0.00			95.33	0.00	97.22	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.314734695
95.26	0.01	94.91	0.02	93.95	0.01	91.54	0.01			95.35	0.02	97.22	0.00	98.59	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2080608903
95.27	0.01	94.93	0.02	93.96	0.01	91.54	0.01			95.36	0.02	97.22	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.837496916
95.28	0.01	94.96	0.02	93.97	0.01	91.54	0.01			95.38	0.02	97.22	0.00	98.59	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.343556655
95.29	0.01	94.96	0.00	93.98	0.01	91.54	0.00			95.38	0.00	97.22	0.00	98.63	0.04	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1469385134
95.29	0.01	94.96	0.00	94.03	0.05	91.54	0.00			95.38	0.00	97.22	0.00	98.63	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1941660203
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95.32	0.01	94.97	0.00	94.15	0.04	91.56	0.00			95.39	0.00	97.22	0.00	98.64	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1522066977
95.33	0.01	94.98	0.01	94.18	0.03	91.57	0.01			95.39	0.00	97.22	0.00	98.64	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1773812439
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95.36	0.01	94.98	0.00	94.25	0.00	91.61	0.00			95.39	0.00	97.22	0.00	98.72	0.04	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3712505564
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95.38	0.01	94.98	0.00	94.29	0.01	91.68	0.00			95.39	0.00	97.22	0.00	98.73	0.01	/workspace/coverage/cover_reg_top/5.chip_tl_errors.1927288338
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95.39	0.01	94.98	0.00	94.30	0.00	91.69	0.00			95.39	0.00	97.22	0.00	98.78	0.02	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.723094753
95.40	0.01	94.98	0.00	94.30	0.00	91.69	0.00			95.39	0.00	97.22	0.00	98.80	0.02	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1301112870
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95.41	0.01	94.98	0.00	94.32	0.00	91.74	0.01			95.39	0.00	97.22	0.00	98.83	0.01	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2296005910
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95.44	0.01	94.98	0.00	94.40	0.00	91.75	0.00			95.39	0.00	97.22	0.00	98.88	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2021317696
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95.45	0.01	94.98	0.00	94.40	0.00	91.75	0.00			95.39	0.00	97.22	0.00	98.95	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.4017712719
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95.54	0.01	94.98	0.00	94.40	0.00	91.75	0.00			95.39	0.00	97.22	0.00	99.51	0.01	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2329726583
95.54	0.01	94.98	0.00	94.40	0.00	91.75	0.00			95.39	0.00	97.22	0.00	99.52	0.01	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.479988311
95.55	0.01	94.98	0.00	94.40	0.00	91.75	0.00			95.39	0.00	97.22	0.00	99.53	0.01	/workspace/coverage/default/91.chip_sw_all_escalation_resets.1626658756
95.55	0.01	94.98	0.00	94.41	0.01	91.75	0.00			95.39	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.252316571
95.55	0.01	94.99	0.01	94.41	0.00	91.76	0.01			95.39	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/8.chip_sw_all_escalation_resets.567350726
95.55	0.01	94.99	0.00	94.41	0.00	91.77	0.01			95.39	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3331865200
95.55	0.01	94.99	0.00	94.41	0.00	91.78	0.01			95.39	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2456718101
95.55	0.01	94.99	0.01	94.41	0.00	91.78	0.01			95.39	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.1337317891
95.56	0.01	95.00	0.01	94.41	0.00	91.78	0.01			95.39	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.326541217
95.56	0.01	95.00	0.00	94.41	0.00	91.78	0.00			95.40	0.01	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.1039781241
95.56	0.01	95.00	0.00	94.42	0.01	91.78	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_rw.3085688092
95.56	0.01	95.00	0.00	94.43	0.01	91.78	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/13.xbar_stress_all.111053953
95.56	0.01	95.00	0.01	94.43	0.01	91.78	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3932235463
95.56	0.01	95.00	0.00	94.43	0.00	91.79	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2234659020
95.56	0.01	95.00	0.00	94.43	0.00	91.80	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2560069907
95.56	0.01	95.00	0.00	94.43	0.00	91.80	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3994297836
95.57	0.01	95.00	0.00	94.43	0.00	91.81	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3830168373
95.57	0.01	95.00	0.00	94.43	0.00	91.81	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2860988899
95.57	0.01	95.00	0.00	94.43	0.00	91.82	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1494228921
95.57	0.01	95.00	0.00	94.43	0.00	91.82	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.589161599
95.57	0.01	95.00	0.00	94.43	0.00	91.83	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1502296112
95.57	0.01	95.00	0.00	94.43	0.00	91.83	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/2.chip_sw_flash_init.1205245931
95.57	0.01	95.00	0.00	94.43	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/1.xbar_access_same_device.881652781
95.57	0.01	95.00	0.00	94.44	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3594360626
95.57	0.01	95.00	0.00	94.44	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2416078550
95.57	0.01	95.00	0.00	94.45	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.181665734
95.57	0.01	95.00	0.00	94.45	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/25.chip_tl_errors.1350349491
95.57	0.01	95.00	0.00	94.45	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.124654422
95.57	0.01	95.00	0.00	94.46	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2526566249
95.57	0.01	95.00	0.00	94.46	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.142620539
95.57	0.01	95.00	0.00	94.46	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.55080124
95.58	0.01	95.00	0.00	94.47	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.3080936408
95.58	0.01	95.00	0.00	94.47	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1111379880
95.58	0.01	95.00	0.00	94.47	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1033907586
95.58	0.01	95.00	0.00	94.48	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1393081023
95.58	0.01	95.00	0.00	94.48	0.01	91.83	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.616233532
95.58	0.01	95.00	0.00	94.48	0.00	91.84	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/2.chip_tap_straps_testunlock0.3890608976
95.58	0.01	95.01	0.01	94.48	0.00	91.84	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2523698314
95.58	0.01	95.01	0.01	94.48	0.00	91.84	0.00			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2094258649
95.58	0.01	95.01	0.00	94.48	0.00	91.84	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.1930409592
95.58	0.01	95.01	0.00	94.48	0.00	91.84	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.696818119
95.58	0.01	95.01	0.00	94.48	0.00	91.84	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.264637016
95.58	0.01	95.01	0.00	94.48	0.00	91.84	0.01			95.40	0.00	97.22	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3690982527

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1594885880
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3181851725
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1585295982
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3282195555
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.556046427
/workspace/coverage/cover_reg_top/0.chip_tl_errors.4221035258
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2973979656
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3858330475
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3241114328
/workspace/coverage/cover_reg_top/0.xbar_error_random.1993451502
/workspace/coverage/cover_reg_top/0.xbar_random.859654597
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2982820032
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2517407407
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2908657799
/workspace/coverage/cover_reg_top/0.xbar_same_source.923920520
/workspace/coverage/cover_reg_top/0.xbar_smoke.974558464
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1983092360
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1632383152
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2319704891
/workspace/coverage/cover_reg_top/0.xbar_stress_all.397115281
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.411321481
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.974924122
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1097222152
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1118544686
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.411205487
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3056474629
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.271109866
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1353429897
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2242780938
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2806975160
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3116398218
/workspace/coverage/cover_reg_top/1.xbar_error_random.3813996896
/workspace/coverage/cover_reg_top/1.xbar_random.2204348928
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2997199007
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.211164258
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.686663867
/workspace/coverage/cover_reg_top/1.xbar_same_source.2985495001
/workspace/coverage/cover_reg_top/1.xbar_smoke.978228493
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2984096031
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3949720698
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2092446209
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1767483147
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2993786317
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3396997556
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3325710352
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2481855746
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2165314270
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2667151904
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1951489645
/workspace/coverage/cover_reg_top/10.xbar_error_random.2537260177
/workspace/coverage/cover_reg_top/10.xbar_random.2211294685
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3603997346
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3797826804
/workspace/coverage/cover_reg_top/10.xbar_same_source.3102981468
/workspace/coverage/cover_reg_top/10.xbar_smoke.3451135356
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1092701791
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1527954780
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3078246641
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1725822638
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2000627555
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3983477004
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.4016101842
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2533764741
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1614710095
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2598946934
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2086232070
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3028475005
/workspace/coverage/cover_reg_top/11.xbar_error_random.1345734817
/workspace/coverage/cover_reg_top/11.xbar_random.363808139
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3528310026
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.4197103360
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.4283579136
/workspace/coverage/cover_reg_top/11.xbar_same_source.2587710240
/workspace/coverage/cover_reg_top/11.xbar_smoke.1954185861
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2526542600
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.123951219
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3263696742
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1318625081
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3867466756
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1543825414
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3470279291
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3923484734
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1708605877
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2136308167
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.4014111685
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2042023310
/workspace/coverage/cover_reg_top/12.xbar_error_random.3313696193
/workspace/coverage/cover_reg_top/12.xbar_random.3418198029
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1702373510
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1134371408
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.4066579731
/workspace/coverage/cover_reg_top/12.xbar_same_source.509528716
/workspace/coverage/cover_reg_top/12.xbar_smoke.1288654717
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3631345959
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.946885469
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1955248855
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1352885062
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.289692122
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1163204202
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1841717854
/workspace/coverage/cover_reg_top/13.chip_csr_rw.1043882122
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3282273500
/workspace/coverage/cover_reg_top/13.chip_tl_errors.4249934949
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.4202497198
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.308860210
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2010422256
/workspace/coverage/cover_reg_top/13.xbar_error_random.4139357743
/workspace/coverage/cover_reg_top/13.xbar_random.1225131293
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3074421934
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.701221458
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4047841194
/workspace/coverage/cover_reg_top/13.xbar_same_source.1512547323
/workspace/coverage/cover_reg_top/13.xbar_smoke.2748788323
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2373139039
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1816518857
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1053182799
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1995833959
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2128229548
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.4166234769
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1635665448
/workspace/coverage/cover_reg_top/14.chip_csr_rw.2348126599
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3080278687
/workspace/coverage/cover_reg_top/14.chip_tl_errors.2240327541
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.608579936
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2553659482
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1080006744
/workspace/coverage/cover_reg_top/14.xbar_error_random.1543965435
/workspace/coverage/cover_reg_top/14.xbar_random.2853242282
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2944792765
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1306380708
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2246979997
/workspace/coverage/cover_reg_top/14.xbar_same_source.2197677705
/workspace/coverage/cover_reg_top/14.xbar_smoke.3024296001
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.1693934016
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.989149870
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3837362908
/workspace/coverage/cover_reg_top/14.xbar_stress_all.3816025451
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.179803221
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2257995253
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2313874772
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/workspace/coverage/default/9.chip_sw_all_escalation_resets.1433897666
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2608859653
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3933439501
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1693173253
/workspace/coverage/default/93.chip_sw_all_escalation_resets.771870254
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2313528756
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3954665348
/workspace/coverage/default/96.chip_sw_all_escalation_resets.800430421
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3019532635
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2912755250
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1591204752
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3694132980
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3093264505
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.401830088
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.342640122
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3090925623
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3280419278
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1118668857

---

Total test records in report: 2735

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2317524947			May 16 04:23:29 PM PDT 24	May 16 05:12:23 PM PDT 24	17396870440 ps
T2	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2570650983			May 16 04:23:27 PM PDT 24	May 16 04:49:10 PM PDT 24	7975131796 ps
T3	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1869817042			May 16 04:10:57 PM PDT 24	May 16 04:37:12 PM PDT 24	7254781782 ps
T102	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.932964924			May 16 04:08:24 PM PDT 24	May 16 05:09:29 PM PDT 24	18919712071 ps
T59	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1669726097			May 16 04:29:04 PM PDT 24	May 16 04:34:20 PM PDT 24	3500430360 ps
T98	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1237443664			May 16 04:30:16 PM PDT 24	May 16 04:40:05 PM PDT 24	4172812664 ps
T33	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3343680130			May 16 04:02:11 PM PDT 24	May 16 04:07:58 PM PDT 24	4896462070 ps
T4	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3438373045			May 16 04:02:49 PM PDT 24	May 16 04:13:36 PM PDT 24	6259279042 ps
T60	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1319937368			May 16 04:25:53 PM PDT 24	May 16 04:38:00 PM PDT 24	4246708312 ps
T132	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3797435494			May 16 04:27:34 PM PDT 24	May 16 05:03:04 PM PDT 24	12787489432 ps
T45	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.219871251			May 16 04:14:06 PM PDT 24	May 16 04:24:02 PM PDT 24	5599757861 ps
T355	/workspace/coverage/default/0.chip_sw_aes_idle.1017911890			May 16 04:03:27 PM PDT 24	May 16 04:08:06 PM PDT 24	2848053612 ps
T89	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1284513899			May 16 04:29:15 PM PDT 24	May 16 04:38:39 PM PDT 24	5282477000 ps
T90	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3451418961			May 16 04:08:24 PM PDT 24	May 16 04:36:21 PM PDT 24	13395538051 ps
T116	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1011088672			May 16 04:24:30 PM PDT 24	May 16 04:27:52 PM PDT 24	2327236019 ps
T184	/workspace/coverage/default/42.chip_sw_all_escalation_resets.2777095745			May 16 04:28:27 PM PDT 24	May 16 04:38:06 PM PDT 24	5865172210 ps
T187	/workspace/coverage/default/2.chip_sw_kmac_idle.3989517157			May 16 04:24:52 PM PDT 24	May 16 04:30:02 PM PDT 24	3089158546 ps
T286	/workspace/coverage/default/0.chip_sw_example_rom.2866237009			May 16 04:01:12 PM PDT 24	May 16 04:02:45 PM PDT 24	2032723736 ps
T5	/workspace/coverage/default/0.chip_jtag_mem_access.3121288446			May 16 03:56:10 PM PDT 24	May 16 04:18:04 PM PDT 24	13702616388 ps
T185	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.153909373			May 16 04:07:55 PM PDT 24	May 16 04:35:38 PM PDT 24	10117338464 ps
T186	/workspace/coverage/default/92.chip_sw_all_escalation_resets.1693173253			May 16 04:32:40 PM PDT 24	May 16 04:41:14 PM PDT 24	4646192920 ps
T16	/workspace/coverage/default/0.chip_sw_usbdev_vbus.2004697019			May 16 04:03:46 PM PDT 24	May 16 04:07:45 PM PDT 24	2725287056 ps
T155	/workspace/coverage/default/0.chip_sw_edn_auto_mode.1945869695			May 16 04:04:22 PM PDT 24	May 16 04:25:10 PM PDT 24	5263585278 ps
T112	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3227131873			May 16 04:11:48 PM PDT 24	May 16 04:20:36 PM PDT 24	5465458460 ps
T312	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2296005910			May 16 04:29:35 PM PDT 24	May 16 04:35:38 PM PDT 24	4290782516 ps
T101	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.310952380			May 16 04:05:43 PM PDT 24	May 16 04:19:23 PM PDT 24	6492187227 ps
T620	/workspace/coverage/default/1.chip_sw_aes_entropy.3025809538			May 16 04:08:48 PM PDT 24	May 16 04:12:11 PM PDT 24	2271391150 ps
T310	/workspace/coverage/default/69.chip_sw_all_escalation_resets.2052529210			May 16 04:30:09 PM PDT 24	May 16 04:38:57 PM PDT 24	4720696280 ps
T153	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.912621211			May 16 04:30:45 PM PDT 24	May 16 04:43:39 PM PDT 24	4758879775 ps
T46	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2791170447			May 16 04:07:19 PM PDT 24	May 16 04:17:05 PM PDT 24	5828594880 ps
T6	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3056951484			May 16 04:05:28 PM PDT 24	May 16 04:43:35 PM PDT 24	23934178403 ps
T83	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3788428892			May 16 04:11:03 PM PDT 24	May 16 04:30:52 PM PDT 24	9557558980 ps
T217	/workspace/coverage/default/1.chip_sw_plic_sw_irq.2832830223			May 16 04:12:20 PM PDT 24	May 16 04:16:18 PM PDT 24	3033851508 ps
T188	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.213731678			May 16 04:04:07 PM PDT 24	May 16 05:16:38 PM PDT 24	13842154110 ps
T61	/workspace/coverage/default/2.chip_sival_flash_info_access.2159445975			May 16 04:24:59 PM PDT 24	May 16 04:31:02 PM PDT 24	3437068530 ps
T13	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1926170748			May 16 04:27:20 PM PDT 24	May 16 04:50:52 PM PDT 24	8092838251 ps
T69	/workspace/coverage/default/76.chip_sw_all_escalation_resets.2207537570			May 16 04:30:10 PM PDT 24	May 16 04:40:28 PM PDT 24	6006599260 ps
T81	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2814418201			May 16 04:04:09 PM PDT 24	May 16 04:15:01 PM PDT 24	4917853124 ps
T360	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1806500338			May 16 04:29:38 PM PDT 24	May 16 04:37:38 PM PDT 24	4132713872 ps
T14	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1664568471			May 16 04:31:42 PM PDT 24	May 16 04:40:04 PM PDT 24	4160201832 ps
T17	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4161928344			May 16 04:25:38 PM PDT 24	May 16 04:32:16 PM PDT 24	7290622200 ps
T113	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2885767662			May 16 04:03:43 PM PDT 24	May 16 04:12:26 PM PDT 24	3969183037 ps
T145	/workspace/coverage/default/2.chip_sw_otbn_randomness.2836153770			May 16 04:28:47 PM PDT 24	May 16 04:42:25 PM PDT 24	5934628600 ps
T146	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2042865620			May 16 04:27:14 PM PDT 24	May 16 04:45:47 PM PDT 24	7021941276 ps
T147	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1618101530			May 16 04:30:06 PM PDT 24	May 16 04:36:51 PM PDT 24	3327384966 ps
T18	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3363692538			May 16 04:03:25 PM PDT 24	May 16 05:55:41 PM PDT 24	31806769346 ps
T95	/workspace/coverage/default/2.chip_tap_straps_dev.2807553107			May 16 04:27:09 PM PDT 24	May 16 04:53:29 PM PDT 24	18135591227 ps
T148	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1975684050			May 16 04:29:41 PM PDT 24	May 16 04:35:44 PM PDT 24	3575878774 ps
T149	/workspace/coverage/default/2.chip_sw_edn_auto_mode.56333106			May 16 04:28:32 PM PDT 24	May 16 04:43:22 PM PDT 24	4413572830 ps
T150	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.414061750			May 16 04:30:01 PM PDT 24	May 16 04:36:09 PM PDT 24	3485489416 ps
T277	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1792456739			May 16 04:31:14 PM PDT 24	May 16 04:37:40 PM PDT 24	3427793464 ps
T808	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.263963865			May 16 04:07:03 PM PDT 24	May 16 04:11:36 PM PDT 24	2996542856 ps
T189	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.413978901			May 16 04:09:38 PM PDT 24	May 16 04:13:10 PM PDT 24	2284300872 ps
T245	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1403115706			May 16 04:08:15 PM PDT 24	May 16 05:03:25 PM PDT 24	29273161778 ps
T204	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.554351055			May 16 04:08:47 PM PDT 24	May 16 04:21:24 PM PDT 24	4687409232 ps
T77	/workspace/coverage/default/0.chip_tap_straps_testunlock0.3593348288			May 16 04:04:16 PM PDT 24	May 16 04:11:08 PM PDT 24	5273967306 ps
T82	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1930964289			May 16 04:12:51 PM PDT 24	May 16 04:24:24 PM PDT 24	3978563116 ps
T154	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3013273432			May 16 04:24:24 PM PDT 24	May 16 04:37:04 PM PDT 24	3475741950 ps
T151	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2482168476			May 16 04:29:32 PM PDT 24	May 16 05:26:04 PM PDT 24	25017355860 ps
T180	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.392293524			May 16 04:26:30 PM PDT 24	May 16 05:00:30 PM PDT 24	12868197200 ps
T156	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.343556655			May 16 04:25:48 PM PDT 24	May 16 04:34:27 PM PDT 24	6549286154 ps
T212	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1445672250			May 16 04:25:59 PM PDT 24	May 16 04:32:50 PM PDT 24	3909737703 ps
T193	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.4034391783			May 16 04:13:18 PM PDT 24	May 16 04:34:55 PM PDT 24	7064882348 ps
T42	/workspace/coverage/default/1.rom_e2e_smoke.2543958899			May 16 04:25:23 PM PDT 24	May 16 05:40:00 PM PDT 24	17438042390 ps
T809	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.335513013			May 16 04:09:38 PM PDT 24	May 16 04:18:40 PM PDT 24	6477350552 ps
T15	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.4234359518			May 16 04:04:06 PM PDT 24	May 16 04:15:37 PM PDT 24	3623306060 ps
T19	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2381716845			May 16 04:23:33 PM PDT 24	May 16 04:46:09 PM PDT 24	20993635200 ps
T606	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.404374813			May 16 04:30:43 PM PDT 24	May 16 04:36:54 PM PDT 24	3687596800 ps
T74	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1716814936			May 16 04:23:09 PM PDT 24	May 16 04:42:26 PM PDT 24	8419145750 ps
T78	/workspace/coverage/default/1.chip_tap_straps_testunlock0.2951053077			May 16 04:13:07 PM PDT 24	May 16 04:23:16 PM PDT 24	7230685409 ps
T810	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1244265597			May 16 04:08:18 PM PDT 24	May 16 04:16:14 PM PDT 24	6796220054 ps
T369	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2020607203			May 16 04:30:35 PM PDT 24	May 16 04:35:27 PM PDT 24	4042172052 ps
T319	/workspace/coverage/default/88.chip_sw_all_escalation_resets.2185821551			May 16 04:31:17 PM PDT 24	May 16 04:41:37 PM PDT 24	6366349950 ps
T99	/workspace/coverage/default/0.chip_sw_flash_init.3086435503			May 16 04:02:15 PM PDT 24	May 16 04:33:51 PM PDT 24	18849505258 ps
T327	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.79089950			May 16 04:27:12 PM PDT 24	May 16 04:30:55 PM PDT 24	2476476845 ps
T811	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1700461884			May 16 04:23:23 PM PDT 24	May 16 04:32:43 PM PDT 24	4132315028 ps
T117	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.4104212204			May 16 04:14:14 PM PDT 24	May 16 04:18:52 PM PDT 24	2366101096 ps
T190	/workspace/coverage/default/1.chip_sw_kmac_idle.1044234133			May 16 04:11:47 PM PDT 24	May 16 04:15:35 PM PDT 24	2850763580 ps
T328	/workspace/coverage/default/2.chip_sw_hmac_enc.402476081			May 16 04:30:16 PM PDT 24	May 16 04:35:13 PM PDT 24	3549127274 ps
T219	/workspace/coverage/default/28.chip_sw_all_escalation_resets.1647149259			May 16 04:29:50 PM PDT 24	May 16 04:37:49 PM PDT 24	5115425980 ps
T47	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1162325607			May 16 04:14:35 PM PDT 24	May 16 04:20:21 PM PDT 24	7440518304 ps
T329	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1564753197			May 16 04:15:20 PM PDT 24	May 16 04:19:13 PM PDT 24	2727231332 ps
T371	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1324352180			May 16 04:30:45 PM PDT 24	May 16 04:49:18 PM PDT 24	7530185283 ps
T372	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2656211045			May 16 04:24:28 PM PDT 24	May 16 04:28:35 PM PDT 24	3280090574 ps
T243	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3089948586			May 16 04:22:14 PM PDT 24	May 16 04:25:34 PM PDT 24	2710338200 ps
T373	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2303398346			May 16 04:36:37 PM PDT 24	May 16 04:43:50 PM PDT 24	3428922418 ps
T812	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.3308462388			May 16 04:04:05 PM PDT 24	May 16 04:21:29 PM PDT 24	5491232196 ps
T380	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.479988311			May 16 04:26:38 PM PDT 24	May 16 04:32:41 PM PDT 24	3717421908 ps
T293	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1773812439			May 16 04:08:39 PM PDT 24	May 16 04:19:25 PM PDT 24	4518597535 ps
T68	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2247733678			May 16 04:03:58 PM PDT 24	May 16 04:09:39 PM PDT 24	3243914606 ps
T311	/workspace/coverage/default/0.chip_sw_flash_crash_alert.4216545677			May 16 04:07:53 PM PDT 24	May 16 04:17:39 PM PDT 24	5223127338 ps
T813	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1672771808			May 16 04:15:12 PM PDT 24	May 16 04:19:29 PM PDT 24	3460864631 ps
T237	/workspace/coverage/default/14.chip_sw_all_escalation_resets.69912425			May 16 04:30:12 PM PDT 24	May 16 04:43:41 PM PDT 24	4922018026 ps
T278	/workspace/coverage/default/2.chip_sw_edn_boot_mode.1504405149			May 16 04:23:31 PM PDT 24	May 16 04:31:33 PM PDT 24	2727852840 ps
T21	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1916388379			May 16 04:24:29 PM PDT 24	May 16 04:46:48 PM PDT 24	20525155572 ps
T279	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3565050486			May 16 04:08:07 PM PDT 24	May 16 04:24:44 PM PDT 24	7462808066 ps
T280	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.670284925			May 16 04:11:07 PM PDT 24	May 16 04:21:13 PM PDT 24	4387816120 ps
T281	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3378233390			May 16 04:05:49 PM PDT 24	May 16 04:12:29 PM PDT 24	2719718508 ps
T282	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1220191019			May 16 04:30:34 PM PDT 24	May 16 04:37:39 PM PDT 24	3871932952 ps
T65	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2601704086			May 16 04:13:49 PM PDT 24	May 16 04:25:46 PM PDT 24	5526941800 ps
T181	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3801349845			May 16 04:07:46 PM PDT 24	May 16 04:18:06 PM PDT 24	3463886886 ps
T182	/workspace/coverage/default/2.chip_tap_straps_prod.803820350			May 16 04:27:36 PM PDT 24	May 16 04:49:18 PM PDT 24	12368897883 ps
T307	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3133721118			May 16 04:26:16 PM PDT 24	May 16 04:29:55 PM PDT 24	2977917216 ps
T25	/workspace/coverage/default/2.chip_sw_gpio_smoketest.3087912386			May 16 04:24:08 PM PDT 24	May 16 04:29:22 PM PDT 24	2930712600 ps
T814	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.4290819372			May 16 04:11:22 PM PDT 24	May 16 04:16:03 PM PDT 24	2374117886 ps
T104	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2268712892			May 16 04:04:04 PM PDT 24	May 16 05:04:51 PM PDT 24	17249514200 ps
T213	/workspace/coverage/default/4.chip_sw_uart_tx_rx.499021651			May 16 04:32:06 PM PDT 24	May 16 04:41:04 PM PDT 24	4647191092 ps
T815	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2801394874			May 16 04:28:25 PM PDT 24	May 16 04:48:58 PM PDT 24	7574134824 ps
T320	/workspace/coverage/default/78.chip_sw_all_escalation_resets.326270666			May 16 04:30:27 PM PDT 24	May 16 04:37:53 PM PDT 24	5721622304 ps
T109	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2376500401			May 16 04:24:59 PM PDT 24	May 16 04:51:45 PM PDT 24	15966413586 ps
T624	/workspace/coverage/default/1.chip_sw_aon_timer_irq.2073624396			May 16 04:09:57 PM PDT 24	May 16 04:17:05 PM PDT 24	4341431768 ps
T816	/workspace/coverage/default/2.chip_sw_csrng_kat_test.4168354734			May 16 04:23:33 PM PDT 24	May 16 04:27:16 PM PDT 24	2414176800 ps
T817	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.657281711			May 16 04:09:37 PM PDT 24	May 16 04:20:20 PM PDT 24	6188926644 ps
T236	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3182084521			May 16 04:08:00 PM PDT 24	May 16 04:49:14 PM PDT 24	28534588834 ps
T220	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.92141953			May 16 04:06:24 PM PDT 24	May 16 04:30:13 PM PDT 24	8010840071 ps
T818	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.1641560640			May 16 04:23:29 PM PDT 24	May 16 04:28:05 PM PDT 24	3541131740 ps
T603	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.4125603134			May 16 04:29:33 PM PDT 24	May 16 04:34:36 PM PDT 24	3364245412 ps
T348	/workspace/coverage/default/1.chip_sw_edn_boot_mode.3491693942			May 16 04:10:39 PM PDT 24	May 16 04:19:22 PM PDT 24	2923001112 ps
T819	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3159576313			May 16 04:02:27 PM PDT 24	May 16 04:34:05 PM PDT 24	8607215080 ps
T820	/workspace/coverage/default/0.chip_sw_example_concurrency.71603411			May 16 04:02:17 PM PDT 24	May 16 04:06:29 PM PDT 24	2503919568 ps
T701	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.518252156			May 16 04:29:39 PM PDT 24	May 16 04:35:20 PM PDT 24	3640298120 ps
T196	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2172387732			May 16 04:23:14 PM PDT 24	May 16 04:27:15 PM PDT 24	2428135192 ps
T7	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4069756532			May 16 04:10:00 PM PDT 24	May 16 04:15:34 PM PDT 24	2842570042 ps
T79	/workspace/coverage/default/3.chip_tap_straps_prod.1841087055			May 16 04:24:27 PM PDT 24	May 16 04:27:03 PM PDT 24	2885085425 ps
T821	/workspace/coverage/default/0.chip_sw_aes_enc.2593557944			May 16 04:05:50 PM PDT 24	May 16 04:10:03 PM PDT 24	3137614580 ps
T222	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2662687109			May 16 04:23:39 PM PDT 24	May 16 04:40:20 PM PDT 24	5998236164 ps
T822	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3236394287			May 16 04:26:04 PM PDT 24	May 16 04:42:28 PM PDT 24	5098076800 ps
T110	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3517913420			May 16 04:32:58 PM PDT 24	May 16 04:38:23 PM PDT 24	3925174360 ps
T96	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.4116811936			May 16 04:07:20 PM PDT 24	May 16 04:30:53 PM PDT 24	7720629560 ps
T205	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3781415698			May 16 04:25:27 PM PDT 24	May 16 04:36:21 PM PDT 24	4054050536 ps
T100	/workspace/coverage/default/1.chip_sw_flash_init.2137272086			May 16 04:07:34 PM PDT 24	May 16 04:33:17 PM PDT 24	18975781280 ps
T20	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.2470238591			May 16 04:02:43 PM PDT 24	May 16 04:11:49 PM PDT 24	3625294946 ps
T823	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.785036843			May 16 04:03:12 PM PDT 24	May 16 04:07:22 PM PDT 24	2796786667 ps
T338	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1458376292			May 16 04:31:56 PM PDT 24	May 16 04:38:03 PM PDT 24	3949187272 ps
T344	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3644402816			May 16 04:22:54 PM PDT 24	May 16 04:32:08 PM PDT 24	5249636070 ps
T232	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2803423852			May 16 04:03:50 PM PDT 24	May 16 04:17:06 PM PDT 24	4661042430 ps
T264	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.933359996			May 16 04:03:07 PM PDT 24	May 16 04:07:12 PM PDT 24	3432389000 ps
T206	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2608859653			May 16 04:27:18 PM PDT 24	May 16 04:35:14 PM PDT 24	3654108192 ps
T265	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3014997859			May 16 04:09:18 PM PDT 24	May 16 04:13:32 PM PDT 24	2821821290 ps
T266	/workspace/coverage/default/68.chip_sw_all_escalation_resets.871979572			May 16 04:29:09 PM PDT 24	May 16 04:39:15 PM PDT 24	6038650434 ps
T267	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.818062801			May 16 04:22:33 PM PDT 24	May 16 04:40:25 PM PDT 24	15323940900 ps
T36	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.637622654			May 16 04:04:05 PM PDT 24	May 16 04:12:26 PM PDT 24	5706117496 ps
T208	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2701902681			May 16 04:24:26 PM PDT 24	May 16 04:36:19 PM PDT 24	4820946200 ps
T223	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.515810524			May 16 04:04:52 PM PDT 24	May 16 04:27:32 PM PDT 24	6699371756 ps
T268	/workspace/coverage/default/0.chip_sw_edn_sw_mode.2582885822			May 16 04:04:55 PM PDT 24	May 16 04:33:09 PM PDT 24	7262917352 ps
T607	/workspace/coverage/default/86.chip_sw_all_escalation_resets.240138915			May 16 04:31:45 PM PDT 24	May 16 04:40:58 PM PDT 24	6040833840 ps
T103	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1605837978			May 16 04:25:25 PM PDT 24	May 16 04:39:02 PM PDT 24	9779095981 ps
T589	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2232330058			May 16 04:03:35 PM PDT 24	May 16 04:08:26 PM PDT 24	3223574296 ps
T370	/workspace/coverage/default/1.chip_sw_edn_auto_mode.1193751882			May 16 04:10:47 PM PDT 24	May 16 04:38:35 PM PDT 24	6504727256 ps
T157	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1935020461			May 16 04:11:17 PM PDT 24	May 16 04:18:39 PM PDT 24	5002432672 ps
T604	/workspace/coverage/default/39.chip_sw_all_escalation_resets.1077277728			May 16 04:28:37 PM PDT 24	May 16 04:37:18 PM PDT 24	4630560708 ps
T824	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1337235344			May 16 04:13:08 PM PDT 24	May 16 04:23:12 PM PDT 24	3487507438 ps
T646	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.383611721			May 16 04:29:26 PM PDT 24	May 16 04:35:04 PM PDT 24	3214315272 ps
T825	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1336794573			May 16 04:22:26 PM PDT 24	May 16 04:29:46 PM PDT 24	3583336200 ps
T48	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3569687976			May 16 04:06:45 PM PDT 24	May 16 04:11:45 PM PDT 24	3867276616 ps
T86	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1385167481			May 16 04:30:42 PM PDT 24	May 16 04:37:33 PM PDT 24	3431113776 ps
T114	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.438646711			May 16 04:16:33 PM PDT 24	May 16 04:26:05 PM PDT 24	4092651960 ps
T393	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3098298808			May 16 04:05:11 PM PDT 24	May 16 04:14:39 PM PDT 24	5226210688 ps
T394	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1960937301			May 16 04:13:37 PM PDT 24	May 16 04:26:11 PM PDT 24	5287774112 ps
T88	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3433912120			May 16 04:28:39 PM PDT 24	May 16 04:35:31 PM PDT 24	4134684712 ps
T209	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3932235463			May 16 04:02:40 PM PDT 24	May 16 04:17:30 PM PDT 24	4833932856 ps
T317	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2805633302			May 16 04:07:20 PM PDT 24	May 16 04:35:24 PM PDT 24	9329788222 ps
T111	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.830357067			May 16 04:32:41 PM PDT 24	May 16 04:37:50 PM PDT 24	3636871540 ps
T203	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3202807216			May 16 04:09:25 PM PDT 24	May 16 04:14:21 PM PDT 24	3563573530 ps
T826	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.4035148593			May 16 04:23:36 PM PDT 24	May 16 04:30:15 PM PDT 24	3039449862 ps
T605	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3169434503			May 16 04:28:15 PM PDT 24	May 16 04:34:04 PM PDT 24	3628408034 ps
T827	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1097419561			May 16 04:12:11 PM PDT 24	May 16 04:22:14 PM PDT 24	7418255328 ps
T183	/workspace/coverage/default/3.chip_tap_straps_dev.2710655551			May 16 04:26:01 PM PDT 24	May 16 04:39:50 PM PDT 24	7278344499 ps
T828	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3183106853			May 16 04:25:30 PM PDT 24	May 16 04:32:31 PM PDT 24	4050230280 ps
T87	/workspace/coverage/default/53.chip_sw_all_escalation_resets.1477669726			May 16 04:28:07 PM PDT 24	May 16 04:38:41 PM PDT 24	4291801484 ps
T22	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.536509061			May 16 04:09:15 PM PDT 24	May 16 04:39:31 PM PDT 24	21997325730 ps
T91	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1042314918			May 16 04:05:52 PM PDT 24	May 16 04:33:15 PM PDT 24	7553384416 ps
T105	/workspace/coverage/default/2.chip_sw_otbn_smoketest.3416601928			May 16 04:24:38 PM PDT 24	May 16 04:48:25 PM PDT 24	7936745466 ps
T643	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3865523641			May 16 04:33:54 PM PDT 24	May 16 04:39:40 PM PDT 24	3262443740 ps
T829	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3422966162			May 16 04:26:06 PM PDT 24	May 16 04:33:41 PM PDT 24	4283399256 ps
T374	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2999336799			May 16 04:08:44 PM PDT 24	May 16 04:15:30 PM PDT 24	4428150488 ps
T830	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3327324563			May 16 04:29:48 PM PDT 24	May 16 04:33:30 PM PDT 24	2461134064 ps
T334	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1922109206			May 16 04:12:07 PM PDT 24	May 16 04:17:07 PM PDT 24	3013012804 ps
T609	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2084518385			May 16 04:28:54 PM PDT 24	May 16 04:35:23 PM PDT 24	3571634568 ps
T316	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3720491584			May 16 04:03:22 PM PDT 24	May 16 04:12:13 PM PDT 24	4015014240 ps
T194	/workspace/coverage/default/2.chip_sw_kmac_entropy.494910459			May 16 04:25:10 PM PDT 24	May 16 04:29:38 PM PDT 24	2384910906 ps
T269	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1618391892			May 16 04:24:59 PM PDT 24	May 16 04:38:11 PM PDT 24	5955577588 ps
T831	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1970608320			May 16 04:20:41 PM PDT 24	May 16 04:25:03 PM PDT 24	3416826960 ps
T356	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1108135515			May 16 04:34:03 PM PDT 24	May 16 04:40:51 PM PDT 24	4067171964 ps
T221	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.505733016			May 16 04:11:19 PM PDT 24	May 16 04:31:58 PM PDT 24	8136752600 ps
T231	/workspace/coverage/default/41.chip_sw_all_escalation_resets.1097648966			May 16 04:29:11 PM PDT 24	May 16 04:39:21 PM PDT 24	4809933448 ps
T331	/workspace/coverage/default/23.chip_sw_all_escalation_resets.1100789873			May 16 04:31:08 PM PDT 24	May 16 04:39:07 PM PDT 24	4692549576 ps
T688	/workspace/coverage/default/2.chip_sw_all_escalation_resets.531203283			May 16 04:22:15 PM PDT 24	May 16 04:32:41 PM PDT 24	4703456192 ps
T335	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3527366036			May 16 04:02:27 PM PDT 24	May 16 04:38:29 PM PDT 24	26068174708 ps
T131	/workspace/coverage/default/43.chip_sw_all_escalation_resets.334412107			May 16 04:28:37 PM PDT 24	May 16 04:37:12 PM PDT 24	5859205496 ps
T136	/workspace/coverage/default/95.chip_sw_all_escalation_resets.3954665348			May 16 04:33:02 PM PDT 24	May 16 04:42:34 PM PDT 24	5288389806 ps
T26	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.4128081796			May 16 04:03:15 PM PDT 24	May 16 04:09:01 PM PDT 24	3901274788 ps
T137	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1145280608			May 16 04:26:43 PM PDT 24	May 16 04:51:25 PM PDT 24	8584306936 ps
T73	/workspace/coverage/default/0.chip_sw_alert_test.2140227488			May 16 04:03:52 PM PDT 24	May 16 04:08:37 PM PDT 24	2975112188 ps
T138	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2346005693			May 16 04:08:18 PM PDT 24	May 16 04:14:51 PM PDT 24	3083566188 ps
T139	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3780569565			May 16 04:10:15 PM PDT 24	May 16 04:14:53 PM PDT 24	2390768672 ps
T10	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1752370966			May 16 04:04:04 PM PDT 24	May 16 04:16:06 PM PDT 24	5826667668 ps
T140	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2520935341			May 16 04:25:51 PM PDT 24	May 16 04:35:07 PM PDT 24	4358168024 ps
T141	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.774309785			May 16 04:03:06 PM PDT 24	May 16 04:09:16 PM PDT 24	3196928184 ps
T133	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3802567733			May 16 04:30:44 PM PDT 24	May 16 04:38:30 PM PDT 24	4793184408 ps
T216	/workspace/coverage/default/1.chip_plic_all_irqs_20.1816174282			May 16 04:12:07 PM PDT 24	May 16 04:24:48 PM PDT 24	4393046448 ps
T832	/workspace/coverage/default/2.rom_keymgr_functest.603161116			May 16 04:29:44 PM PDT 24	May 16 04:39:03 PM PDT 24	5356891802 ps
T833	/workspace/coverage/default/2.chip_sw_example_rom.4250013075			May 16 04:22:24 PM PDT 24	May 16 04:24:39 PM PDT 24	1662438088 ps
T27	/workspace/coverage/default/1.chip_sw_gpio.4125255449			May 16 04:09:18 PM PDT 24	May 16 04:17:15 PM PDT 24	4344806297 ps
T834	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.380164495			May 16 04:24:23 PM PDT 24	May 16 04:30:38 PM PDT 24	3937284680 ps
T636	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3520508692			May 16 04:09:39 PM PDT 24	May 16 04:17:34 PM PDT 24	3953246302 ps
T207	/workspace/coverage/default/2.chip_sw_pattgen_ios.4079909971			May 16 04:23:41 PM PDT 24	May 16 04:27:56 PM PDT 24	2870197752 ps
T835	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1074540363			May 16 04:07:16 PM PDT 24	May 16 04:12:14 PM PDT 24	3055247864 ps
T395	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3138352302			May 16 04:15:51 PM PDT 24	May 16 05:13:47 PM PDT 24	24413767206 ps
T175	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.3158584156			May 16 04:08:43 PM PDT 24	May 16 07:04:59 PM PDT 24	65968595885 ps
T228	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2435236996			May 16 04:16:30 PM PDT 24	May 16 04:50:52 PM PDT 24	18921986175 ps
T836	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2506958808			May 16 04:24:58 PM PDT 24	May 16 04:48:54 PM PDT 24	13425954599 ps
T601	/workspace/coverage/default/0.chip_tap_straps_dev.1039781241			May 16 04:05:11 PM PDT 24	May 16 04:18:47 PM PDT 24	9069835709 ps
T837	/workspace/coverage/default/2.chip_sw_uart_smoketest.1248934472			May 16 04:24:26 PM PDT 24	May 16 04:27:13 PM PDT 24	2590101720 ps
T296	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1689285526			May 16 04:10:20 PM PDT 24	May 16 04:21:42 PM PDT 24	3818856306 ps
T838	/workspace/coverage/default/1.chip_sw_aes_idle.1159321424			May 16 04:12:44 PM PDT 24	May 16 04:17:21 PM PDT 24	3391768970 ps
T642	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.4186853139			May 16 04:28:00 PM PDT 24	May 16 04:34:02 PM PDT 24	3406685638 ps
T839	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.969756548			May 16 04:07:37 PM PDT 24	May 16 04:23:44 PM PDT 24	5721393500 ps
T608	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.769823988			May 16 04:10:27 PM PDT 24	May 16 04:15:29 PM PDT 24	3953191700 ps
T840	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1679095629			May 16 04:08:18 PM PDT 24	May 16 04:19:15 PM PDT 24	4821107932 ps
T290	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1033907586			May 16 04:11:20 PM PDT 24	May 16 04:38:55 PM PDT 24	12044532968 ps
T689	/workspace/coverage/default/98.chip_sw_all_escalation_resets.2912755250			May 16 04:32:29 PM PDT 24	May 16 04:41:02 PM PDT 24	4135975074 ps
T581	/workspace/coverage/default/1.chip_sw_edn_kat.2182889398			May 16 04:13:13 PM PDT 24	May 16 04:24:23 PM PDT 24	3363096696 ps
T378	/workspace/coverage/default/2.chip_sw_kmac_app_rom.1564163651			May 16 04:23:02 PM PDT 24	May 16 04:26:58 PM PDT 24	2490996612 ps
T299	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2523698314			May 16 04:05:19 PM PDT 24	May 16 04:15:44 PM PDT 24	4271689266 ps
T841	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.43465637			May 16 04:23:56 PM PDT 24	May 16 04:42:14 PM PDT 24	8112818070 ps
T842	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.71437191			May 16 04:22:42 PM PDT 24	May 16 04:36:36 PM PDT 24	5478316658 ps
T668	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3048059025			May 16 04:30:51 PM PDT 24	May 16 04:37:31 PM PDT 24	3637119000 ps
T224	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4078271872			May 16 04:25:03 PM PDT 24	May 16 04:52:01 PM PDT 24	9298346914 ps
T843	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2917583505			May 16 04:25:32 PM PDT 24	May 16 04:32:29 PM PDT 24	4133926480 ps
T708	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3787816228			May 16 04:29:44 PM PDT 24	May 16 04:34:33 PM PDT 24	3879784998 ps
T719	/workspace/coverage/default/16.chip_sw_all_escalation_resets.3823181819			May 16 04:28:01 PM PDT 24	May 16 04:38:00 PM PDT 24	4503180256 ps
T80	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3269269268			May 16 04:05:18 PM PDT 24	May 16 04:14:00 PM PDT 24	5283781786 ps
T844	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2188357793			May 16 04:26:07 PM PDT 24	May 16 04:34:24 PM PDT 24	3960283928 ps
T845	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.554293881			May 16 04:10:50 PM PDT 24	May 16 04:21:11 PM PDT 24	8759600368 ps
T846	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1791610323			May 16 04:08:06 PM PDT 24	May 16 04:14:33 PM PDT 24	4343382320 ps
T126	/workspace/coverage/default/3.chip_tap_straps_rma.649715973			May 16 04:23:34 PM PDT 24	May 16 04:30:37 PM PDT 24	4733945241 ps
T847	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1502296112			May 16 04:04:03 PM PDT 24	May 16 04:11:03 PM PDT 24	4696286584 ps
T848	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1832888856			May 16 04:08:36 PM PDT 24	May 16 04:16:54 PM PDT 24	5154842650 ps
T610	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1661777089			May 16 04:32:43 PM PDT 24	May 16 04:38:27 PM PDT 24	3177481136 ps
T849	/workspace/coverage/default/0.chip_sw_kmac_idle.1611308658			May 16 04:03:53 PM PDT 24	May 16 04:08:24 PM PDT 24	3003205960 ps
T118	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2113087537			May 16 04:14:58 PM PDT 24	May 16 04:19:25 PM PDT 24	2806492476 ps
T37	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.339821494			May 16 04:22:58 PM PDT 24	May 16 04:29:02 PM PDT 24	4991710352 ps
T850	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.795740049			May 16 04:25:06 PM PDT 24	May 16 04:35:00 PM PDT 24	4500321896 ps
T678	/workspace/coverage/default/17.chip_sw_all_escalation_resets.3279118918			May 16 04:26:07 PM PDT 24	May 16 04:35:16 PM PDT 24	5485341204 ps
T851	/workspace/coverage/default/20.chip_sw_all_escalation_resets.1504010266			May 16 04:26:44 PM PDT 24	May 16 04:37:22 PM PDT 24	5536614324 ps
T339	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.452034685			May 16 04:29:49 PM PDT 24	May 16 04:37:53 PM PDT 24	3644845080 ps
T852	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3253196644			May 16 04:24:39 PM PDT 24	May 16 04:34:59 PM PDT 24	9074663864 ps
T176	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3538362198			May 16 04:02:51 PM PDT 24	May 16 07:22:16 PM PDT 24	63181955885 ps
T129	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.830438519			May 16 04:03:40 PM PDT 24	May 16 04:13:18 PM PDT 24	3571798370 ps