Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	137224	1			T62	69		T63	20		T64	14
values[2]	8692	1			T242	2		T241	2		T483	3
values[3]	3306	1			T480	6		T388	1		T390	1
values[4]	2043	1			T480	7		T388	1		T492	10
values[5]	1367	1			T480	3		T492	7		T721	3
values[6]	854	1			T480	9		T492	7		T404	3
values[7]	584	1			T480	18		T492	11		T404	3
values[8]	429	1			T480	4		T492	7		T404	17
values[9]	415	1			T480	13		T492	9		T404	4
values[10]	369	1			T480	8		T492	11		T404	9
values[11]	317	1			T480	3		T492	8		T404	10
values[12]	367	1			T480	4		T492	6		T404	6
values[13]	322	1			T480	9		T492	5		T404	11
values[14]	306	1			T480	6		T492	9		T404	22
values[15]	305	1			T480	3		T492	10		T404	5
values[16]	350	1			T480	3		T492	5		T404	3
values[17]	293	1			T480	6		T492	4		T404	5
values[18]	313	1			T480	15		T492	4		T404	3
values[19]	292	1			T480	18		T492	6		T404	3
values[20]	347	1			T480	12		T492	4		T404	11
values[21]	314	1			T480	7		T492	6		T404	8
values[22]	348	1			T480	9		T492	6		T404	5
values[23]	334	1			T480	4		T492	13		T404	5
values[24]	308	1			T480	8		T492	15		T404	7
values[25]	313	1			T480	9		T492	7		T404	9
values[26]	360	1			T480	8		T492	8		T404	11
values[27]	304	1			T480	19		T492	3		T404	13
values[28]	314	1			T480	8		T492	4		T404	5
values[29]	291	1			T480	6		T492	27		T404	3
values[30]	307	1			T480	5		T492	6		T404	2
values[31]	336	1			T480	4		T492	6		T404	11
values[32]	386	1			T480	7		T492	5		T404	8
values[33]	282	1			T480	4		T492	4		T404	12
values[34]	319	1			T480	13		T492	11		T404	12
values[35]	350	1			T480	4		T492	7		T404	7
values[36]	327	1			T480	6		T492	2		T404	3
values[37]	311	1			T480	10		T492	4		T404	19
values[38]	260	1			T480	8		T492	8		T404	5
values[39]	310	1			T480	6		T492	3		T404	5
values[40]	299	1			T480	3		T492	6		T404	4
values[41]	275	1			T480	9		T492	5		T404	8
values[42]	331	1			T480	8		T492	10		T404	6
values[43]	318	1			T480	22		T492	6		T404	4
values[44]	302	1			T480	8		T492	13		T404	4
values[45]	322	1			T480	5		T492	3		T404	6
values[46]	279	1			T480	16		T492	9		T404	29
values[47]	304	1			T480	10		T492	24		T404	5
values[48]	293	1			T480	4		T492	5		T404	7
values[49]	314	1			T480	15		T492	3		T404	11
values[50]	257	1			T480	6		T492	4		T404	3
values[51]	269	1			T480	6		T492	11		T404	7
values[52]	260	1			T480	4		T492	6		T404	2
values[53]	246	1			T480	4		T492	11		T404	5
values[54]	255	1			T480	7		T492	3		T404	3
values[55]	235	1			T480	6		T492	3		T404	3
values[56]	222	1			T480	10		T492	3		T404	4
values[57]	237	1			T480	5		T492	13		T404	3
values[58]	289	1			T480	3		T492	15		T404	6
values[59]	201	1			T480	3		T492	6		T404	4
values[60]	231	1			T480	3		T492	3		T404	6
values[61]	226	1			T480	3		T492	11		T404	8
values[62]	237	1			T492	7		T404	2		T722	2
values[63]	190	1			T492	14		T404	5		T722	2
values[64]	171	1			T492	4		T404	8		T722	2
values[65]	143	1			T492	7		T722	2		T723	7
values[66]	136	1			T492	15		T722	2		T723	2
values[67]	84	1			T492	4		T722	2		T723	4
values[68]	91	1			T492	9		T722	2		T723	4
values[69]	95	1			T492	5		T722	2		T723	7
values[70]	101	1			T492	8		T722	2		T723	2
values[71]	103	1			T492	2		T722	2		T723	7
values[72]	113	1			T722	2		T723	13		T724	2
values[73]	113	1			T722	2		T723	9		T724	2
values[74]	89	1			T722	2		T723	2		T724	2
values[75]	79	1			T722	3		T724	2		T725	1
values[76]	60	1			T722	2		T724	2		T725	1
values[77]	81	1			T722	2		T724	2		T725	1
values[78]	63	1			T722	2		T724	2		T725	1
values[79]	79	1			T722	2		T724	2		T725	1
values[80]	49	1			T722	2		T724	2		T725	1
values[81]	41	1			T722	3		T724	2		T725	1
values[82]	64	1			T722	2		T724	2		T725	1
values[83]	58	1			T722	2		T724	2		T725	1
values[84]	51	1			T722	2		T724	2		T725	1
values[85]	45	1			T722	2		T724	2		T725	1
values[86]	45	1			T722	2		T724	2		T725	1
values[87]	50	1			T722	2		T724	3		T725	1
values[88]	72	1			T722	2		T724	9		T725	1
values[89]	53	1			T722	2		T724	5		T725	1
values[90]	77	1			T722	2		T724	8		T725	1
values[91]	74	1			T722	2		T724	8		T725	1
values[92]	58	1			T722	2		T724	5		T725	1
values[93]	62	1			T722	2		T724	5		T725	1
values[94]	51	1			T722	2		T724	4		T725	1
values[95]	54	1			T722	2		T724	3		T725	1
values[96]	73	1			T722	2		T724	7		T725	1
values[97]	55	1			T722	2		T724	7		T725	1
values[98]	64	1			T722	2		T724	5		T725	1
values[99]	63	1			T722	2		T724	2		T725	1
values[100]	55	1			T722	2		T724	6		T725	1
values[101]	46	1			T722	2		T724	3		T725	1
values[102]	64	1			T722	2		T724	5		T725	1
values[103]	59	1			T722	2		T724	3		T725	1
values[104]	65	1			T722	2		T724	5		T725	1
values[105]	68	1			T722	2		T724	7		T725	1
values[106]	56	1			T722	2		T724	7		T725	1
values[107]	64	1			T722	2		T724	9		T725	1
values[108]	58	1			T722	2		T724	3		T725	1
values[109]	47	1			T722	2		T724	5		T725	1
values[110]	63	1			T722	2		T724	4		T725	1
values[111]	77	1			T722	4		T724	3		T725	1
values[112]	97	1			T722	3		T724	3		T725	1
values[113]	83	1			T722	6		T724	5		T725	1
values[114]	77	1			T722	4		T724	5		T725	1
values[115]	82	1			T722	3		T724	7		T725	1
values[116]	61	1			T722	3		T724	6		T725	1
values[117]	81	1			T722	6		T724	13		T725	2
values[118]	62	1			T722	8		T724	2		T725	1
values[119]	72	1			T722	2		T724	3		T725	3
values[120]	76	1			T722	4		T724	2		T725	1
values[121]	78	1			T722	3		T724	3		T725	1
values[122]	64	1			T722	3		T724	3		T725	1
values[123]	69	1			T722	4		T724	6		T725	2
values[124]	55	1			T722	4		T724	2		T725	2
values[125]	72	1			T722	7		T724	4		T725	1
values[126]	116	1			T722	2		T724	3		T725	1
values[127]	722	1			T722	54		T724	51		T725	16
values[128]	5732	1			T722	691		T724	520		T725	258

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	163304	1			T62	59		T63	16		T64	11
values[2]	4889	1			T63	2		T241	1		T483	7
values[3]	2264	1			T388	2		T554	1		T402	1
values[4]	1470	1			T388	1		T726	25		T580	1
values[5]	1217	1			T726	22		T580	6		T727	19
values[6]	1019	1			T726	10		T580	16		T727	5
values[7]	858	1			T726	2		T580	18		T728	1
values[8]	711	1			T580	12		T728	5		T433	21
values[9]	616	1			T580	15		T728	7		T433	26
values[10]	553	1			T580	4		T728	19		T433	30
values[11]	480	1			T580	2		T728	38		T433	22
values[12]	549	1			T580	8		T728	31		T433	15
values[13]	554	1			T580	10		T728	46		T433	20
values[14]	552	1			T580	15		T728	50		T433	18
values[15]	515	1			T580	16		T728	17		T433	8
values[16]	525	1			T580	13		T728	23		T433	10
values[17]	442	1			T580	7		T728	18		T433	20
values[18]	490	1			T580	21		T728	12		T433	9
values[19]	459	1			T580	22		T728	10		T433	2
values[20]	406	1			T580	13		T728	27		T433	3
values[21]	317	1			T580	12		T728	26		T433	7
values[22]	343	1			T580	21		T728	29		T433	6
values[23]	327	1			T580	24		T728	40		T433	10
values[24]	259	1			T580	11		T728	19		T433	12
values[25]	237	1			T580	9		T728	6		T433	6
values[26]	238	1			T580	30		T433	2		T443	9
values[27]	235	1			T580	24		T433	2		T443	3
values[28]	218	1			T580	25		T433	1		T443	6
values[29]	159	1			T580	7		T433	2		T443	2
values[30]	124	1			T580	8		T433	11		T443	3
values[31]	171	1			T580	15		T433	9		T443	6
values[32]	174	1			T580	22		T433	14		T443	1
values[33]	153	1			T580	23		T433	14		T443	6
values[34]	152	1			T580	24		T433	22		T443	8
values[35]	151	1			T580	39		T433	17		T443	11
values[36]	136	1			T580	12		T433	8		T443	29
values[37]	99	1			T580	1		T433	2		T443	28
values[38]	96	1			T433	14		T443	10		T729	1
values[39]	116	1			T433	20		T443	4		T729	1
values[40]	92	1			T433	17		T443	1		T729	1
values[41]	75	1			T433	20		T729	1		T730	3
values[42]	84	1			T433	16		T729	1		T730	2
values[43]	70	1			T433	8		T729	1		T730	2
values[44]	66	1			T433	3		T729	1		T730	2
values[45]	52	1			T729	1		T730	2		T731	2
values[46]	69	1			T729	1		T730	2		T731	2
values[47]	58	1			T729	1		T730	2		T731	2
values[48]	60	1			T729	1		T730	2		T731	2
values[49]	65	1			T729	1		T730	2		T731	2
values[50]	65	1			T729	1		T730	2		T731	2
values[51]	52	1			T729	1		T730	2		T731	2
values[52]	54	1			T729	1		T730	2		T731	2
values[53]	60	1			T729	1		T730	2		T731	2
values[54]	57	1			T729	1		T730	2		T731	2
values[55]	50	1			T729	1		T730	2		T731	2
values[56]	70	1			T729	1		T730	2		T731	2
values[57]	67	1			T729	1		T730	2		T731	2
values[58]	39	1			T729	1		T730	2		T731	2
values[59]	37	1			T729	1		T730	2		T731	2
values[60]	36	1			T729	1		T730	2		T731	2
values[61]	35	1			T729	1		T730	2		T731	2
values[62]	34	1			T729	1		T730	2		T731	2
values[63]	33	1			T729	1		T730	2		T731	2
values[64]	33	1			T729	1		T730	2		T731	2
values[65]	39	1			T729	1		T730	2		T731	2
values[66]	35	1			T729	1		T730	2		T731	2
values[67]	39	1			T729	1		T730	2		T731	2
values[68]	39	1			T729	1		T730	2		T731	2
values[69]	31	1			T729	1		T730	2		T731	2
values[70]	36	1			T729	1		T730	2		T731	2
values[71]	40	1			T729	1		T730	2		T731	2
values[72]	37	1			T729	1		T730	2		T731	2
values[73]	44	1			T729	1		T730	2		T731	2
values[74]	37	1			T729	1		T730	2		T731	2
values[75]	36	1			T729	1		T730	2		T731	2
values[76]	37	1			T729	1		T730	2		T731	2
values[77]	42	1			T729	1		T730	2		T731	2
values[78]	43	1			T729	1		T730	2		T731	2
values[79]	37	1			T729	1		T730	2		T731	2
values[80]	41	1			T729	1		T730	2		T731	2
values[81]	52	1			T729	1		T730	2		T731	2
values[82]	47	1			T729	1		T730	2		T731	2
values[83]	41	1			T729	1		T730	2		T731	2
values[84]	43	1			T729	1		T730	2		T731	2
values[85]	43	1			T729	1		T730	2		T731	2
values[86]	54	1			T729	1		T730	2		T731	2
values[87]	47	1			T729	2		T730	2		T731	2
values[88]	59	1			T729	4		T730	2		T731	2
values[89]	59	1			T729	7		T730	2		T731	2
values[90]	57	1			T729	2		T730	2		T731	2
values[91]	42	1			T729	2		T730	2		T731	2
values[92]	54	1			T729	2		T730	2		T731	2
values[93]	58	1			T729	5		T730	2		T731	2
values[94]	56	1			T729	2		T730	2		T731	3
values[95]	57	1			T729	3		T730	2		T731	2
values[96]	47	1			T729	1		T730	2		T731	2
values[97]	52	1			T729	1		T730	2		T731	3
values[98]	52	1			T729	1		T730	2		T731	2
values[99]	57	1			T729	1		T730	2		T731	3
values[100]	68	1			T729	8		T730	2		T731	4
values[101]	58	1			T729	1		T730	2		T731	6
values[102]	65	1			T729	3		T730	2		T731	8
values[103]	69	1			T729	3		T730	2		T731	4
values[104]	66	1			T729	4		T730	2		T731	7
values[105]	69	1			T729	4		T730	2		T731	4
values[106]	58	1			T729	1		T730	3		T731	5
values[107]	86	1			T729	4		T730	2		T731	4
values[108]	82	1			T729	1		T730	2		T731	5
values[109]	78	1			T729	2		T730	2		T731	4
values[110]	70	1			T729	2		T730	2		T731	3
values[111]	77	1			T729	3		T730	2		T731	4
values[112]	74	1			T729	2		T730	2		T731	6
values[113]	68	1			T729	2		T730	2		T731	4
values[114]	73	1			T729	3		T730	3		T731	6
values[115]	75	1			T729	5		T730	4		T731	4
values[116]	69	1			T729	2		T730	2		T731	10
values[117]	90	1			T729	4		T730	5		T731	11
values[118]	70	1			T729	2		T730	3		T731	6
values[119]	83	1			T729	2		T730	3		T731	12
values[120]	72	1			T729	1		T730	8		T731	2
values[121]	80	1			T729	2		T730	6		T731	5
values[122]	76	1			T729	1		T730	4		T731	4
values[123]	101	1			T729	1		T730	5		T731	2
values[124]	142	1			T729	2		T730	4		T731	5
values[125]	241	1			T729	1		T730	6		T731	4
values[126]	535	1			T729	25		T730	25		T731	24
values[127]	2387	1			T729	100		T730	212		T731	219
values[128]	4240	1			T729	177		T730	389		T731	443

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141645	1			T62	70		T63	16		T64	15
values[2]	10485	1			T242	1		T493	1		T488	1
values[3]	4515	1			T388	1		T554	2		T389	41
values[4]	2552	1			T554	1		T389	21		T403	11
values[5]	1581	1			T389	19		T403	6		T732	3
values[6]	1116	1			T389	10		T403	10		T732	12
values[7]	777	1			T389	10		T403	3		T732	5
values[8]	630	1			T389	11		T403	19		T732	5
values[9]	530	1			T389	7		T403	7		T732	8
values[10]	435	1			T403	4		T732	8		T405	20
values[11]	423	1			T403	3		T732	3		T405	19
values[12]	375	1			T403	9		T732	8		T405	18
values[13]	332	1			T403	6		T732	4		T405	11
values[14]	314	1			T403	7		T732	4		T405	8
values[15]	320	1			T403	9		T732	11		T405	7
values[16]	352	1			T403	11		T732	7		T405	5
values[17]	302	1			T403	5		T732	6		T405	9
values[18]	252	1			T403	7		T732	6		T405	12
values[19]	314	1			T403	4		T732	18		T405	17
values[20]	297	1			T403	5		T732	5		T405	11
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values[29]	269	1			T403	4		T732	4		T405	6
values[30]	278	1			T403	6		T732	5		T405	2
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values[70]	98	1			T405	5		T525	1		T441	7
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values[98]	39	1			T525	1		T734	1		T729	2
values[99]	23	1			T525	1		T734	1		T729	2
values[100]	25	1			T525	2		T734	1		T729	2
values[101]	42	1			T525	2		T734	1		T729	2
values[102]	34	1			T525	2		T734	1		T729	2
values[103]	33	1			T525	5		T734	1		T729	2
values[104]	38	1			T525	1		T734	1		T729	3
values[105]	37	1			T525	1		T734	1		T729	8
values[106]	41	1			T525	2		T734	1		T729	8
values[107]	39	1			T525	1		T734	1		T729	8
values[108]	27	1			T525	1		T734	1		T729	4
values[109]	35	1			T525	1		T734	1		T729	6
values[110]	37	1			T525	4		T734	1		T729	5
values[111]	39	1			T525	1		T734	1		T729	2
values[112]	40	1			T525	2		T734	1		T729	3
values[113]	35	1			T525	4		T734	1		T729	3
values[114]	26	1			T525	2		T734	1		T729	6
values[115]	41	1			T525	2		T734	1		T729	7
values[116]	36	1			T525	2		T734	1		T729	5
values[117]	37	1			T525	2		T734	2		T729	5
values[118]	40	1			T525	3		T734	1		T729	3
values[119]	53	1			T525	1		T734	1		T729	14
values[120]	37	1			T525	1		T734	1		T729	8
values[121]	28	1			T525	1		T734	2		T729	3
values[122]	30	1			T525	1		T734	1		T729	4
values[123]	39	1			T525	1		T734	2		T729	3
values[124]	48	1			T525	2		T734	3		T729	5
values[125]	52	1			T525	3		T734	5		T729	3
values[126]	70	1			T525	1		T734	2		T729	3
values[127]	581	1			T525	25		T734	36		T729	68
values[128]	5442	1			T525	249		T734	404		T729	617