Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143071	1			T62	75		T63	19		T64	6
values[2]	11777	1			T62	2		T63	2		T242	1
values[3]	5072	1			T240	89		T480	8		T388	1
values[4]	3086	1			T240	42		T480	5		T401	13
values[5]	2056	1			T240	30		T480	7		T401	4
values[6]	1429	1			T240	16		T480	6		T401	9
values[7]	895	1			T240	12		T480	3		T401	13
values[8]	627	1			T240	16		T480	9		T401	18
values[9]	497	1			T240	2		T480	3		T401	7
values[10]	492	1			T480	6		T401	11		T587	4
values[11]	532	1			T480	12		T401	8		T587	3
values[12]	370	1			T480	8		T401	8		T587	17
values[13]	311	1			T480	11		T401	3		T587	7
values[14]	292	1			T480	6		T401	8		T587	5
values[15]	308	1			T480	6		T401	9		T587	5
values[16]	355	1			T480	15		T401	4		T587	3
values[17]	319	1			T480	8		T401	13		T587	6
values[18]	311	1			T480	7		T401	4		T587	8
values[19]	318	1			T480	4		T401	11		T587	14
values[20]	372	1			T480	10		T401	14		T587	3
values[21]	355	1			T480	10		T401	5		T587	7
values[22]	353	1			T480	2		T401	5		T587	3
values[23]	316	1			T480	9		T401	4		T587	5
values[24]	311	1			T480	4		T401	3		T587	12
values[25]	348	1			T480	15		T401	2		T587	19
values[26]	265	1			T480	3		T401	9		T587	4
values[27]	311	1			T480	5		T401	6		T587	9
values[28]	307	1			T480	5		T401	7		T587	4
values[29]	288	1			T480	4		T401	15		T587	5
values[30]	300	1			T480	3		T401	9		T587	3
values[31]	298	1			T480	10		T401	3		T587	4
values[32]	292	1			T480	18		T401	6		T587	8
values[33]	311	1			T480	14		T401	8		T587	4
values[34]	390	1			T480	3		T401	12		T587	3
values[35]	298	1			T480	3		T401	5		T587	3
values[36]	290	1			T480	5		T401	3		T587	9
values[37]	327	1			T480	11		T401	9		T587	10
values[38]	333	1			T480	8		T401	4		T587	20
values[39]	279	1			T480	6		T401	7		T587	13
values[40]	261	1			T480	15		T401	3		T587	5
values[41]	306	1			T480	6		T401	7		T587	11
values[42]	262	1			T480	6		T401	5		T587	6
values[43]	287	1			T480	7		T401	4		T587	3
values[44]	288	1			T480	2		T401	13		T587	16
values[45]	239	1			T480	6		T401	20		T587	4
values[46]	282	1			T480	5		T401	7		T587	5
values[47]	313	1			T480	5		T401	12		T587	6
values[48]	269	1			T480	5		T401	10		T587	6
values[49]	241	1			T480	11		T401	5		T587	8
values[50]	270	1			T480	10		T401	3		T587	13
values[51]	294	1			T480	7		T401	3		T587	5
values[52]	296	1			T480	20		T401	6		T587	15
values[53]	287	1			T480	5		T401	10		T587	13
values[54]	263	1			T480	3		T401	9		T587	7
values[55]	246	1			T480	13		T401	4		T587	7
values[56]	214	1			T480	8		T401	8		T587	2
values[57]	238	1			T480	8		T401	5		T428	10
values[58]	203	1			T480	8		T401	9		T428	4
values[59]	219	1			T480	4		T401	3		T428	11
values[60]	271	1			T480	5		T401	6		T428	7
values[61]	176	1			T480	2		T401	6		T428	5
values[62]	205	1			T480	5		T401	3		T428	5
values[63]	163	1			T480	5		T401	5		T428	4
values[64]	158	1			T480	8		T401	8		T428	5
values[65]	161	1			T480	4		T401	10		T428	11
values[66]	179	1			T480	3		T401	12		T428	15
values[67]	200	1			T480	5		T428	13		T761	1
values[68]	190	1			T480	8		T761	1		T752	1
values[69]	167	1			T480	7		T761	1		T752	1
values[70]	153	1			T480	6		T761	1		T752	1
values[71]	133	1			T480	7		T761	1		T752	1
values[72]	120	1			T480	3		T761	1		T752	1
values[73]	111	1			T480	4		T761	1		T752	1
values[74]	145	1			T480	16		T761	1		T752	1
values[75]	104	1			T480	13		T761	1		T752	1
values[76]	84	1			T761	1		T752	1		T730	1
values[77]	105	1			T761	1		T752	1		T730	1
values[78]	89	1			T761	1		T752	1		T730	1
values[79]	92	1			T761	1		T752	1		T730	1
values[80]	64	1			T761	1		T752	1		T730	1
values[81]	58	1			T761	1		T752	1		T730	1
values[82]	72	1			T761	1		T752	1		T730	1
values[83]	73	1			T761	1		T752	1		T730	1
values[84]	89	1			T761	1		T752	1		T730	1
values[85]	100	1			T761	1		T752	1		T730	1
values[86]	82	1			T761	1		T752	1		T730	1
values[87]	101	1			T761	1		T752	1		T730	1
values[88]	117	1			T761	1		T752	1		T730	1
values[89]	82	1			T761	1		T752	1		T730	2
values[90]	62	1			T761	1		T752	1		T730	1
values[91]	74	1			T761	1		T752	1		T730	1
values[92]	79	1			T761	1		T752	1		T730	1
values[93]	80	1			T761	1		T752	1		T730	1
values[94]	82	1			T761	1		T752	1		T730	1
values[95]	69	1			T761	1		T752	1		T730	1
values[96]	65	1			T761	2		T752	2		T730	1
values[97]	68	1			T761	1		T752	1		T730	1
values[98]	75	1			T761	2		T752	2		T730	1
values[99]	89	1			T761	1		T752	1		T730	1
values[100]	78	1			T761	4		T752	5		T730	1
values[101]	69	1			T761	2		T752	3		T730	1
values[102]	69	1			T761	1		T752	1		T730	1
values[103]	67	1			T761	1		T752	2		T730	1
values[104]	60	1			T761	4		T752	2		T730	1
values[105]	64	1			T761	1		T752	1		T730	1
values[106]	57	1			T761	2		T752	2		T730	1
values[107]	67	1			T761	3		T752	8		T730	1
values[108]	57	1			T761	2		T752	2		T730	1
values[109]	65	1			T761	3		T752	1		T730	1
values[110]	59	1			T761	2		T752	2		T730	1
values[111]	64	1			T761	1		T752	5		T730	1
values[112]	58	1			T761	1		T752	1		T730	1
values[113]	56	1			T761	3		T752	1		T730	1
values[114]	52	1			T761	1		T752	1		T730	1
values[115]	48	1			T761	1		T752	5		T730	1
values[116]	41	1			T761	1		T752	2		T730	1
values[117]	53	1			T761	1		T752	3		T730	1
values[118]	59	1			T761	1		T752	3		T730	1
values[119]	64	1			T761	1		T752	1		T730	1
values[120]	55	1			T761	1		T752	2		T730	2
values[121]	55	1			T761	1		T752	1		T730	2
values[122]	41	1			T761	1		T752	1		T730	1
values[123]	52	1			T761	1		T752	1		T730	2
values[124]	62	1			T761	4		T752	1		T730	3
values[125]	66	1			T761	1		T752	1		T730	2
values[126]	121	1			T761	3		T752	1		T730	4
values[127]	701	1			T761	32		T752	18		T730	39
values[128]	5120	1			T761	374		T752	295		T730	294