Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	133664	1			T62	66		T63	18		T64	16
values[2]	7632	1			T62	1		T63	2		T242	1
values[3]	2864	1			T240	32		T479	82		T480	7
values[4]	1723	1			T240	32		T479	50		T403	13
values[5]	1113	1			T240	25		T479	31		T403	8
values[6]	778	1			T240	28		T479	18		T403	7
values[7]	583	1			T240	17		T479	8		T403	5
values[8]	522	1			T240	6		T479	4		T403	19
values[9]	427	1			T240	8		T403	8		T411	12
values[10]	362	1			T240	10		T403	3		T411	38
values[11]	313	1			T240	3		T403	5		T411	10
values[12]	359	1			T240	7		T403	12		T411	1
values[13]	309	1			T403	8		T762	1		T760	1
values[14]	336	1			T403	10		T762	1		T760	1
values[15]	337	1			T403	7		T762	1		T760	1
values[16]	335	1			T403	12		T762	1		T760	1
values[17]	328	1			T403	5		T762	1		T760	1
values[18]	281	1			T403	8		T762	1		T760	1
values[19]	286	1			T403	8		T762	1		T760	1
values[20]	288	1			T403	7		T762	1		T760	1
values[21]	235	1			T403	11		T762	1		T760	1
values[22]	225	1			T403	13		T762	1		T760	1
values[23]	327	1			T403	4		T762	1		T760	1
values[24]	323	1			T403	6		T762	1		T760	1
values[25]	351	1			T403	15		T762	1		T760	1
values[26]	398	1			T403	3		T762	1		T760	1
values[27]	270	1			T403	3		T762	1		T760	1
values[28]	291	1			T403	3		T762	1		T760	1
values[29]	320	1			T403	8		T762	1		T760	1
values[30]	314	1			T403	5		T762	1		T760	1
values[31]	284	1			T403	4		T762	1		T760	1
values[32]	314	1			T403	18		T762	1		T760	1
values[33]	300	1			T403	4		T762	1		T760	1
values[34]	343	1			T403	3		T762	1		T760	1
values[35]	302	1			T403	9		T762	1		T760	1
values[36]	301	1			T403	6		T762	1		T760	1
values[37]	286	1			T403	11		T762	1		T760	1
values[38]	268	1			T403	5		T762	1		T760	1
values[39]	338	1			T403	4		T762	1		T760	1
values[40]	242	1			T403	10		T762	1		T760	1
values[41]	252	1			T403	9		T762	1		T760	1
values[42]	277	1			T403	9		T762	1		T760	1
values[43]	231	1			T403	8		T762	1		T760	1
values[44]	270	1			T403	5		T762	1		T760	1
values[45]	256	1			T403	11		T762	1		T760	1
values[46]	287	1			T403	9		T762	1		T760	1
values[47]	215	1			T403	4		T762	1		T760	1
values[48]	269	1			T403	4		T762	1		T760	1
values[49]	263	1			T403	4		T762	1		T760	1
values[50]	218	1			T403	4		T762	1		T760	1
values[51]	240	1			T403	23		T762	1		T760	1
values[52]	193	1			T403	8		T762	1		T760	1
values[53]	223	1			T403	4		T762	1		T760	1
values[54]	214	1			T403	13		T762	1		T760	1
values[55]	219	1			T403	18		T762	1		T760	1
values[56]	209	1			T403	3		T762	1		T760	1
values[57]	187	1			T762	1		T760	1		T763	4
values[58]	179	1			T762	1		T760	1		T764	1
values[59]	162	1			T762	1		T760	1		T764	1
values[60]	125	1			T762	1		T760	1		T764	1
values[61]	146	1			T762	1		T760	1		T764	1
values[62]	126	1			T762	1		T760	1		T764	1
values[63]	116	1			T762	1		T760	1		T764	1
values[64]	156	1			T762	1		T760	1		T764	1
values[65]	93	1			T762	1		T760	1		T764	1
values[66]	93	1			T762	1		T760	1		T764	1
values[67]	63	1			T762	1		T760	1		T764	1
values[68]	61	1			T762	1		T760	1		T764	1
values[69]	40	1			T762	1		T760	1		T764	1
values[70]	46	1			T762	1		T760	1		T764	1
values[71]	51	1			T762	1		T760	1		T764	1
values[72]	50	1			T762	1		T760	1		T764	1
values[73]	50	1			T762	1		T760	2		T764	1
values[74]	53	1			T762	1		T760	1		T764	1
values[75]	40	1			T762	1		T760	1		T764	1
values[76]	51	1			T762	1		T760	1		T764	1
values[77]	47	1			T762	1		T760	1		T764	1
values[78]	41	1			T762	1		T760	1		T764	1
values[79]	44	1			T762	1		T760	1		T764	1
values[80]	30	1			T762	1		T760	1		T764	1
values[81]	34	1			T762	1		T760	1		T764	1
values[82]	32	1			T762	1		T760	1		T764	2
values[83]	30	1			T762	1		T760	1		T764	1
values[84]	26	1			T762	1		T760	1		T764	1
values[85]	36	1			T762	1		T760	1		T764	4
values[86]	26	1			T762	1		T760	1		T764	1
values[87]	29	1			T762	1		T760	1		T764	1
values[88]	39	1			T762	2		T760	1		T764	2
values[89]	45	1			T762	2		T760	3		T764	4
values[90]	36	1			T762	2		T760	5		T764	2
values[91]	52	1			T762	1		T760	2		T764	3
values[92]	47	1			T762	1		T760	5		T764	6
values[93]	37	1			T762	2		T760	1		T764	2
values[94]	37	1			T762	3		T760	2		T764	3
values[95]	38	1			T762	1		T760	1		T764	3
values[96]	43	1			T762	2		T760	2		T764	4
values[97]	57	1			T762	2		T760	6		T764	9
values[98]	48	1			T762	6		T760	4		T764	1
values[99]	29	1			T762	2		T760	1		T764	2
values[100]	30	1			T762	2		T760	1		T764	2
values[101]	31	1			T762	3		T760	2		T764	3
values[102]	44	1			T762	3		T760	1		T764	1
values[103]	41	1			T762	3		T760	4		T764	2
values[104]	42	1			T762	7		T760	2		T764	1
values[105]	44	1			T762	3		T760	2		T764	3
values[106]	37	1			T762	1		T760	4		T764	3
values[107]	30	1			T762	2		T760	2		T764	6
values[108]	37	1			T762	1		T760	2		T764	3
values[109]	39	1			T762	1		T760	4		T764	2
values[110]	33	1			T762	3		T760	2		T764	3
values[111]	34	1			T762	3		T760	1		T764	3
values[112]	37	1			T762	1		T760	3		T764	3
values[113]	30	1			T762	2		T760	2		T764	2
values[114]	32	1			T762	2		T760	4		T764	1
values[115]	42	1			T762	8		T760	2		T764	1
values[116]	35	1			T762	3		T760	1		T764	1
values[117]	35	1			T762	4		T760	1		T764	3
values[118]	31	1			T762	3		T760	3		T764	2
values[119]	41	1			T762	2		T760	2		T764	1
values[120]	33	1			T762	4		T760	1		T764	3
values[121]	39	1			T762	1		T760	5		T764	2
values[122]	54	1			T762	3		T760	8		T764	3
values[123]	53	1			T762	1		T760	4		T764	4
values[124]	44	1			T762	1		T760	2		T764	5
values[125]	48	1			T762	3		T760	2		T764	1
values[126]	66	1			T762	2		T760	1		T764	2
values[127]	474	1			T762	24		T760	26		T764	16
values[128]	4481	1			T762	254		T760	316		T764	253