Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141272	1			T62	55		T63	12		T64	18
values[2]	10037	1			T240	54		T241	1		T485	1
values[3]	3773	1			T240	47		T479	109		T401	3
values[4]	2219	1			T240	35		T479	36		T401	6
values[5]	1378	1			T240	23		T479	24		T401	8
values[6]	869	1			T240	34		T479	12		T401	5
values[7]	648	1			T240	13		T479	7		T401	4
values[8]	566	1			T240	31		T479	4		T401	13
values[9]	489	1			T240	22		T401	6		T492	13
values[10]	358	1			T240	13		T401	3		T492	7
values[11]	415	1			T240	21		T401	15		T492	4
values[12]	358	1			T240	27		T401	19		T492	7
values[13]	385	1			T240	26		T401	6		T492	10
values[14]	406	1			T240	26		T401	6		T492	6
values[15]	387	1			T240	28		T401	5		T492	6
values[16]	370	1			T240	26		T401	6		T492	10
values[17]	344	1			T240	16		T401	10		T492	11
values[18]	333	1			T240	9		T401	5		T492	5
values[19]	359	1			T240	10		T401	5		T492	4
values[20]	360	1			T240	8		T401	5		T492	9
values[21]	362	1			T240	4		T401	9		T492	14
values[22]	403	1			T240	1		T401	8		T492	6
values[23]	379	1			T401	5		T492	15		T738	1
values[24]	351	1			T401	5		T492	11		T738	1
values[25]	316	1			T401	4		T492	4		T738	1
values[26]	362	1			T401	11		T492	4		T738	1
values[27]	290	1			T401	3		T492	4		T738	1
values[28]	350	1			T401	10		T492	3		T738	1
values[29]	321	1			T401	4		T492	3		T738	1
values[30]	327	1			T401	9		T492	5		T738	1
values[31]	362	1			T401	10		T492	3		T738	1
values[32]	346	1			T401	7		T492	7		T738	1
values[33]	358	1			T401	11		T492	8		T738	1
values[34]	337	1			T401	7		T492	6		T738	1
values[35]	317	1			T401	4		T492	9		T738	1
values[36]	311	1			T401	4		T492	11		T738	1
values[37]	363	1			T401	16		T492	9		T738	1
values[38]	276	1			T401	3		T492	3		T738	1
values[39]	333	1			T492	16		T738	1		T406	4
values[40]	357	1			T492	3		T738	1		T406	5
values[41]	321	1			T492	3		T738	1		T406	6
values[42]	348	1			T492	8		T738	1		T406	5
values[43]	340	1			T492	5		T738	1		T406	6
values[44]	329	1			T492	4		T738	1		T406	6
values[45]	320	1			T492	9		T738	1		T406	12
values[46]	285	1			T492	9		T738	1		T406	5
values[47]	254	1			T492	3		T738	1		T406	7
values[48]	297	1			T492	8		T738	1		T406	3
values[49]	295	1			T492	7		T738	1		T406	8
values[50]	283	1			T492	3		T738	1		T406	7
values[51]	298	1			T492	12		T738	1		T406	6
values[52]	268	1			T492	3		T738	1		T406	9
values[53]	314	1			T492	1		T738	1		T406	15
values[54]	260	1			T738	1		T406	10		T735	1
values[55]	250	1			T738	1		T406	5		T735	4
values[56]	262	1			T738	1		T406	12		T735	3
values[57]	189	1			T738	1		T406	14		T735	4
values[58]	190	1			T738	1		T406	13		T735	7
values[59]	208	1			T738	1		T406	7		T735	2
values[60]	184	1			T738	1		T406	6		T735	2
values[61]	185	1			T738	1		T406	7		T735	2
values[62]	164	1			T738	1		T406	9		T735	1
values[63]	177	1			T738	1		T406	15		T735	4
values[64]	174	1			T738	1		T406	10		T735	1
values[65]	154	1			T738	1		T406	8		T735	5
values[66]	137	1			T738	1		T406	1		T735	5
values[67]	141	1			T738	1		T735	4		T417	7
values[68]	152	1			T738	1		T735	4		T417	5
values[69]	100	1			T738	1		T735	1		T417	10
values[70]	88	1			T738	1		T735	2		T417	8
values[71]	83	1			T738	1		T735	2		T417	3
values[72]	88	1			T738	1		T735	7		T417	4
values[73]	79	1			T738	1		T735	9		T417	2
values[74]	63	1			T738	1		T735	4		T417	4
values[75]	64	1			T738	1		T735	4		T736	1
values[76]	60	1			T738	1		T735	4		T736	1
values[77]	46	1			T738	1		T735	4		T736	1
values[78]	55	1			T738	1		T735	1		T736	1
values[79]	62	1			T738	1		T735	1		T736	1
values[80]	64	1			T738	1		T735	7		T736	1
values[81]	66	1			T738	1		T735	9		T736	1
values[82]	75	1			T738	1		T735	3		T736	1
values[83]	67	1			T738	1		T735	5		T736	1
values[84]	69	1			T738	1		T735	6		T736	1
values[85]	61	1			T738	1		T735	5		T736	1
values[86]	52	1			T738	1		T735	1		T736	1
values[87]	66	1			T738	1		T735	2		T736	1
values[88]	61	1			T738	1		T735	3		T736	1
values[89]	62	1			T738	1		T735	2		T736	1
values[90]	71	1			T738	1		T735	3		T736	1
values[91]	64	1			T738	1		T735	5		T736	1
values[92]	56	1			T738	1		T735	2		T736	1
values[93]	78	1			T738	1		T735	2		T736	1
values[94]	78	1			T738	1		T735	8		T736	1
values[95]	85	1			T738	1		T735	5		T736	1
values[96]	87	1			T738	1		T735	7		T736	1
values[97]	65	1			T738	1		T735	5		T736	1
values[98]	75	1			T738	1		T735	2		T736	1
values[99]	90	1			T738	1		T735	5		T736	1
values[100]	76	1			T738	1		T735	5		T736	1
values[101]	72	1			T738	1		T735	3		T736	2
values[102]	85	1			T738	1		T735	5		T736	7
values[103]	81	1			T738	2		T735	2		T736	5
values[104]	81	1			T738	1		T735	7		T736	1
values[105]	97	1			T738	1		T735	11		T736	1
values[106]	84	1			T738	1		T735	6		T736	3
values[107]	105	1			T738	1		T735	7		T736	2
values[108]	96	1			T738	1		T735	7		T736	2
values[109]	92	1			T738	1		T735	5		T736	1
values[110]	82	1			T738	1		T735	2		T736	1
values[111]	78	1			T738	1		T735	1		T736	1
values[112]	81	1			T738	1		T735	2		T736	1
values[113]	90	1			T738	1		T735	7		T736	1
values[114]	85	1			T738	1		T735	4		T736	3
values[115]	82	1			T738	1		T735	2		T736	1
values[116]	100	1			T738	1		T735	12		T736	2
values[117]	83	1			T738	1		T735	6		T736	1
values[118]	86	1			T738	1		T735	17		T736	1
values[119]	77	1			T738	1		T735	6		T736	2
values[120]	85	1			T738	1		T735	2		T736	2
values[121]	84	1			T738	1		T735	8		T736	2
values[122]	86	1			T738	3		T735	3		T736	2
values[123]	74	1			T738	1		T735	4		T736	2
values[124]	91	1			T738	2		T735	8		T736	3
values[125]	100	1			T738	3		T736	2		T765	3
values[126]	199	1			T738	5		T736	1		T765	32
values[127]	1090	1			T738	41		T736	37		T765	85
values[128]	9238	1			T738	407		T736	379		T765	38