Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	488	1			T497	1		T401	1		T484	1
all_values[1]	470	1			T479	2		T480	1		T484	1
all_values[2]	426	1			T480	1		T401	1		T484	2
all_values[3]	510	1			T480	2		T401	1		T484	1
all_values[4]	458	1			T240	2		T396	1		T484	1
all_values[5]	469	1			T401	1		T721	4		T389	1
all_values[6]	505	1			T480	1		T484	1		T799	1
all_values[7]	505	1			T240	1		T401	2		T799	1
all_values[8]	479	1			T480	1		T799	1		T492	1
all_values[9]	506	1			T240	1		T396	1		T480	2
all_values[10]	472	1			T240	1		T480	1		T401	2
all_values[11]	489	1			T240	1		T401	1		T799	2
all_values[12]	474	1			T480	1		T799	1		T492	2
all_values[13]	504	1			T480	1		T401	2		T484	2
all_values[14]	481	1			T480	1		T484	2		T799	1
all_values[15]	499	1			T484	3		T799	1		T492	2
all_values[16]	489	1			T479	1		T480	1		T799	1
all_values[17]	480	1			T240	1		T484	2		T492	2
all_values[18]	493	1			T240	1		T479	1		T484	1
all_values[19]	529	1			T497	1		T401	2		T799	2
all_values[20]	450	1			T480	1		T401	1		T484	1
all_values[21]	483	1			T401	4		T799	1		T721	2
all_values[22]	458	1			T401	1		T799	1		T721	2
all_values[23]	453	1			T480	1		T484	2		T799	1
all_values[24]	488	1			T479	1		T799	1		T721	4
all_values[25]	485	1			T479	1		T497	1		T480	2
all_values[26]	478	1			T480	2		T484	2		T721	1
all_values[27]	476	1			T401	3		T799	1		T721	1
all_values[28]	529	1			T497	1		T401	3		T484	2
all_values[29]	499	1			T480	2		T484	2		T799	1
all_values[30]	447	1			T480	1		T484	2		T799	1
all_values[31]	487	1			T240	2		T484	2		T492	2
all_values[32]	496	1			T240	1		T480	1		T799	1
all_values[33]	534	1			T799	1		T389	1		T512	1
all_values[34]	483	1			T240	1		T480	1		T401	1
all_values[35]	502	1			T480	1		T401	1		T484	1
all_values[36]	502	1			T479	1		T401	1		T492	1
all_values[37]	463	1			T240	1		T479	1		T396	1
all_values[38]	468	1			T240	1		T480	3		T401	1
all_values[39]	504	1			T240	1		T480	1		T721	2
all_values[40]	502	1			T479	1		T401	1		T484	2
all_values[41]	472	1			T240	2		T479	1		T497	1
all_values[42]	431	1			T240	1		T479	1		T480	1
all_values[43]	481	1			T721	5		T389	1		T512	1
all_values[44]	489	1			T396	1		T401	1		T484	1
all_values[45]	513	1			T240	1		T479	1		T401	1
all_values[46]	469	1			T497	1		T401	2		T799	1
all_values[47]	470	1			T240	1		T484	1		T799	1
all_values[48]	452	1			T480	1		T799	2		T492	1
all_values[49]	440	1			T479	1		T497	1		T484	2