Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141888	1			T62	88		T63	2		T72	8
values[2]	8845	1			T62	2		T66	2		T234	45
values[3]	3222	1			T66	2		T234	7		T405	13
values[4]	2179	1			T66	3		T234	5		T405	6
values[5]	1628	1			T66	2		T405	4		T787	49
values[6]	1142	1			T66	4		T405	8		T787	30
values[7]	895	1			T66	1		T405	4		T787	18
values[8]	636	1			T66	1		T405	6		T787	34
values[9]	551	1			T66	2		T405	5		T787	26
values[10]	547	1			T66	1		T405	9		T787	29
values[11]	456	1			T66	3		T405	15		T787	13
values[12]	480	1			T66	2		T405	4		T787	1
values[13]	462	1			T66	3		T405	8		T572	4
values[14]	467	1			T66	3		T405	13		T572	5
values[15]	371	1			T66	4		T405	4		T572	13
values[16]	304	1			T66	3		T405	9		T572	3
values[17]	395	1			T66	3		T405	3		T572	3
values[18]	382	1			T66	4		T405	6		T572	5
values[19]	382	1			T66	1		T405	4		T572	10
values[20]	378	1			T66	4		T405	3		T572	13
values[21]	395	1			T66	5		T405	4		T572	4
values[22]	429	1			T66	3		T405	13		T572	6
values[23]	386	1			T66	9		T405	7		T572	6
values[24]	391	1			T66	6		T405	4		T572	8
values[25]	385	1			T66	6		T405	8		T572	5
values[26]	350	1			T66	12		T405	4		T572	5
values[27]	368	1			T66	9		T405	4		T572	10
values[28]	400	1			T66	6		T405	6		T572	24
values[29]	377	1			T66	2		T405	8		T572	13
values[30]	389	1			T66	4		T405	5		T572	6
values[31]	392	1			T66	1		T405	4		T572	6
values[32]	351	1			T66	1		T405	8		T572	3
values[33]	372	1			T66	1		T405	12		T572	4
values[34]	342	1			T66	3		T405	9		T572	4
values[35]	391	1			T66	1		T405	10		T572	4
values[36]	365	1			T66	2		T405	12		T572	8
values[37]	352	1			T66	4		T405	4		T572	23
values[38]	372	1			T66	3		T405	7		T572	18
values[39]	384	1			T66	1		T405	4		T572	14
values[40]	421	1			T66	2		T405	6		T572	5
values[41]	452	1			T66	2		T405	7		T572	9
values[42]	364	1			T66	1		T405	7		T572	7
values[43]	372	1			T66	2		T405	12		T572	4
values[44]	339	1			T66	2		T405	8		T572	3
values[45]	338	1			T66	7		T405	6		T572	7
values[46]	327	1			T66	7		T405	6		T572	6
values[47]	376	1			T66	6		T405	6		T572	2
values[48]	291	1			T66	3		T405	5		T572	8
values[49]	280	1			T66	5		T405	9		T572	3
values[50]	275	1			T66	5		T405	4		T572	14
values[51]	279	1			T66	1		T405	10		T572	11
values[52]	309	1			T66	3		T405	12		T572	7
values[53]	298	1			T66	1		T405	3		T572	7
values[54]	272	1			T66	1		T405	6		T572	6
values[55]	226	1			T66	3		T405	6		T572	5
values[56]	274	1			T66	4		T405	3		T572	8
values[57]	224	1			T66	1		T405	5		T572	7
values[58]	263	1			T66	5		T405	15		T572	4
values[59]	251	1			T66	3		T405	10		T572	7
values[60]	205	1			T66	1		T405	4		T572	4
values[61]	191	1			T66	2		T405	9		T572	6
values[62]	216	1			T66	1		T572	17		T781	2
values[63]	168	1			T66	1		T572	10		T781	2
values[64]	201	1			T66	2		T572	16		T781	2
values[65]	175	1			T66	1		T572	9		T781	2
values[66]	126	1			T66	1		T781	2		T493	1
values[67]	132	1			T66	2		T781	2		T493	1
values[68]	130	1			T66	4		T781	2		T493	1
values[69]	97	1			T66	2		T781	2		T493	1
values[70]	123	1			T66	3		T781	2		T493	1
values[71]	103	1			T66	1		T781	2		T493	1
values[72]	124	1			T66	5		T781	2		T493	1
values[73]	99	1			T66	4		T781	2		T493	2
values[74]	110	1			T66	7		T781	2		T493	1
values[75]	91	1			T66	5		T781	2		T493	1
values[76]	72	1			T66	1		T781	2		T493	1
values[77]	88	1			T66	4		T781	2		T493	1
values[78]	81	1			T66	3		T781	2		T493	1
values[79]	83	1			T66	2		T781	2		T493	1
values[80]	69	1			T66	4		T781	2		T493	1
values[81]	45	1			T66	1		T781	2		T493	1
values[82]	69	1			T66	2		T781	2		T493	1
values[83]	90	1			T66	1		T781	4		T493	1
values[84]	81	1			T66	3		T781	2		T493	1
values[85]	54	1			T66	2		T781	2		T493	1
values[86]	58	1			T66	1		T781	2		T493	1
values[87]	68	1			T66	5		T781	2		T493	1
values[88]	48	1			T66	1		T781	2		T493	1
values[89]	66	1			T66	2		T781	2		T493	1
values[90]	78	1			T66	2		T781	2		T493	1
values[91]	72	1			T66	4		T781	2		T493	2
values[92]	82	1			T66	7		T781	2		T493	9
values[93]	78	1			T66	3		T781	2		T493	3
values[94]	65	1			T66	1		T781	2		T493	5
values[95]	69	1			T66	3		T781	2		T493	4
values[96]	71	1			T66	1		T781	2		T493	3
values[97]	70	1			T66	4		T781	3		T493	3
values[98]	68	1			T66	3		T781	4		T493	2
values[99]	56	1			T66	1		T781	5		T493	2
values[100]	61	1			T66	1		T781	8		T493	2
values[101]	47	1			T781	4		T493	2		T790	2
values[102]	56	1			T781	3		T493	1		T790	3
values[103]	66	1			T781	3		T493	6		T790	4
values[104]	74	1			T781	5		T493	5		T790	10
values[105]	90	1			T781	7		T493	4		T790	9
values[106]	70	1			T781	2		T493	1		T790	1
values[107]	70	1			T781	4		T493	1		T790	1
values[108]	66	1			T781	2		T493	1		T790	1
values[109]	67	1			T781	4		T493	3		T790	1
values[110]	75	1			T781	8		T493	1		T790	6
values[111]	59	1			T781	4		T493	3		T790	5
values[112]	67	1			T781	4		T493	1		T790	2
values[113]	64	1			T781	10		T493	2		T790	2
values[114]	56	1			T781	8		T493	1		T790	5
values[115]	72	1			T781	3		T493	4		T790	2
values[116]	59	1			T781	2		T493	1		T790	2
values[117]	57	1			T781	9		T493	1		T790	4
values[118]	55	1			T781	3		T493	5		T790	1
values[119]	52	1			T781	3		T493	1		T790	1
values[120]	67	1			T781	14		T493	1		T790	2
values[121]	64	1			T781	5		T493	4		T790	1
values[122]	57	1			T781	5		T493	2		T790	2
values[123]	61	1			T781	4		T493	2		T790	2
values[124]	56	1			T781	3		T493	4		T790	1
values[125]	86	1			T781	4		T493	1		T790	1
values[126]	134	1			T781	6		T493	3		T790	1
values[127]	720	1			T781	74		T493	25		T790	28
values[128]	6327	1			T781	607		T493	251		T790	252