Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.54	95.54	94.41	90.99		95.29	97.38	99.60

Total tests in report: 2779

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
41.24	41.24	50.74	50.74	46.89	46.89	25.25	25.25			61.85	61.85	62.59	62.59	0.13	0.13	/workspace/coverage/default/0.chip_sw_gpio.3488280220
51.01	9.76	58.27	7.52	55.62	8.73	31.36	6.11			69.49	7.64	90.37	27.78	0.93	0.80	/workspace/coverage/default/2.chip_jtag_csr_rw.476706831
58.35	7.34	65.26	6.99	62.20	6.58	35.67	4.31			70.68	1.19	90.37	0.00	25.92	24.99	/workspace/coverage/cover_reg_top/28.xbar_stress_all.3387254038
62.68	4.33	74.19	8.93	68.25	6.05	38.42	2.76			78.93	8.25	90.37	0.00	25.92	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.2460906631
66.60	3.92	74.20	0.01	68.27	0.02	61.66	23.24			78.96	0.02	90.56	0.19	25.93	0.01	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1486719387
70.40	3.81	74.20	0.00	68.27	0.00	61.66	0.00			78.96	0.00	90.56	0.00	48.78	22.85	/workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.2587855731
73.13	2.72	74.20	0.00	68.27	0.00	61.66	0.00			78.96	0.00	90.56	0.00	65.12	16.33	/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2509342344
75.51	2.39	79.34	5.14	72.25	3.98	65.12	3.46			80.71	1.76	90.56	0.00	65.12	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1209328858
77.77	2.26	82.08	2.74	78.13	5.89	65.24	0.12			84.87	4.16	90.56	0.00	65.75	0.63	/workspace/coverage/cover_reg_top/11.chip_csr_rw.642495768
79.82	2.05	83.17	1.09	79.06	0.93	74.32	9.08			85.48	0.61	91.11	0.56	65.76	0.01	/workspace/coverage/default/2.rom_e2e_shutdown_output.3946825210
81.41	1.60	83.17	0.00	79.06	0.00	74.32	0.00			85.48	0.00	91.11	0.00	75.34	9.58	/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1981403993
82.66	1.25	85.45	2.28	81.53	2.47	74.78	0.46			87.50	2.02	91.30	0.19	75.40	0.06	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3234194921
83.76	1.10	85.45	0.00	81.68	0.15	74.78	0.00			87.50	0.00	91.30	0.00	81.87	6.47	/workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.950649530
84.71	0.95	87.13	1.68	83.20	1.52	75.51	0.72			89.26	1.76	91.30	0.00	81.87	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3990570729
85.62	0.91	87.13	0.00	83.20	0.00	75.51	0.00			89.26	0.00	91.30	0.00	87.32	5.45	/workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2096161879
86.46	0.84	88.65	1.52	84.88	1.68	75.69	0.18			90.92	1.67	91.30	0.00	87.32	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3495278094
87.26	0.79	89.01	0.36	85.03	0.15	75.71	0.01			91.09	0.16	95.37	4.07	87.32	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.677530555
88.04	0.79	89.69	0.67	85.71	0.67	78.32	2.62			91.66	0.57	95.56	0.19	87.32	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.413677344
88.76	0.72	89.70	0.01	85.92	0.21	79.22	0.90			91.69	0.03	95.56	0.00	90.46	3.14	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3067779725
89.34	0.58	90.32	0.62	86.50	0.58	80.70	1.47			92.46	0.77	95.56	0.00	90.51	0.05	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2521983934
89.84	0.50	90.76	0.44	88.19	1.68	81.11	0.41			92.47	0.01	95.56	0.00	90.94	0.43	/workspace/coverage/cover_reg_top/15.chip_tl_errors.3535125168
90.32	0.49	90.80	0.03	88.19	0.00	83.80	2.70			92.47	0.00	95.74	0.19	90.94	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3408890603
90.71	0.39	90.84	0.04	88.22	0.04	84.31	0.51			92.47	0.00	95.74	0.00	92.69	1.75	/workspace/coverage/default/0.chip_sw_alert_test.4210163719
91.09	0.38	91.74	0.90	88.22	0.00	84.44	0.13			92.47	0.00	95.74	0.00	93.94	1.25	/workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.1974051797
91.47	0.37	91.74	0.00	88.22	0.00	84.44	0.00			92.47	0.00	95.74	0.00	96.17	2.23	/workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1110559565
91.79	0.32	92.17	0.43	88.64	0.41	84.60	0.16			92.86	0.39	96.30	0.56	96.17	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2637589018
92.07	0.28	92.17	0.00	88.64	0.00	84.60	0.00			92.86	0.00	96.30	0.00	97.85	1.68	/workspace/coverage/cover_reg_top/87.xbar_access_same_device.1468398473
92.34	0.27	92.42	0.24	89.26	0.63	84.70	0.10			93.51	0.65	96.30	0.00	97.85	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.4109353312
92.56	0.22	93.25	0.83	89.50	0.24	84.84	0.15			93.63	0.12	96.30	0.00	97.85	0.00	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.725504043
92.76	0.20	93.35	0.10	89.61	0.11	85.50	0.66			93.75	0.12	96.30	0.00	98.04	0.19	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.300988640
92.94	0.18	93.35	0.00	89.61	0.00	86.61	1.10			93.75	0.00	96.30	0.00	98.04	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.571555779
93.09	0.14	93.35	0.00	89.62	0.01	87.46	0.86			93.75	0.00	96.30	0.00	98.04	0.00	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2996479508
93.23	0.14	93.36	0.01	90.01	0.40	87.47	0.01			94.20	0.44	96.30	0.00	98.04	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.4124015573
93.37	0.14	93.65	0.29	90.28	0.27	87.76	0.28			94.20	0.00	96.30	0.00	98.04	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1450529339
93.50	0.13	93.65	0.00	91.08	0.80	87.76	0.00			94.20	0.00	96.30	0.00	98.04	0.00	/workspace/coverage/cover_reg_top/22.chip_tl_errors.96484137
93.62	0.12	93.65	0.00	91.08	0.00	88.45	0.70			94.20	0.00	96.30	0.00	98.04	0.00	/workspace/coverage/default/1.chip_sw_flash_init.1503340052
93.73	0.12	93.82	0.17	91.55	0.47	88.47	0.02			94.22	0.02	96.30	0.00	98.04	0.00	/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1437378025
93.84	0.11	93.82	0.00	91.55	0.00	89.13	0.66			94.22	0.00	96.30	0.00	98.04	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1553212511
93.93	0.08	93.84	0.02	91.63	0.08	89.30	0.17			94.26	0.04	96.48	0.19	98.04	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4174265854
94.00	0.07	93.89	0.05	91.70	0.07	89.45	0.15			94.43	0.17	96.48	0.00	98.04	0.00	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2167383630
94.07	0.07	94.04	0.15	91.74	0.04	89.46	0.01			94.46	0.02	96.67	0.19	98.05	0.01	/workspace/coverage/default/54.chip_sw_all_escalation_resets.639871546
94.14	0.07	94.18	0.14	91.83	0.09	89.54	0.08			94.55	0.10	96.67	0.00	98.05	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2839333244
94.20	0.07	94.18	0.00	92.24	0.41	89.54	0.00			94.55	0.00	96.67	0.00	98.05	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.3396935456
94.27	0.06	94.28	0.10	92.42	0.17	89.55	0.02			94.64	0.08	96.67	0.00	98.05	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.950058641
94.32	0.06	94.28	0.00	92.57	0.16	89.55	0.00			94.82	0.18	96.67	0.00	98.05	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1964359013
94.37	0.05	94.28	0.00	92.65	0.08	89.55	0.00			94.84	0.02	96.67	0.00	98.26	0.21	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3133941922
94.42	0.05	94.33	0.06	92.79	0.14	89.55	0.00			94.92	0.08	96.67	0.00	98.26	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1104513830
94.47	0.05	94.37	0.03	92.85	0.06	89.70	0.15			94.95	0.02	96.67	0.00	98.26	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1544223931
94.51	0.04	94.38	0.01	92.86	0.01	89.70	0.00			94.97	0.02	96.85	0.19	98.27	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2589187041
94.55	0.04	94.41	0.03	92.87	0.01	89.71	0.01			94.98	0.01	97.04	0.19	98.28	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.913369656
94.59	0.04	94.41	0.01	92.88	0.01	89.72	0.02			94.99	0.01	97.22	0.19	98.30	0.01	/workspace/coverage/default/4.chip_sw_all_escalation_resets.3298182267
94.62	0.04	94.41	0.00	92.88	0.00	89.77	0.04			94.99	0.00	97.41	0.19	98.30	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3475922562
94.66	0.04	94.41	0.00	92.88	0.00	89.99	0.22			94.99	0.00	97.41	0.00	98.30	0.00	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2580021450
94.70	0.03	94.51	0.10	92.88	0.00	90.08	0.10			95.00	0.01	97.41	0.00	98.30	0.00	/workspace/coverage/default/3.chip_tap_straps_testunlock0.3600824506
94.73	0.03	94.51	0.00	92.98	0.10	90.08	0.00			95.01	0.02	97.41	0.00	98.37	0.07	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.4179674790
94.76	0.03	94.57	0.06	93.02	0.04	90.13	0.04			95.03	0.02	97.41	0.00	98.38	0.01	/workspace/coverage/default/45.chip_sw_all_escalation_resets.2801831545
94.78	0.03	94.57	0.00	93.02	0.00	90.29	0.17			95.03	0.00	97.41	0.00	98.38	0.00	/workspace/coverage/default/0.chip_sw_flash_init.1856973963
94.81	0.03	94.65	0.07	93.05	0.03	90.31	0.01			95.08	0.05	97.41	0.00	98.38	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2865886889
94.84	0.03	94.65	0.00	93.21	0.16	90.31	0.00			95.08	0.00	97.41	0.00	98.38	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2146779609
94.86	0.03	94.68	0.03	93.26	0.05	90.33	0.03			95.12	0.04	97.41	0.00	98.38	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.764387417
94.89	0.02	94.75	0.07	93.31	0.05	90.33	0.00			95.15	0.03	97.41	0.00	98.38	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2652740254
94.91	0.02	94.76	0.01	93.35	0.04	90.43	0.09			95.16	0.01	97.41	0.00	98.38	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3858736510
94.94	0.02	94.76	0.00	93.38	0.03	90.43	0.00			95.16	0.00	97.41	0.00	98.48	0.11	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.537655278
94.96	0.02	94.76	0.00	93.50	0.12	90.43	0.00			95.16	0.00	97.41	0.00	98.48	0.00	/workspace/coverage/cover_reg_top/25.chip_tl_errors.221696102
94.97	0.02	94.79	0.03	93.54	0.05	90.44	0.01			95.18	0.02	97.41	0.00	98.48	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.670377829
94.99	0.02	94.84	0.05	93.56	0.01	90.45	0.01			95.22	0.03	97.41	0.00	98.48	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1489775437
95.01	0.02	94.85	0.01	93.62	0.06	90.45	0.01			95.25	0.03	97.41	0.00	98.48	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1804646054
95.03	0.02	94.85	0.00	93.68	0.06	90.45	0.00			95.25	0.00	97.41	0.00	98.52	0.04	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2667614304
95.04	0.01	94.85	0.00	93.76	0.09	90.45	0.00			95.25	0.00	97.41	0.00	98.52	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.101672659
95.05	0.01	94.85	0.00	93.83	0.07	90.45	0.00			95.27	0.02	97.41	0.00	98.52	0.00	/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1029384818
95.07	0.01	94.85	0.00	93.83	0.00	90.53	0.08			95.27	0.00	97.41	0.00	98.52	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1919211329
95.08	0.01	94.85	0.00	93.83	0.00	90.53	0.00			95.27	0.00	97.41	0.00	98.59	0.07	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.3874854440
95.09	0.01	94.85	0.00	93.83	0.00	90.59	0.07			95.27	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.328407150
95.10	0.01	94.85	0.00	93.89	0.06	90.59	0.00			95.27	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.3895337963
95.11	0.01	94.85	0.00	93.95	0.06	90.59	0.00			95.27	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.125756913
95.12	0.01	94.85	0.00	93.95	0.00	90.65	0.06			95.27	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1334576567
95.13	0.01	94.87	0.02	93.96	0.01	90.68	0.03			95.27	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_power_sleep_load.2039419837
95.14	0.01	94.89	0.02	93.96	0.01	90.68	0.01			95.28	0.02	97.41	0.00	98.59	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3899784351
95.15	0.01	94.89	0.00	93.99	0.03	90.70	0.02			95.28	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1184536315
95.15	0.01	94.91	0.01	94.00	0.01	90.74	0.03			95.28	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3628212064
95.16	0.01	94.91	0.00	94.00	0.01	90.74	0.00			95.28	0.00	97.41	0.00	98.63	0.04	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1721773012
95.17	0.01	94.91	0.00	94.03	0.03	90.74	0.00			95.28	0.00	97.41	0.00	98.64	0.01	/workspace/coverage/cover_reg_top/2.chip_tl_errors.3926133658
95.17	0.01	94.91	0.00	94.07	0.04	90.74	0.00			95.28	0.00	97.41	0.00	98.64	0.00	/workspace/coverage/cover_reg_top/19.xbar_access_same_device.13959053
95.18	0.01	94.91	0.00	94.10	0.04	90.74	0.00			95.28	0.00	97.41	0.00	98.64	0.00	/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.754408914
95.18	0.01	94.91	0.01	94.12	0.02	90.75	0.01			95.28	0.00	97.41	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.336124933
95.19	0.01	94.91	0.00	94.12	0.00	90.75	0.00			95.28	0.00	97.41	0.00	98.67	0.04	/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.270186246
95.20	0.01	94.91	0.00	94.12	0.00	90.75	0.00			95.28	0.00	97.41	0.00	98.71	0.04	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.323714068
95.20	0.01	94.91	0.00	94.12	0.00	90.78	0.04			95.28	0.00	97.41	0.00	98.71	0.00	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.620647144
95.21	0.01	94.91	0.00	94.12	0.01	90.80	0.02			95.28	0.00	97.41	0.00	98.72	0.01	/workspace/coverage/default/85.chip_sw_all_escalation_resets.2440224397
95.21	0.01	94.91	0.00	94.14	0.02	90.80	0.00			95.28	0.00	97.41	0.00	98.73	0.01	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3159967747
95.22	0.01	94.91	0.00	94.17	0.03	90.80	0.00			95.28	0.00	97.41	0.00	98.73	0.00	/workspace/coverage/cover_reg_top/94.xbar_stress_all.4227989163
95.22	0.01	94.91	0.00	94.17	0.00	90.83	0.03			95.28	0.00	97.41	0.00	98.73	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3529926688
95.23	0.01	94.91	0.00	94.17	0.01	90.83	0.00			95.28	0.00	97.41	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3807127745
95.23	0.01	94.91	0.00	94.20	0.02	90.83	0.00			95.28	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3343121614
95.23	0.01	94.92	0.01	94.21	0.01	90.83	0.01			95.28	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.1767355230
95.24	0.01	94.94	0.01	94.21	0.00	90.84	0.01			95.28	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3380834665
95.24	0.01	94.94	0.00	94.23	0.02	90.84	0.00			95.28	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/cover_reg_top/75.xbar_stress_all.1814229851
95.25	0.01	94.94	0.00	94.25	0.02	90.84	0.00			95.28	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1697858517
95.25	0.01	94.94	0.00	94.26	0.01	90.84	0.00			95.28	0.00	97.41	0.00	98.77	0.01	/workspace/coverage/cover_reg_top/20.chip_tl_errors.695832444
95.25	0.01	94.94	0.00	94.26	0.00	90.86	0.02			95.28	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1598661207
95.25	0.01	94.94	0.00	94.27	0.02	90.86	0.00			95.28	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/13.xbar_access_same_device.4023367035
95.26	0.01	94.94	0.00	94.29	0.02	90.86	0.00			95.28	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/1.chip_sw_gpio.1110065365
95.26	0.01	94.94	0.00	94.29	0.00	90.88	0.02			95.28	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.2724173163
95.26	0.01	94.94	0.00	94.29	0.00	90.89	0.02			95.28	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1962693351
95.27	0.01	94.94	0.00	94.30	0.01	90.89	0.00			95.28	0.00	97.41	0.00	98.78	0.01	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.2946734419
95.27	0.01	94.94	0.00	94.30	0.01	90.89	0.00			95.28	0.00	97.41	0.00	98.79	0.01	/workspace/coverage/default/33.chip_sw_all_escalation_resets.2838875376
95.27	0.01	94.94	0.00	94.30	0.01	90.91	0.01			95.28	0.00	97.41	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3404280436
95.27	0.01	94.94	0.00	94.32	0.01	90.91	0.00			95.28	0.00	97.41	0.00	98.79	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.638298569
95.28	0.01	94.94	0.00	94.32	0.00	90.91	0.01			95.28	0.00	97.41	0.00	98.80	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.929649623
95.28	0.01	94.94	0.00	94.32	0.00	90.91	0.01			95.28	0.00	97.41	0.00	98.81	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2226172017
95.28	0.01	94.94	0.00	94.32	0.00	90.92	0.01			95.28	0.00	97.41	0.00	98.81	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.2934789754
95.28	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.83	0.01	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1430357184
95.28	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.84	0.01	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1796112023
95.29	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.85	0.01	/workspace/coverage/cover_reg_top/14.chip_tl_errors.3974137011
95.29	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.86	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.85655764
95.29	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.87	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.743713851
95.29	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.88	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2224076540
95.29	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.90	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1930463521
95.30	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.91	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1056272626
95.30	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.92	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3617133888
95.30	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.93	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2371440095
95.30	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.94	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3564486524
95.30	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.95	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.4138682241
95.31	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.97	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1004522315
95.31	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.98	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.572326106
95.31	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	98.99	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2469427165
95.31	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.00	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1206446975
95.31	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.01	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2717202741
95.32	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.02	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2374828436
95.32	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.04	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1849631986
95.32	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.05	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.696379545
95.32	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.06	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.859826887
95.32	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.07	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.2924900251
95.33	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.08	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4174610956
95.33	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.10	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.4050901769
95.33	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.11	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2113560087
95.33	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.12	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.4083542950
95.33	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.13	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1879878309
95.34	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.14	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3577119036
95.34	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.15	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2032550485
95.34	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.17	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.3944255065
95.34	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.18	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2336194121
95.34	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.19	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.127425374
95.34	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.20	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3103021708
95.35	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.21	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.2798946661
95.35	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.22	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3964001441
95.35	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.24	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1152212626
95.35	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.25	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.2948497996
95.35	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.26	0.01	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1748583307
95.36	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.27	0.01	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.831495185
95.36	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.28	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.4157577761
95.36	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.30	0.01	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630141456
95.36	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.31	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.918584147
95.36	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.32	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.792788490
95.37	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.33	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.277189148
95.37	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.34	0.01	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3958439829
95.37	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.35	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.916686069
95.37	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.37	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.1425130199
95.37	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.38	0.01	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.778549111
95.38	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.39	0.01	/workspace/coverage/default/44.chip_sw_all_escalation_resets.1383251032
95.38	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.40	0.01	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.897376692
95.38	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.41	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.751740013
95.38	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.42	0.01	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2698736073
95.38	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.44	0.01	/workspace/coverage/default/5.chip_sw_all_escalation_resets.3680159592
95.39	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.45	0.01	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2997478375
95.39	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.46	0.01	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.4240646314
95.39	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.47	0.01	/workspace/coverage/default/58.chip_sw_all_escalation_resets.4200984773
95.39	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.48	0.01	/workspace/coverage/default/61.chip_sw_all_escalation_resets.1403637015
95.39	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/73.chip_sw_all_escalation_resets.50105830
95.40	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2543632575
95.40	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2390420138
95.40	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/80.chip_sw_all_escalation_resets.262411712
95.40	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.54	0.01	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2540564553
95.40	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.55	0.01	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1081619740
95.41	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.57	0.01	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2544265892
95.41	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.58	0.01	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3576840382
95.41	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.59	0.01	/workspace/coverage/default/95.chip_sw_all_escalation_resets.1496791933
95.41	0.01	94.94	0.00	94.32	0.00	90.92	0.00			95.28	0.00	97.41	0.00	99.60	0.01	/workspace/coverage/default/97.chip_sw_all_escalation_resets.3851353896
95.41	0.01	94.94	0.01	94.32	0.00	90.93	0.01			95.28	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3740401797
95.42	0.01	94.94	0.00	94.33	0.01	90.93	0.00			95.28	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2734751558
95.42	0.01	94.94	0.00	94.34	0.01	90.93	0.00			95.28	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3088908563
95.42	0.01	94.94	0.00	94.35	0.01	90.93	0.00			95.28	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.3434762086
95.42	0.01	94.94	0.01	94.35	0.00	90.94	0.01			95.28	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/23.chip_sw_all_escalation_resets.1018328345
95.42	0.01	94.94	0.00	94.35	0.00	90.95	0.01			95.28	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3972324256
95.42	0.01	94.94	0.00	94.35	0.00	90.96	0.01			95.28	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/2.chip_sw_flash_init.1640223613
95.43	0.01	94.94	0.00	94.35	0.01	90.96	0.01			95.28	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2553305708
95.43	0.01	94.94	0.00	94.35	0.00	90.96	0.00			95.29	0.01	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2093186721
95.43	0.01	94.94	0.00	94.36	0.01	90.96	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1278699582
95.43	0.01	94.94	0.00	94.37	0.01	90.96	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.3646124391
95.43	0.01	94.94	0.00	94.37	0.01	90.96	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.377519416
95.43	0.01	94.94	0.00	94.37	0.00	90.97	0.01			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3430581556
95.43	0.01	94.94	0.00	94.37	0.00	90.98	0.01			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_kmac_entropy.1741661963
95.43	0.01	94.95	0.01	94.37	0.00	90.98	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3441370057
95.43	0.01	94.96	0.01	94.37	0.00	90.98	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.3227117502
95.44	0.01	94.96	0.00	94.37	0.00	90.98	0.01			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.981785732
95.44	0.01	94.96	0.00	94.38	0.01	90.98	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.3310934677
95.44	0.01	94.96	0.00	94.38	0.01	90.98	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.4127035303
95.44	0.01	94.96	0.00	94.38	0.01	90.98	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.1229791047
95.44	0.01	94.96	0.00	94.39	0.01	90.98	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3262063207
95.44	0.01	94.96	0.00	94.39	0.01	90.98	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_irq.658822874
95.44	0.01	94.96	0.00	94.40	0.01	90.98	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2680384712
95.44	0.01	94.96	0.00	94.40	0.01	90.98	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.619084311
95.44	0.01	94.96	0.00	94.40	0.01	90.98	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_spi_device_tpm.3900488427
95.44	0.01	94.96	0.00	94.41	0.01	90.98	0.00			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3076222821
95.44	0.01	94.96	0.00	94.41	0.00	90.99	0.01			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/1.chip_tap_straps_testunlock0.1876923986
95.44	0.01	94.96	0.00	94.41	0.00	90.99	0.01			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.4184514787
95.44	0.01	94.96	0.00	94.41	0.00	90.99	0.01			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.613440340
95.44	0.01	94.96	0.00	94.41	0.00	90.99	0.01			95.29	0.00	97.41	0.00	99.60	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3343006524

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.496886562
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1679342674
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2316858393
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1959155369
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2448855282
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2538663313
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1248910299
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3432607190
/workspace/coverage/cover_reg_top/0.xbar_error_random.1469318084
/workspace/coverage/cover_reg_top/0.xbar_random.2020836019
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.4167209101
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.35177341
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3368674176
/workspace/coverage/cover_reg_top/0.xbar_same_source.2304575920
/workspace/coverage/cover_reg_top/0.xbar_smoke.3283831394
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3375023607
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2552042498
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1176236677
/workspace/coverage/cover_reg_top/0.xbar_stress_all.654439228
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.4132906579
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.374343507
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.4165344467
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1920015530
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1377154002
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3285237022
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2076878287
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3125085044
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3236767208
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.777400980
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3779931371
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1468572537
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2592328106
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3999281277
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.4049890543
/workspace/coverage/cover_reg_top/1.xbar_error_random.223948543
/workspace/coverage/cover_reg_top/1.xbar_random.1021665793
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1008622725
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2950395611
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.679210498
/workspace/coverage/cover_reg_top/1.xbar_same_source.3162913428
/workspace/coverage/cover_reg_top/1.xbar_smoke.2428078198
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.750537407
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2625159123
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1793175481
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3791856120
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1726365192
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2588254033
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2757156441
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1493099603
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1734122368
/workspace/coverage/cover_reg_top/10.chip_tl_errors.3859200527
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1550975827
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3184167561
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2782367204
/workspace/coverage/cover_reg_top/10.xbar_error_random.292074461
/workspace/coverage/cover_reg_top/10.xbar_random.448676757
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.325940172
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2993340994
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.883171717
/workspace/coverage/cover_reg_top/10.xbar_same_source.16854300
/workspace/coverage/cover_reg_top/10.xbar_smoke.127794219
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3249288167
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.177140381
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1731412680
/workspace/coverage/cover_reg_top/10.xbar_stress_all.898212128
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3377120332
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1520599147
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1792964119
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1377967578
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3887796346
/workspace/coverage/cover_reg_top/11.chip_tl_errors.2903054355
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.115972598
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2107679019
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3225702403
/workspace/coverage/cover_reg_top/11.xbar_error_random.1793882234
/workspace/coverage/cover_reg_top/11.xbar_random.2001926487
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.531562347
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3242118055
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3880830911
/workspace/coverage/cover_reg_top/11.xbar_same_source.1172380544
/workspace/coverage/cover_reg_top/11.xbar_smoke.2413482957
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1935155965
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.888396316
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1270351009
/workspace/coverage/cover_reg_top/11.xbar_stress_all.496194382
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3249212245
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1525032340
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2127422874
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2856214818
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3198123978
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2852600365
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3787757525
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2365608029
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1958500123
/workspace/coverage/cover_reg_top/12.xbar_error_random.2635515581
/workspace/coverage/cover_reg_top/12.xbar_random.246246722
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3274771616
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3896733050
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3223231215
/workspace/coverage/cover_reg_top/12.xbar_same_source.1284482655
/workspace/coverage/cover_reg_top/12.xbar_smoke.4190513744
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3464026018
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.319028999
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3268423507
/workspace/coverage/cover_reg_top/12.xbar_stress_all.490221250
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1355235408
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3046349231
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2880410801
/workspace/coverage/cover_reg_top/13.chip_csr_rw.1041051153
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2351432596
/workspace/coverage/cover_reg_top/13.xbar_error_random.2782044562
/workspace/coverage/cover_reg_top/13.xbar_random.2122791380
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3991689239
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3080321842
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4236576682
/workspace/coverage/cover_reg_top/13.xbar_same_source.1362551294
/workspace/coverage/cover_reg_top/13.xbar_smoke.3727652876
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.124227465
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.883281646
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.105076660
/workspace/coverage/cover_reg_top/13.xbar_stress_all.3143997370
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1791363456
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.763143136
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1594806293
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1589588985
/workspace/coverage/cover_reg_top/14.chip_csr_rw.2120249056
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3011583300
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.1297421379
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2672446445
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2687815619
/workspace/coverage/cover_reg_top/14.xbar_error_random.2040216134
/workspace/coverage/cover_reg_top/14.xbar_random.2073497777
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1194603268
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1295628468
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3190965792
/workspace/coverage/cover_reg_top/14.xbar_same_source.1790800283
/workspace/coverage/cover_reg_top/14.xbar_smoke.4021655045
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3970588545
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1519121168
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3555445942
/workspace/coverage/cover_reg_top/14.xbar_stress_all.3291679687
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.691808784
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3528871975
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1441795349
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.1240760107
/workspace/coverage/cover_reg_top/15.chip_csr_rw.2531845845
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.1420010275
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.3974769353
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2975963332
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1962088429
/workspace/coverage/cover_reg_top/15.xbar_error_random.2819511315
/workspace/coverage/cover_reg_top/15.xbar_random.649045170
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2174299758
/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.3051844425
/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.3624786118
/workspace/coverage/cover_reg_top/15.xbar_same_source.1475518709
/workspace/coverage/cover_reg_top/15.xbar_smoke.3644352099
/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.530495360
/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.1544873761
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.4102104207
/workspace/coverage/cover_reg_top/15.xbar_stress_all.711272197
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1486883952
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2455248283
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.3427614888
/workspace/coverage/cover_reg_top/16.chip_csr_rw.1494787506
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1252690742
/workspace/coverage/cover_reg_top/16.xbar_access_same_device.475306999
/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2473967750
/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3432055160
/workspace/coverage/cover_reg_top/16.xbar_error_random.2771140683
/workspace/coverage/cover_reg_top/16.xbar_random.2921826084
/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2357439500
/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.652477553
/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.2950602895
/workspace/coverage/cover_reg_top/16.xbar_same_source.1651553986
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/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.780494855
/workspace/coverage/default/74.chip_sw_all_escalation_resets.988643694
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1141078760
/workspace/coverage/default/75.chip_sw_all_escalation_resets.4012202641
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4230617641
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1409645599
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1114371554
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1174662357
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2251407199
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1238656328
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2944583490
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3276233132
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2832709291
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1282432267
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.983795452
/workspace/coverage/default/81.chip_sw_all_escalation_resets.1126239016
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2554126452
/workspace/coverage/default/83.chip_sw_all_escalation_resets.4074965151
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1820832268
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1530772987
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1381779558
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3172246745
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2160634214
/workspace/coverage/default/87.chip_sw_all_escalation_resets.447001692
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.332032721
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1703665396
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1344766049
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3669753196
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2883198396
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3612581915
/workspace/coverage/default/90.chip_sw_all_escalation_resets.25169994
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1793930454
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3748075928
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1815431269
/workspace/coverage/default/94.chip_sw_all_escalation_resets.961285586
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1700183992
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1717354667
/workspace/coverage/default/99.chip_sw_all_escalation_resets.402094311
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1777309660
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.984030555
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.435335016
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.831488320
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2811641037
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2177857426
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2065681615
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1455190388

---

Total test records in report: 2779

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.4155900778			May 19 04:16:49 PM PDT 24	May 19 04:23:20 PM PDT 24	3940870802 ps
T2	/workspace/coverage/default/0.chip_sw_gpio.3488280220			May 19 03:44:35 PM PDT 24	May 19 03:53:27 PM PDT 24	3693035606 ps
T3	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3972324256			May 19 03:44:11 PM PDT 24	May 19 03:48:46 PM PDT 24	3013266228 ps
T4	/workspace/coverage/default/2.rom_e2e_shutdown_output.3946825210			May 19 04:12:27 PM PDT 24	May 19 04:51:58 PM PDT 24	21212858792 ps
T98	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2996479508			May 19 04:06:02 PM PDT 24	May 19 04:31:56 PM PDT 24	7447423334 ps
T15	/workspace/coverage/default/0.chip_sw_usbdev_vbus.2527045042			May 19 03:43:25 PM PDT 24	May 19 03:47:17 PM PDT 24	2614654240 ps
T5	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1919211329			May 19 03:50:47 PM PDT 24	May 19 03:59:51 PM PDT 24	6748578949 ps
T112	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2737376140			May 19 03:58:56 PM PDT 24	May 19 04:02:47 PM PDT 24	2819919816 ps
T30	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.300988640			May 19 03:53:31 PM PDT 24	May 19 04:20:01 PM PDT 24	14878118969 ps
T135	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1184536315			May 19 04:09:43 PM PDT 24	May 19 04:32:04 PM PDT 24	7836344888 ps
T187	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1233919137			May 19 04:10:35 PM PDT 24	May 19 04:32:53 PM PDT 24	8445346200 ps
T93	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4240591990			May 19 03:46:30 PM PDT 24	May 19 03:55:18 PM PDT 24	5883093536 ps
T188	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3234194921			May 19 04:15:36 PM PDT 24	May 19 04:20:31 PM PDT 24	3182066850 ps
T285	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2226172017			May 19 04:12:45 PM PDT 24	May 19 04:18:44 PM PDT 24	3463676400 ps
T113	/workspace/coverage/default/0.chip_sw_aes_idle.79964508			May 19 03:44:24 PM PDT 24	May 19 03:49:18 PM PDT 24	3172106104 ps
T161	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2285598489			May 19 03:47:41 PM PDT 24	May 19 03:50:33 PM PDT 24	3044233032 ps
T31	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.501117360			May 19 03:47:28 PM PDT 24	May 19 03:56:40 PM PDT 24	5179496036 ps
T212	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3441370057			May 19 03:43:50 PM PDT 24	May 19 03:59:57 PM PDT 24	5170295188 ps
T286	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2160634214			May 19 04:16:40 PM PDT 24	May 19 04:22:19 PM PDT 24	3370220168 ps
T287	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3669753196			May 19 04:10:37 PM PDT 24	May 19 04:16:38 PM PDT 24	3254619054 ps
T97	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1486719387			May 19 03:48:15 PM PDT 24	May 19 04:20:51 PM PDT 24	9483702954 ps
T86	/workspace/coverage/default/22.chip_sw_all_escalation_resets.3400110421			May 19 04:13:29 PM PDT 24	May 19 04:23:08 PM PDT 24	5396885464 ps
T669	/workspace/coverage/default/2.chip_sw_hmac_smoketest.2839004532			May 19 04:07:19 PM PDT 24	May 19 04:14:12 PM PDT 24	3538926260 ps
T42	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.432305292			May 19 03:52:56 PM PDT 24	May 19 04:45:19 PM PDT 24	10885465854 ps
T61	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2127323607			May 19 04:08:58 PM PDT 24	May 19 04:24:18 PM PDT 24	9208019128 ps
T159	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.4072926540			May 19 04:03:15 PM PDT 24	May 19 04:08:48 PM PDT 24	3714443177 ps
T43	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1768196913			May 19 04:02:54 PM PDT 24	May 19 05:00:13 PM PDT 24	13902617814 ps
T87	/workspace/coverage/default/1.chip_sw_flash_crash_alert.1990451804			May 19 03:57:19 PM PDT 24	May 19 04:07:44 PM PDT 24	4821031754 ps
T841	/workspace/coverage/default/0.chip_sw_example_concurrency.246167789			May 19 03:44:02 PM PDT 24	May 19 03:48:12 PM PDT 24	2802130212 ps
T189	/workspace/coverage/default/2.chip_sw_kmac_idle.313900602			May 19 04:04:35 PM PDT 24	May 19 04:08:13 PM PDT 24	2410614136 ps
T114	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4174265854			May 19 03:56:53 PM PDT 24	May 19 04:09:00 PM PDT 24	4159089210 ps
T186	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2692686211			May 19 03:50:54 PM PDT 24	May 19 04:01:41 PM PDT 24	5349177624 ps
T282	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.696379545			May 19 04:11:32 PM PDT 24	May 19 04:19:23 PM PDT 24	3798442438 ps
T47	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2167383630			May 19 04:06:16 PM PDT 24	May 19 04:17:13 PM PDT 24	3989722932 ps
T210	/workspace/coverage/default/0.chip_sw_pattgen_ios.1880428198			May 19 03:44:30 PM PDT 24	May 19 03:48:45 PM PDT 24	2619346800 ps
T10	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.725504043			May 19 03:48:56 PM PDT 24	May 19 03:54:14 PM PDT 24	2418358904 ps
T213	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2870844634			May 19 03:50:23 PM PDT 24	May 19 04:06:55 PM PDT 24	4746108520 ps
T106	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.107816253			May 19 04:08:06 PM PDT 24	May 19 04:14:36 PM PDT 24	3432856752 ps
T283	/workspace/coverage/default/2.chip_plic_all_irqs_20.2460906631			May 19 04:04:49 PM PDT 24	May 19 04:17:51 PM PDT 24	4419740552 ps
T284	/workspace/coverage/default/29.chip_sw_all_escalation_resets.929649623			May 19 04:12:55 PM PDT 24	May 19 04:23:19 PM PDT 24	4569700450 ps
T92	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3206215406			May 19 03:53:21 PM PDT 24	May 19 04:39:52 PM PDT 24	10948415736 ps
T6	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.703455613			May 19 04:01:46 PM PDT 24	May 19 04:17:08 PM PDT 24	9700545252 ps
T162	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3252184314			May 19 04:05:18 PM PDT 24	May 19 04:14:23 PM PDT 24	5414859592 ps
T216	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2163317168			May 19 03:58:00 PM PDT 24	May 19 04:06:17 PM PDT 24	5245952242 ps
T208	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2648937851			May 19 04:14:27 PM PDT 24	May 19 04:53:36 PM PDT 24	13325240460 ps
T76	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1603143397			May 19 03:43:35 PM PDT 24	May 19 04:02:43 PM PDT 24	7954625800 ps
T214	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1901263031			May 19 04:11:53 PM PDT 24	May 19 04:47:22 PM PDT 24	13107533414 ps
T67	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3408890603			May 19 03:53:58 PM PDT 24	May 19 04:03:56 PM PDT 24	5759721172 ps
T383	/workspace/coverage/default/62.chip_sw_all_escalation_resets.252698475			May 19 04:14:21 PM PDT 24	May 19 04:24:50 PM PDT 24	5283820680 ps
T183	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2919981017			May 19 04:00:45 PM PDT 24	May 19 04:13:03 PM PDT 24	4082299276 ps
T842	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2822136716			May 19 04:07:58 PM PDT 24	May 19 04:14:08 PM PDT 24	6587516902 ps
T235	/workspace/coverage/default/0.chip_sw_plic_sw_irq.3227117502			May 19 03:47:03 PM PDT 24	May 19 03:51:19 PM PDT 24	3219469150 ps
T48	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4023355056			May 19 03:54:50 PM PDT 24	May 19 04:06:08 PM PDT 24	4107772732 ps
T44	/workspace/coverage/default/0.chip_jtag_mem_access.1346916455			May 19 03:37:42 PM PDT 24	May 19 04:03:07 PM PDT 24	13550943773 ps
T363	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1114371554			May 19 04:16:16 PM PDT 24	May 19 04:22:33 PM PDT 24	4457967000 ps
T196	/workspace/coverage/default/85.chip_sw_all_escalation_resets.2440224397			May 19 04:17:48 PM PDT 24	May 19 04:27:10 PM PDT 24	4733323820 ps
T209	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.99789930			May 19 04:14:09 PM PDT 24	May 19 04:54:25 PM PDT 24	12792312280 ps
T99	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3947310512			May 19 04:00:42 PM PDT 24	May 19 04:21:54 PM PDT 24	6506196008 ps
T156	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2521983934			May 19 03:47:09 PM PDT 24	May 19 04:30:01 PM PDT 24	16155944205 ps
T329	/workspace/coverage/default/45.chip_sw_all_escalation_resets.2801831545			May 19 04:13:48 PM PDT 24	May 19 04:24:12 PM PDT 24	5471995078 ps
T102	/workspace/coverage/default/2.chip_sw_otbn_smoketest.513598745			May 19 04:06:22 PM PDT 24	May 19 04:55:22 PM PDT 24	10593208140 ps
T843	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3451896258			May 19 04:00:34 PM PDT 24	May 19 04:05:36 PM PDT 24	4379368040 ps
T240	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1705997223			May 19 04:04:00 PM PDT 24	May 19 04:10:58 PM PDT 24	3209335360 ps
T103	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.620647144			May 19 04:06:12 PM PDT 24	May 19 05:02:21 PM PDT 24	24853005074 ps
T13	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2154667310			May 19 03:49:30 PM PDT 24	May 19 03:56:21 PM PDT 24	4982008814 ps
T149	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1113656534			May 19 03:50:11 PM PDT 24	May 19 04:13:46 PM PDT 24	7978241280 ps
T150	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.102850100			May 19 04:08:35 PM PDT 24	May 19 04:14:27 PM PDT 24	4149971590 ps
T128	/workspace/coverage/default/1.chip_tap_straps_prod.691340589			May 19 03:55:47 PM PDT 24	May 19 04:14:34 PM PDT 24	9482917298 ps
T151	/workspace/coverage/default/0.rom_keymgr_functest.592483942			May 19 03:48:33 PM PDT 24	May 19 04:01:54 PM PDT 24	4938321396 ps
T152	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.560123649			May 19 04:05:52 PM PDT 24	May 19 04:21:53 PM PDT 24	6721809920 ps
T153	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.619084311			May 19 03:44:03 PM PDT 24	May 19 03:59:23 PM PDT 24	4975873840 ps
T154	/workspace/coverage/default/3.chip_sw_uart_tx_rx.603118911			May 19 04:08:25 PM PDT 24	May 19 04:17:23 PM PDT 24	4681185600 ps
T155	/workspace/coverage/default/2.chip_sw_kmac_smoketest.4053233086			May 19 04:06:44 PM PDT 24	May 19 04:11:41 PM PDT 24	2421201890 ps
T115	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1044784926			May 19 03:45:56 PM PDT 24	May 19 03:56:40 PM PDT 24	4334117840 ps
T335	/workspace/coverage/default/0.chip_sw_flash_crash_alert.839991815			May 19 03:49:40 PM PDT 24	May 19 04:02:37 PM PDT 24	4982773024 ps
T670	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.3190218192			May 19 03:55:36 PM PDT 24	May 19 03:59:54 PM PDT 24	2746737572 ps
T211	/workspace/coverage/default/1.chip_sw_pattgen_ios.1767355230			May 19 03:49:45 PM PDT 24	May 19 03:54:38 PM PDT 24	2340336120 ps
T643	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1703665396			May 19 04:19:34 PM PDT 24	May 19 04:25:44 PM PDT 24	3850127966 ps
T7	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3495278094			May 19 03:59:00 PM PDT 24	May 19 04:04:26 PM PDT 24	2666191765 ps
T844	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.975914611			May 19 03:56:55 PM PDT 24	May 19 04:00:33 PM PDT 24	2307662677 ps
T218	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3786336868			May 19 03:44:06 PM PDT 24	May 19 04:04:52 PM PDT 24	7938788056 ps
T227	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2254185120			May 19 03:42:53 PM PDT 24	May 19 03:53:28 PM PDT 24	5553764968 ps
T157	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3430581556			May 19 03:45:08 PM PDT 24	May 19 03:53:45 PM PDT 24	19009733064 ps
T845	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.583916341			May 19 04:03:07 PM PDT 24	May 19 04:10:43 PM PDT 24	3795919500 ps
T315	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2095309036			May 19 03:44:29 PM PDT 24	May 19 03:54:11 PM PDT 24	4167488016 ps
T373	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1282432267			May 19 04:18:56 PM PDT 24	May 19 04:24:39 PM PDT 24	3315233084 ps
T846	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1312941106			May 19 04:01:37 PM PDT 24	May 19 04:15:09 PM PDT 24	9159534864 ps
T206	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3132795388			May 19 03:51:42 PM PDT 24	May 19 03:58:01 PM PDT 24	2989833402 ps
T668	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1282440440			May 19 03:46:32 PM PDT 24	May 19 03:51:11 PM PDT 24	2909106629 ps
T50	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.948057713			May 19 03:57:10 PM PDT 24	May 19 04:05:19 PM PDT 24	4907666680 ps
T360	/workspace/coverage/default/1.chip_sw_edn_kat.3535958626			May 19 03:54:33 PM PDT 24	May 19 04:05:08 PM PDT 24	3765363500 ps
T333	/workspace/coverage/default/9.chip_sw_all_escalation_resets.2883198396			May 19 04:10:16 PM PDT 24	May 19 04:18:18 PM PDT 24	4794195256 ps
T175	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.883362467			May 19 04:01:57 PM PDT 24	May 19 04:12:40 PM PDT 24	8277870726 ps
T322	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2253272239			May 19 03:50:31 PM PDT 24	May 19 04:03:15 PM PDT 24	4455669940 ps
T133	/workspace/coverage/default/40.chip_sw_all_escalation_resets.3711375826			May 19 04:13:26 PM PDT 24	May 19 04:24:42 PM PDT 24	5453960378 ps
T142	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3335435476			May 19 04:00:47 PM PDT 24	May 19 04:11:38 PM PDT 24	4527869664 ps
T107	/workspace/coverage/default/1.chip_plic_all_irqs_10.413677344			May 19 03:54:35 PM PDT 24	May 19 04:05:22 PM PDT 24	4431097720 ps
T143	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1017267533			May 19 03:48:31 PM PDT 24	May 19 04:48:12 PM PDT 24	17841146745 ps
T16	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.714792330			May 19 04:04:56 PM PDT 24	May 19 04:11:12 PM PDT 24	6647642350 ps
T85	/workspace/coverage/default/0.chip_sw_all_escalation_resets.4052027508			May 19 03:44:06 PM PDT 24	May 19 03:54:01 PM PDT 24	5351466430 ps
T81	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2456122408			May 19 03:47:11 PM PDT 24	May 19 03:53:25 PM PDT 24	3796622888 ps
T144	/workspace/coverage/default/43.chip_sw_all_escalation_resets.1425130199			May 19 04:15:38 PM PDT 24	May 19 04:23:22 PM PDT 24	4550647874 ps
T145	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.184822677			May 19 03:51:28 PM PDT 24	May 19 04:18:50 PM PDT 24	9668132862 ps
T146	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3660724490			May 19 03:53:34 PM PDT 24	May 19 04:54:02 PM PDT 24	14382382232 ps
T392	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3816352165			May 19 03:48:33 PM PDT 24	May 19 03:54:39 PM PDT 24	4785581464 ps
T393	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2815415775			May 19 04:10:53 PM PDT 24	May 19 04:31:48 PM PDT 24	7833952408 ps
T49	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2083172905			May 19 03:56:12 PM PDT 24	May 19 04:02:52 PM PDT 24	7017832210 ps
T394	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3270923521			May 19 03:53:00 PM PDT 24	May 19 03:57:08 PM PDT 24	3226399762 ps
T847	/workspace/coverage/default/1.chip_sw_aes_smoketest.1863475886			May 19 03:58:16 PM PDT 24	May 19 04:03:50 PM PDT 24	2444239272 ps
T371	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1110110848			May 19 03:46:00 PM PDT 24	May 19 04:04:15 PM PDT 24	8194050424 ps
T848	/workspace/coverage/default/2.rom_keymgr_functest.1331322993			May 19 04:08:21 PM PDT 24	May 19 04:15:53 PM PDT 24	4651065490 ps
T14	/workspace/coverage/default/2.chip_sw_gpio.1721609172			May 19 04:00:38 PM PDT 24	May 19 04:10:27 PM PDT 24	4211199484 ps
T344	/workspace/coverage/default/0.chip_sw_aon_timer_irq.658822874			May 19 03:44:09 PM PDT 24	May 19 03:51:00 PM PDT 24	4340374984 ps
T163	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2352197622			May 19 03:44:14 PM PDT 24	May 19 03:54:51 PM PDT 24	6132922988 ps
T381	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2692276038			May 19 04:00:25 PM PDT 24	May 19 04:18:02 PM PDT 24	5770524760 ps
T307	/workspace/coverage/default/1.chip_plic_all_irqs_20.638298569			May 19 03:54:15 PM PDT 24	May 19 04:07:04 PM PDT 24	4467541456 ps
T849	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1446907752			May 19 03:47:10 PM PDT 24	May 19 04:24:23 PM PDT 24	26671489088 ps
T334	/workspace/coverage/default/55.chip_sw_all_escalation_resets.1077680934			May 19 04:20:25 PM PDT 24	May 19 04:29:03 PM PDT 24	5771681832 ps
T850	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.685066009			May 19 03:46:35 PM PDT 24	May 19 03:53:43 PM PDT 24	3299225960 ps
T653	/workspace/coverage/default/96.chip_sw_all_escalation_resets.1700183992			May 19 04:17:46 PM PDT 24	May 19 04:27:13 PM PDT 24	6365491968 ps
T184	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2382915042			May 19 03:47:20 PM PDT 24	May 19 03:51:43 PM PDT 24	3405590466 ps
T362	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1132636529			May 19 04:13:32 PM PDT 24	May 19 04:19:34 PM PDT 24	3356308846 ps
T384	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.780494855			May 19 04:15:44 PM PDT 24	May 19 04:22:33 PM PDT 24	3715769336 ps
T80	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1329102666			May 19 03:48:24 PM PDT 24	May 19 03:58:12 PM PDT 24	4785599588 ps
T215	/workspace/coverage/default/84.chip_sw_all_escalation_resets.1530772987			May 19 04:16:27 PM PDT 24	May 19 04:24:00 PM PDT 24	4202209096 ps
T70	/workspace/coverage/default/0.chip_sw_alert_test.4210163719			May 19 03:46:29 PM PDT 24	May 19 03:53:20 PM PDT 24	3387053120 ps
T724	/workspace/coverage/default/82.chip_sw_all_escalation_resets.2554126452			May 19 04:16:12 PM PDT 24	May 19 04:24:49 PM PDT 24	5379006080 ps
T382	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2520910095			May 19 03:43:12 PM PDT 24	May 19 03:57:51 PM PDT 24	5889661490 ps
T851	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1314936363			May 19 04:03:48 PM PDT 24	May 19 04:14:53 PM PDT 24	4937365112 ps
T375	/workspace/coverage/default/24.chip_sw_all_escalation_resets.967488609			May 19 04:13:34 PM PDT 24	May 19 04:23:31 PM PDT 24	4485902856 ps
T624	/workspace/coverage/default/0.chip_sw_edn_kat.1534380321			May 19 03:47:00 PM PDT 24	May 19 03:57:09 PM PDT 24	3142928112 ps
T652	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1820832268			May 19 04:17:36 PM PDT 24	May 19 04:23:25 PM PDT 24	4214765028 ps
T852	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.4228297056			May 19 03:44:04 PM PDT 24	May 19 03:58:16 PM PDT 24	8626284108 ps
T308	/workspace/coverage/default/1.chip_plic_all_irqs_0.3990570729			May 19 03:55:35 PM PDT 24	May 19 04:16:04 PM PDT 24	5995984720 ps
T125	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1146450070			May 19 03:46:39 PM PDT 24	May 19 03:54:53 PM PDT 24	3484732090 ps
T853	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3566714324			May 19 03:47:28 PM PDT 24	May 19 03:54:25 PM PDT 24	4050009042 ps
T854	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3335984324			May 19 03:48:37 PM PDT 24	May 19 03:54:29 PM PDT 24	3761892204 ps
T297	/workspace/coverage/default/4.chip_sw_all_escalation_resets.3298182267			May 19 04:08:49 PM PDT 24	May 19 04:17:49 PM PDT 24	4331589752 ps
T241	/workspace/coverage/default/2.chip_sw_edn_auto_mode.3373813768			May 19 04:05:11 PM PDT 24	May 19 04:32:57 PM PDT 24	7326055030 ps
T232	/workspace/coverage/default/67.chip_sw_all_escalation_resets.16725069			May 19 04:15:44 PM PDT 24	May 19 04:26:08 PM PDT 24	6146586428 ps
T94	/workspace/coverage/default/1.chip_sw_flash_init.1503340052			May 19 03:48:37 PM PDT 24	May 19 04:22:46 PM PDT 24	16924064920 ps
T300	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3899639488			May 19 03:56:15 PM PDT 24	May 19 03:59:57 PM PDT 24	2906829585 ps
T301	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3193812995			May 19 03:58:18 PM PDT 24	May 19 04:09:01 PM PDT 24	3723138488 ps
T302	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3849451491			May 19 03:43:49 PM PDT 24	May 19 03:52:04 PM PDT 24	5689515572 ps
T110	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1215562305			May 19 04:14:32 PM PDT 24	May 19 04:20:25 PM PDT 24	4068266058 ps
T303	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2351845284			May 19 03:53:34 PM PDT 24	May 19 04:50:46 PM PDT 24	14403739080 ps
T304	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2144616932			May 19 03:46:29 PM PDT 24	May 19 03:50:14 PM PDT 24	2959099944 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.764387417			May 19 03:42:18 PM PDT 24	May 19 03:50:00 PM PDT 24	4155026176 ps
T385	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3043252707			May 19 03:56:07 PM PDT 24	May 19 05:05:21 PM PDT 24	15189638438 ps
T236	/workspace/coverage/default/1.chip_sw_power_sleep_load.234118904			May 19 03:58:07 PM PDT 24	May 19 04:05:05 PM PDT 24	4190840772 ps
T191	/workspace/coverage/default/0.chip_sw_kmac_entropy.1741661963			May 19 03:45:42 PM PDT 24	May 19 03:50:05 PM PDT 24	2705759706 ps
T396	/workspace/coverage/default/0.chip_sw_otbn_randomness.2716297967			May 19 03:46:00 PM PDT 24	May 19 04:03:45 PM PDT 24	5947709630 ps
T117	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3920829975			May 19 04:12:05 PM PDT 24	May 19 04:17:49 PM PDT 24	3391940330 ps
T291	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2678307047			May 19 04:07:58 PM PDT 24	May 19 04:21:42 PM PDT 24	5349413301 ps
T18	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.19509279			May 19 03:58:56 PM PDT 24	May 19 04:08:44 PM PDT 24	5536407990 ps
T292	/workspace/coverage/default/1.chip_sw_kmac_app_rom.4171545280			May 19 03:54:42 PM PDT 24	May 19 03:58:15 PM PDT 24	2519586676 ps
T118	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1543676911			May 19 03:47:27 PM PDT 24	May 19 03:51:21 PM PDT 24	2907535953 ps
T134	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2773768851			May 19 04:16:20 PM PDT 24	May 19 04:21:57 PM PDT 24	3537792168 ps
T293	/workspace/coverage/default/1.chip_sw_example_concurrency.506576386			May 19 03:48:42 PM PDT 24	May 19 03:52:41 PM PDT 24	2891186414 ps
T294	/workspace/coverage/default/2.chip_sw_power_sleep_load.642736362			May 19 04:08:05 PM PDT 24	May 19 04:16:59 PM PDT 24	10008206002 ps
T263	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1246940409			May 19 04:02:48 PM PDT 24	May 19 04:10:52 PM PDT 24	9168611315 ps
T295	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3606785784			May 19 03:53:00 PM PDT 24	May 19 03:58:29 PM PDT 24	3163928718 ps
T207	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.678166777			May 19 04:02:33 PM PDT 24	May 19 04:13:24 PM PDT 24	4105707117 ps
T228	/workspace/coverage/default/34.chip_sw_all_escalation_resets.4157577761			May 19 04:16:02 PM PDT 24	May 19 04:24:36 PM PDT 24	6125410928 ps
T251	/workspace/coverage/default/2.rom_e2e_asm_init_prod.2244770074			May 19 04:10:29 PM PDT 24	May 19 05:07:42 PM PDT 24	14219383263 ps
T252	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1381779558			May 19 04:16:55 PM PDT 24	May 19 04:22:44 PM PDT 24	3808278652 ps
T253	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.11948446			May 19 03:56:52 PM PDT 24	May 19 04:06:25 PM PDT 24	3456769140 ps
T254	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.4029562056			May 19 04:02:07 PM PDT 24	May 19 04:11:12 PM PDT 24	4216209728 ps
T160	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2580021450			May 19 03:55:39 PM PDT 24	May 19 04:13:04 PM PDT 24	6326833549 ps
T255	/workspace/coverage/default/1.chip_sw_kmac_smoketest.3223023836			May 19 03:58:08 PM PDT 24	May 19 04:03:46 PM PDT 24	2608618280 ps
T256	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2104570020			May 19 03:46:24 PM PDT 24	May 19 03:56:40 PM PDT 24	4280043252 ps
T257	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3525526782			May 19 03:57:05 PM PDT 24	May 19 04:15:35 PM PDT 24	8053243805 ps
T258	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2390420138			May 19 04:11:53 PM PDT 24	May 19 04:18:28 PM PDT 24	3111011020 ps
T855	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.832987724			May 19 04:11:34 PM PDT 24	May 19 04:18:39 PM PDT 24	4134211024 ps
T116	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.4203126352			May 19 04:04:33 PM PDT 24	May 19 04:18:30 PM PDT 24	7176649126 ps
T104	/workspace/coverage/default/1.chip_sw_otbn_smoketest.876690019			May 19 04:01:55 PM PDT 24	May 19 04:39:13 PM PDT 24	9955907220 ps
T712	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.743713851			May 19 03:55:06 PM PDT 24	May 19 04:03:05 PM PDT 24	3654114520 ps
T275	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4088827223			May 19 03:56:47 PM PDT 24	May 19 04:05:59 PM PDT 24	5380700236 ps
T192	/workspace/coverage/default/2.chip_sw_kmac_entropy.80326352			May 19 04:01:09 PM PDT 24	May 19 04:05:25 PM PDT 24	3357000392 ps
T372	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3713360978			May 19 04:14:31 PM PDT 24	May 19 04:19:37 PM PDT 24	2931586770 ps
T330	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.336124933			May 19 03:43:34 PM PDT 24	May 19 03:56:02 PM PDT 24	4265101496 ps
T856	/workspace/coverage/default/0.chip_sw_uart_tx_rx.1585954283			May 19 03:44:27 PM PDT 24	May 19 03:57:01 PM PDT 24	4334325966 ps
T654	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3704826037			May 19 04:12:37 PM PDT 24	May 19 04:20:03 PM PDT 24	3378301896 ps
T353	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2589187041			May 19 04:12:18 PM PDT 24	May 19 04:19:22 PM PDT 24	3541101300 ps
T100	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3820738684			May 19 04:03:12 PM PDT 24	May 19 04:19:41 PM PDT 24	10285169030 ps
T88	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.612782878			May 19 04:03:42 PM PDT 24	May 19 04:29:08 PM PDT 24	7340201676 ps
T355	/workspace/coverage/default/1.chip_sw_edn_boot_mode.2795254456			May 19 03:52:51 PM PDT 24	May 19 04:01:42 PM PDT 24	2564351152 ps
T356	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.771469452			May 19 03:50:15 PM PDT 24	May 19 03:54:44 PM PDT 24	3537219744 ps
T82	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1553212511			May 19 03:43:44 PM PDT 24	May 19 04:15:19 PM PDT 24	12169666050 ps
T193	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2703585923			May 19 04:03:39 PM PDT 24	May 19 04:24:39 PM PDT 24	6282318504 ps
T71	/workspace/coverage/default/2.chip_sw_alert_test.1351803132			May 19 04:02:56 PM PDT 24	May 19 04:08:45 PM PDT 24	2807905480 ps
T229	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2491833698			May 19 03:44:38 PM PDT 24	May 19 03:55:28 PM PDT 24	7352602890 ps
T357	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3708360869			May 19 04:13:23 PM PDT 24	May 19 04:20:19 PM PDT 24	4182044170 ps
T238	/workspace/coverage/default/0.chip_sw_rv_timer_irq.3827999873			May 19 03:45:15 PM PDT 24	May 19 03:49:04 PM PDT 24	2680616414 ps
T37	/workspace/coverage/default/1.chip_sw_spi_device_tpm.3705025445			May 19 03:50:28 PM PDT 24	May 19 03:56:53 PM PDT 24	3722376013 ps
T276	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1399954766			May 19 04:10:30 PM PDT 24	May 19 04:21:20 PM PDT 24	5111422488 ps
T239	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.378585511			May 19 04:02:34 PM PDT 24	May 19 04:06:28 PM PDT 24	3185229048 ps
T686	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3564486524			May 19 04:11:40 PM PDT 24	May 19 04:17:09 PM PDT 24	4109057500 ps
T857	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1513969837			May 19 04:05:19 PM PDT 24	May 19 04:11:36 PM PDT 24	3144737776 ps
T858	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2553305708			May 19 04:01:39 PM PDT 24	May 19 04:54:25 PM PDT 24	41470733931 ps
T342	/workspace/coverage/default/58.chip_sw_all_escalation_resets.4200984773			May 19 04:19:58 PM PDT 24	May 19 04:27:23 PM PDT 24	4958012752 ps
T706	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2469427165			May 19 04:11:46 PM PDT 24	May 19 04:18:26 PM PDT 24	3359753080 ps
T859	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2754022789			May 19 03:53:20 PM PDT 24	May 19 04:00:38 PM PDT 24	3988824408 ps
T111	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1593232846			May 19 03:53:06 PM PDT 24	May 19 03:59:02 PM PDT 24	3137622226 ps
T860	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.237499289			May 19 04:02:41 PM PDT 24	May 19 04:07:29 PM PDT 24	3159732064 ps
T861	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1451483238			May 19 04:07:32 PM PDT 24	May 19 04:13:05 PM PDT 24	4284800370 ps
T736	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3103021708			May 19 04:13:55 PM PDT 24	May 19 04:23:25 PM PDT 24	4324408308 ps
T690	/workspace/coverage/default/59.chip_sw_all_escalation_resets.3981773421			May 19 04:15:50 PM PDT 24	May 19 04:25:19 PM PDT 24	4599536720 ps
T862	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2116365340			May 19 03:49:50 PM PDT 24	May 19 03:58:43 PM PDT 24	3975910680 ps
T863	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.668840602			May 19 03:53:58 PM PDT 24	May 19 04:50:56 PM PDT 24	13823417015 ps
T728	/workspace/coverage/default/46.chip_sw_all_escalation_resets.751740013			May 19 04:15:00 PM PDT 24	May 19 04:24:37 PM PDT 24	4806182280 ps
T694	/workspace/coverage/default/92.chip_sw_all_escalation_resets.3748075928			May 19 04:17:59 PM PDT 24	May 19 04:27:14 PM PDT 24	4826161880 ps
T864	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2592453212			May 19 04:04:12 PM PDT 24	May 19 04:11:34 PM PDT 24	4321497608 ps
T865	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1421008869			May 19 04:02:32 PM PDT 24	May 19 04:11:28 PM PDT 24	5231476248 ps
T20	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2839333244			May 19 03:44:06 PM PDT 24	May 19 04:14:42 PM PDT 24	24955884380 ps
T691	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.831495185			May 19 04:14:09 PM PDT 24	May 19 04:20:35 PM PDT 24	3448634046 ps
T866	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.758401341			May 19 03:54:52 PM PDT 24	May 19 04:05:11 PM PDT 24	4261760312 ps
T119	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.349575280			May 19 03:57:00 PM PDT 24	May 19 04:00:30 PM PDT 24	2410749438 ps
T695	/workspace/coverage/default/28.chip_sw_all_escalation_resets.127425374			May 19 04:13:29 PM PDT 24	May 19 04:24:00 PM PDT 24	6297033080 ps
T231	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.179647546			May 19 03:48:56 PM PDT 24	May 19 04:15:54 PM PDT 24	10974646216 ps
T760	/workspace/coverage/default/21.chip_sw_all_escalation_resets.4083542950			May 19 04:12:08 PM PDT 24	May 19 04:19:51 PM PDT 24	4003813686 ps
T19	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2637589018			May 19 03:45:42 PM PDT 24	May 19 04:18:59 PM PDT 24	20901946292 ps
T185	/workspace/coverage/default/1.chip_sw_gpio_smoketest.1586763130			May 19 04:02:30 PM PDT 24	May 19 04:07:17 PM PDT 24	2609222109 ps
T722	/workspace/coverage/default/98.chip_sw_all_escalation_resets.1717354667			May 19 04:17:27 PM PDT 24	May 19 04:26:02 PM PDT 24	6113447044 ps
T737	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4230617641			May 19 04:15:55 PM PDT 24	May 19 04:21:07 PM PDT 24	3563992320 ps
T313	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1697858517			May 19 03:43:25 PM PDT 24	May 19 03:55:00 PM PDT 24	4138672122 ps
T21	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.981785732			May 19 03:45:27 PM PDT 24	May 19 04:30:34 PM PDT 24	20317690727 ps
T655	/workspace/coverage/default/80.chip_sw_all_escalation_resets.262411712			May 19 04:16:29 PM PDT 24	May 19 04:24:40 PM PDT 24	4452556252 ps
T32	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3380834665			May 19 04:00:54 PM PDT 24	May 19 04:06:54 PM PDT 24	3052241816 ps
T867	/workspace/coverage/default/0.chip_sw_aes_enc.957450348			May 19 03:45:12 PM PDT 24	May 19 03:50:24 PM PDT 24	3338172038 ps
T386	/workspace/coverage/default/51.chip_sw_all_escalation_resets.2145912517			May 19 04:14:24 PM PDT 24	May 19 04:23:59 PM PDT 24	4869035080 ps
T726	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2717202741			May 19 04:14:40 PM PDT 24	May 19 04:21:55 PM PDT 24	4018445676 ps
T369	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.4294840942			May 19 04:05:05 PM PDT 24	May 19 04:08:13 PM PDT 24	2131763972 ps
T767	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4194066378			May 19 04:19:50 PM PDT 24	May 19 04:26:06 PM PDT 24	3399874382 ps
T868	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1146514821			May 19 03:53:40 PM PDT 24	May 19 05:00:47 PM PDT 24	13885184762 ps
T869	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3704034560			May 19 03:53:57 PM PDT 24	May 19 03:57:04 PM PDT 24	2325685494 ps
T692	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.983795452			May 19 04:17:38 PM PDT 24	May 19 04:23:20 PM PDT 24	3090218350 ps
T870	/workspace/coverage/default/1.chip_sw_edn_sw_mode.1990180691			May 19 03:53:35 PM PDT 24	May 19 04:26:16 PM PDT 24	9131952726 ps
T309	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.670377829			May 19 03:47:38 PM PDT 24	May 19 04:07:33 PM PDT 24	7952606973 ps
T871	/workspace/coverage/default/0.rom_e2e_asm_init_prod.3043959261			May 19 03:54:30 PM PDT 24	May 19 04:50:58 PM PDT 24	14629672961 ps
T266	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3475922562			May 19 03:59:12 PM PDT 24	May 19 04:14:59 PM PDT 24	6594357950 ps
T89	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2752509139			May 19 03:43:16 PM PDT 24	May 19 04:09:38 PM PDT 24	7477442640 ps
T268	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3052546055			May 19 03:54:29 PM PDT 24	May 19 04:10:11 PM PDT 24	5476205300 ps
T269	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1507261209			May 19 03:56:43 PM PDT 24	May 19 04:07:04 PM PDT 24	7100017308 ps
T270	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630141456			May 19 04:12:52 PM PDT 24	May 19 04:18:24 PM PDT 24	2995640152 ps
T271	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3676175516			May 19 03:58:43 PM PDT 24	May 19 04:02:22 PM PDT 24	2909731210 ps
T272	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.976476920			May 19 04:01:02 PM PDT 24	May 19 04:26:11 PM PDT 24	11495332306 ps
T273	/workspace/coverage/default/32.chip_sw_all_escalation_resets.2948497996			May 19 04:13:32 PM PDT 24	May 19 04:24:36 PM PDT 24	5034984304 ps
T274	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1960952315			May 19 03:44:36 PM PDT 24	May 19 03:50:39 PM PDT 24	3694312037 ps
T23	/workspace/coverage/default/0.chip_sw_usbdev_stream.1605631321			May 19 03:45:05 PM PDT 24	May 19 04:51:51 PM PDT 24	19020785894 ps