Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139856	1			T62	102		T63	8		T105	2
values[2]	8696	1			T62	3		T66	1		T234	4
values[3]	3238	1			T455	23		T637	1		T636	134
values[4]	2058	1			T455	12		T636	74		T405	9
values[5]	1285	1			T455	9		T636	47		T405	4
values[6]	858	1			T455	4		T636	15		T405	6
values[7]	651	1			T636	4		T405	5		T781	1
values[8]	594	1			T405	21		T781	1		T794	7
values[9]	515	1			T405	7		T781	1		T534	23
values[10]	451	1			T405	6		T781	1		T534	33
values[11]	391	1			T405	6		T781	1		T534	11
values[12]	433	1			T405	6		T781	1		T534	47
values[13]	427	1			T405	13		T781	1		T534	38
values[14]	360	1			T405	17		T781	1		T534	19
values[15]	307	1			T405	6		T781	1		T534	18
values[16]	358	1			T405	6		T781	1		T534	22
values[17]	342	1			T405	5		T781	1		T534	33
values[18]	342	1			T405	9		T781	1		T534	21
values[19]	318	1			T405	8		T781	1		T534	21
values[20]	312	1			T405	7		T781	1		T534	25
values[21]	311	1			T405	11		T781	1		T534	24
values[22]	302	1			T405	5		T781	1		T534	27
values[23]	330	1			T405	4		T781	1		T534	16
values[24]	315	1			T405	5		T781	1		T534	22
values[25]	342	1			T405	18		T781	1		T534	18
values[26]	376	1			T405	17		T781	1		T534	15
values[27]	333	1			T405	9		T781	1		T534	16
values[28]	330	1			T405	5		T781	1		T534	20
values[29]	324	1			T405	3		T781	1		T534	39
values[30]	309	1			T405	4		T781	1		T534	17
values[31]	351	1			T405	3		T781	1		T534	36
values[32]	313	1			T405	4		T781	1		T534	33
values[33]	353	1			T405	6		T781	1		T534	14
values[34]	305	1			T405	9		T781	1		T534	21
values[35]	310	1			T405	9		T781	1		T534	12
values[36]	306	1			T405	5		T781	1		T534	10
values[37]	344	1			T405	14		T781	1		T534	15
values[38]	293	1			T405	9		T781	1		T534	13
values[39]	282	1			T405	6		T781	1		T534	20
values[40]	276	1			T405	6		T781	1		T534	12
values[41]	323	1			T405	10		T781	1		T534	13
values[42]	344	1			T405	9		T781	1		T534	17
values[43]	339	1			T405	6		T781	1		T534	23
values[44]	286	1			T405	6		T781	1		T534	12
values[45]	281	1			T405	3		T781	1		T534	9
values[46]	269	1			T405	17		T781	1		T534	15
values[47]	307	1			T405	12		T781	1		T534	14
values[48]	284	1			T405	5		T781	1		T534	15
values[49]	268	1			T405	5		T781	1		T534	22
values[50]	244	1			T405	6		T781	1		T534	12
values[51]	263	1			T405	5		T781	1		T534	11
values[52]	266	1			T405	14		T781	1		T534	16
values[53]	247	1			T405	8		T781	1		T534	26
values[54]	245	1			T405	4		T781	1		T534	19
values[55]	244	1			T405	7		T781	1		T534	6
values[56]	248	1			T405	5		T781	1		T534	10
values[57]	246	1			T405	14		T781	1		T534	8
values[58]	223	1			T405	5		T781	1		T534	17
values[59]	235	1			T405	21		T781	1		T534	16
values[60]	207	1			T405	11		T781	1		T534	7
values[61]	212	1			T405	7		T781	1		T534	17
values[62]	218	1			T405	4		T781	1		T534	10
values[63]	182	1			T405	8		T781	1		T534	14
values[64]	186	1			T405	6		T781	1		T534	9
values[65]	151	1			T405	2		T781	1		T534	7
values[66]	153	1			T781	1		T534	7		T487	5
values[67]	144	1			T781	1		T534	6		T487	4
values[68]	144	1			T781	1		T534	10		T487	8
values[69]	150	1			T781	1		T534	12		T487	7
values[70]	153	1			T781	1		T534	6		T487	8
values[71]	149	1			T781	1		T534	3		T487	11
values[72]	139	1			T781	1		T487	9		T783	1
values[73]	101	1			T781	1		T487	3		T783	1
values[74]	90	1			T781	1		T487	6		T783	1
values[75]	81	1			T781	1		T487	3		T783	1
values[76]	63	1			T781	1		T783	1		T795	1
values[77]	54	1			T781	1		T783	1		T795	1
values[78]	67	1			T781	1		T783	1		T795	1
values[79]	57	1			T781	1		T783	1		T795	1
values[80]	57	1			T781	1		T783	1		T795	1
values[81]	78	1			T781	1		T783	1		T795	1
values[82]	87	1			T781	1		T783	1		T795	1
values[83]	52	1			T781	1		T783	1		T795	1
values[84]	53	1			T781	1		T783	1		T795	1
values[85]	65	1			T781	1		T783	3		T795	1
values[86]	65	1			T781	1		T783	6		T795	1
values[87]	68	1			T781	1		T783	5		T795	2
values[88]	59	1			T781	1		T783	2		T795	1
values[89]	58	1			T781	1		T783	1		T795	1
values[90]	77	1			T781	1		T783	3		T795	1
values[91]	73	1			T781	1		T783	8		T795	1
values[92]	53	1			T781	1		T783	3		T795	1
values[93]	58	1			T781	1		T783	2		T795	1
values[94]	69	1			T781	1		T783	4		T795	1
values[95]	50	1			T781	1		T783	1		T795	1
values[96]	59	1			T781	1		T783	1		T795	1
values[97]	62	1			T781	1		T783	1		T795	3
values[98]	81	1			T781	1		T783	1		T795	3
values[99]	87	1			T781	1		T783	9		T795	6
values[100]	67	1			T781	1		T783	1		T795	2
values[101]	87	1			T781	1		T783	1		T795	1
values[102]	64	1			T781	1		T783	3		T795	1
values[103]	67	1			T781	1		T783	5		T795	10
values[104]	66	1			T781	1		T783	5		T795	1
values[105]	45	1			T781	1		T783	4		T795	1
values[106]	65	1			T781	1		T783	2		T795	2
values[107]	48	1			T781	1		T783	2		T795	1
values[108]	54	1			T781	1		T783	2		T795	3
values[109]	55	1			T781	1		T783	2		T795	4
values[110]	54	1			T781	1		T783	4		T795	2
values[111]	49	1			T781	1		T783	1		T795	2
values[112]	38	1			T781	1		T783	2		T795	1
values[113]	59	1			T781	1		T783	3		T795	3
values[114]	44	1			T781	1		T783	3		T795	1
values[115]	47	1			T781	1		T783	4		T795	2
values[116]	41	1			T781	1		T783	2		T795	1
values[117]	46	1			T781	1		T783	1		T795	1
values[118]	48	1			T781	1		T783	2		T795	1
values[119]	77	1			T781	2		T783	3		T795	2
values[120]	65	1			T781	1		T783	1		T795	3
values[121]	45	1			T781	1		T783	1		T795	1
values[122]	41	1			T781	1		T783	6		T795	2
values[123]	48	1			T781	1		T783	1		T795	1
values[124]	70	1			T781	1		T783	1		T795	2
values[125]	71	1			T781	2		T783	1		T795	2
values[126]	99	1			T781	5		T783	5		T795	2
values[127]	599	1			T781	46		T783	34		T795	32
values[128]	4810	1			T781	374		T783	275		T795	283