Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	158690	1			T62	90		T63	6		T64	6
values[2]	3983	1			T62	2		T64	1		T395	6
values[3]	1829	1			T64	3		T413	30		T570	1
values[4]	1261	1			T64	3		T413	12		T570	2
values[5]	1123	1			T64	4		T413	7		T570	6
values[6]	979	1			T64	4		T570	1		T791	14
values[7]	841	1			T64	1		T570	1		T791	25
values[8]	806	1			T64	1		T570	1		T791	23
values[9]	745	1			T64	1		T570	2		T791	18
values[10]	655	1			T64	3		T570	1		T791	10
values[11]	710	1			T64	4		T570	6		T791	3
values[12]	721	1			T64	4		T570	8		T791	7
values[13]	581	1			T64	1		T570	3		T791	12
values[14]	442	1			T64	3		T570	1		T791	18
values[15]	454	1			T64	3		T570	2		T791	32
values[16]	441	1			T64	1		T570	3		T791	37
values[17]	394	1			T64	1		T570	2		T791	47
values[18]	309	1			T64	3		T570	1		T791	37
values[19]	333	1			T64	4		T570	2		T791	37
values[20]	303	1			T64	1		T570	3		T791	29
values[21]	321	1			T64	2		T570	2		T791	27
values[22]	266	1			T64	1		T570	2		T791	15
values[23]	282	1			T64	1		T570	3		T791	31
values[24]	259	1			T64	3		T570	2		T791	22
values[25]	286	1			T64	4		T570	1		T791	26
values[26]	276	1			T64	3		T570	3		T791	13
values[27]	216	1			T64	1		T570	4		T791	5
values[28]	204	1			T64	4		T570	2		T791	1
values[29]	182	1			T64	1		T570	5		T435	1
values[30]	133	1			T64	1		T570	2		T435	1
values[31]	123	1			T64	4		T570	3		T435	1
values[32]	151	1			T64	4		T570	8		T435	1
values[33]	148	1			T64	2		T570	4		T435	1
values[34]	135	1			T64	2		T570	2		T435	1
values[35]	109	1			T64	1		T570	1		T435	1
values[36]	96	1			T64	3		T570	1		T435	1
values[37]	94	1			T64	2		T570	3		T435	1
values[38]	82	1			T64	3		T570	3		T435	1
values[39]	75	1			T64	1		T570	3		T435	1
values[40]	85	1			T64	2		T570	3		T435	1
values[41]	80	1			T64	3		T570	2		T435	1
values[42]	96	1			T64	2		T570	1		T435	1
values[43]	79	1			T64	2		T570	2		T435	1
values[44]	79	1			T64	2		T570	1		T435	1
values[45]	90	1			T64	4		T570	5		T435	1
values[46]	73	1			T64	2		T570	1		T435	1
values[47]	71	1			T64	1		T570	3		T435	1
values[48]	78	1			T64	1		T570	5		T435	1
values[49]	63	1			T64	1		T570	1		T435	1
values[50]	66	1			T64	4		T570	5		T435	1
values[51]	76	1			T64	3		T570	2		T435	1
values[52]	78	1			T64	3		T570	4		T435	1
values[53]	61	1			T64	2		T570	3		T435	1
values[54]	57	1			T64	1		T570	1		T435	1
values[55]	64	1			T64	1		T570	1		T435	1
values[56]	63	1			T64	1		T570	2		T435	1
values[57]	71	1			T64	3		T570	1		T435	1
values[58]	76	1			T64	8		T570	3		T435	1
values[59]	79	1			T64	8		T570	4		T435	1
values[60]	72	1			T64	3		T570	2		T435	1
values[61]	78	1			T64	4		T570	2		T435	1
values[62]	79	1			T64	3		T570	1		T435	1
values[63]	64	1			T64	1		T570	2		T435	1
values[64]	73	1			T64	3		T570	1		T435	1
values[65]	70	1			T64	4		T570	4		T435	1
values[66]	66	1			T64	3		T570	4		T435	1
values[67]	78	1			T64	6		T570	2		T435	1
values[68]	82	1			T64	4		T570	3		T435	1
values[69]	69	1			T64	2		T570	1		T435	1
values[70]	74	1			T64	3		T570	1		T435	1
values[71]	68	1			T64	2		T570	2		T435	1
values[72]	89	1			T64	1		T570	1		T435	1
values[73]	96	1			T64	3		T570	1		T435	1
values[74]	92	1			T64	1		T570	3		T435	1
values[75]	104	1			T64	2		T570	1		T435	1
values[76]	95	1			T64	1		T570	1		T435	1
values[77]	87	1			T64	1		T570	2		T435	1
values[78]	72	1			T64	2		T570	1		T435	1
values[79]	71	1			T64	1		T570	4		T435	1
values[80]	74	1			T64	2		T570	2		T435	1
values[81]	81	1			T64	4		T570	3		T435	1
values[82]	78	1			T64	6		T570	1		T435	1
values[83]	84	1			T64	2		T570	7		T435	1
values[84]	86	1			T64	1		T570	6		T435	1
values[85]	78	1			T64	3		T570	2		T435	1
values[86]	108	1			T64	5		T570	7		T435	1
values[87]	96	1			T64	10		T570	3		T435	1
values[88]	94	1			T64	7		T570	2		T435	1
values[89]	90	1			T64	1		T570	1		T435	1
values[90]	104	1			T64	3		T570	1		T435	1
values[91]	109	1			T64	10		T570	2		T435	1
values[92]	111	1			T64	6		T570	5		T435	1
values[93]	97	1			T64	3		T570	2		T435	1
values[94]	109	1			T64	3		T570	1		T435	7
values[95]	110	1			T64	5		T570	3		T435	1
values[96]	87	1			T64	3		T570	1		T435	1
values[97]	92	1			T64	3		T570	6		T435	2
values[98]	107	1			T64	3		T570	7		T435	3
values[99]	125	1			T64	1		T570	3		T435	4
values[100]	97	1			T64	4		T570	1		T435	2
values[101]	93	1			T64	5		T570	1		T435	3
values[102]	78	1			T64	1		T570	2		T435	3
values[103]	97	1			T64	4		T570	2		T435	2
values[104]	108	1			T64	3		T570	2		T435	2
values[105]	129	1			T64	5		T570	2		T435	1
values[106]	113	1			T64	2		T570	2		T435	3
values[107]	93	1			T64	2		T570	2		T435	1
values[108]	102	1			T64	2		T570	1		T435	4
values[109]	142	1			T64	2		T570	10		T435	2
values[110]	125	1			T64	7		T570	6		T435	2
values[111]	112	1			T64	4		T570	4		T435	3
values[112]	110	1			T64	1		T570	5		T435	4
values[113]	133	1			T64	7		T570	3		T435	6
values[114]	136	1			T64	7		T570	6		T435	1
values[115]	131	1			T64	3		T570	5		T435	2
values[116]	127	1			T64	6		T570	9		T435	1
values[117]	112	1			T64	8		T570	7		T435	1
values[118]	146	1			T64	7		T570	14		T435	1
values[119]	128	1			T64	2		T570	10		T435	1
values[120]	125	1			T64	3		T570	3		T435	3
values[121]	133	1			T64	4		T570	2		T435	4
values[122]	118	1			T64	9		T570	5		T435	1
values[123]	154	1			T64	5		T570	10		T435	1
values[124]	281	1			T64	20		T570	22		T435	5
values[125]	510	1			T64	49		T570	42		T435	6
values[126]	956	1			T64	73		T570	67		T435	11
values[127]	3185	1			T64	32		T570	37		T435	122
values[128]	5413	1			T64	4		T570	4		T435	196