Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pwm_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	140403	1			T62	116		T63	5		T64	113
values[2]	8851	1			T62	1		T64	147		T66	180
values[3]	3017	1			T64	75		T66	72		T484	1
values[4]	1703	1			T64	28		T66	50		T404	6
values[5]	1037	1			T64	31		T66	26		T404	1
values[6]	717	1			T64	27		T66	14		T412	1
values[7]	557	1			T64	27		T66	10		T412	1
values[8]	466	1			T64	25		T66	18		T412	1
values[9]	332	1			T64	12		T66	6		T412	1
values[10]	283	1			T64	2		T66	2		T412	1
values[11]	240	1			T64	1		T412	1		T572	6
values[12]	238	1			T412	1		T572	14		T782	1
values[13]	223	1			T412	1		T572	11		T782	1
values[14]	266	1			T412	1		T572	14		T782	1
values[15]	291	1			T412	1		T572	10		T782	1
values[16]	237	1			T412	1		T572	4		T782	1
values[17]	266	1			T412	1		T572	9		T782	1
values[18]	231	1			T412	1		T572	6		T782	1
values[19]	216	1			T412	1		T572	8		T782	1
values[20]	255	1			T412	1		T572	3		T782	1
values[21]	244	1			T412	1		T572	4		T782	1
values[22]	283	1			T412	1		T572	6		T782	1
values[23]	223	1			T412	1		T572	10		T782	1
values[24]	205	1			T412	1		T572	10		T782	1
values[25]	238	1			T412	1		T572	9		T782	1
values[26]	257	1			T412	1		T572	4		T782	1
values[27]	222	1			T412	1		T572	6		T782	1
values[28]	255	1			T412	1		T572	11		T782	1
values[29]	267	1			T412	1		T572	8		T782	1
values[30]	245	1			T412	1		T572	9		T782	1
values[31]	231	1			T412	1		T572	5		T782	1
values[32]	228	1			T412	1		T572	3		T782	1
values[33]	260	1			T412	1		T572	3		T782	1
values[34]	262	1			T412	1		T572	6		T782	1
values[35]	266	1			T412	1		T572	5		T782	1
values[36]	230	1			T412	1		T572	11		T782	1
values[37]	246	1			T412	1		T572	4		T782	1
values[38]	324	1			T412	1		T572	18		T782	1
values[39]	292	1			T412	1		T572	10		T782	1
values[40]	229	1			T412	1		T572	6		T782	1
values[41]	246	1			T412	1		T572	4		T782	1
values[42]	201	1			T412	1		T572	8		T782	1
values[43]	241	1			T412	1		T572	6		T782	1
values[44]	227	1			T412	1		T572	3		T782	1
values[45]	225	1			T412	1		T572	6		T782	1
values[46]	253	1			T412	1		T572	4		T782	1
values[47]	231	1			T412	1		T572	5		T782	1
values[48]	239	1			T412	1		T572	12		T782	1
values[49]	236	1			T412	1		T572	5		T782	1
values[50]	241	1			T412	1		T572	14		T782	1
values[51]	221	1			T412	1		T572	11		T782	1
values[52]	225	1			T412	1		T572	10		T782	1
values[53]	196	1			T412	1		T572	5		T782	1
values[54]	192	1			T412	1		T572	4		T782	1
values[55]	222	1			T412	1		T572	9		T782	1
values[56]	209	1			T412	1		T572	7		T782	1
values[57]	210	1			T412	1		T572	6		T782	1
values[58]	217	1			T412	1		T572	3		T782	1
values[59]	232	1			T412	1		T572	6		T782	1
values[60]	218	1			T412	1		T572	4		T782	1
values[61]	191	1			T412	1		T572	2		T782	1
values[62]	189	1			T412	1		T572	8		T782	1
values[63]	215	1			T412	1		T572	20		T782	1
values[64]	164	1			T412	1		T572	4		T782	1
values[65]	145	1			T412	1		T572	4		T782	1
values[66]	151	1			T412	1		T572	14		T782	1
values[67]	150	1			T412	1		T572	10		T782	1
values[68]	130	1			T412	1		T572	12		T782	1
values[69]	142	1			T412	1		T572	9		T782	1
values[70]	136	1			T412	1		T572	5		T782	1
values[71]	111	1			T412	1		T572	5		T782	1
values[72]	138	1			T412	1		T572	5		T782	1
values[73]	118	1			T412	1		T572	4		T782	1
values[74]	126	1			T412	1		T572	8		T782	1
values[75]	89	1			T412	1		T572	4		T782	1
values[76]	74	1			T412	1		T782	1		T493	1
values[77]	82	1			T412	1		T782	1		T493	1
values[78]	105	1			T412	1		T782	2		T493	1
values[79]	90	1			T412	1		T782	3		T493	1
values[80]	96	1			T412	1		T782	4		T493	1
values[81]	83	1			T412	1		T782	3		T493	1
values[82]	79	1			T412	1		T782	2		T493	1
values[83]	94	1			T412	1		T782	5		T493	1
values[84]	95	1			T412	1		T782	2		T493	1
values[85]	84	1			T412	1		T782	5		T493	1
values[86]	82	1			T412	1		T782	6		T493	1
values[87]	77	1			T412	1		T782	9		T493	1
values[88]	92	1			T412	1		T782	4		T493	1
values[89]	114	1			T412	1		T782	10		T493	1
values[90]	107	1			T412	1		T782	3		T493	1
values[91]	96	1			T412	1		T782	1		T493	1
values[92]	87	1			T412	1		T782	1		T493	1
values[93]	82	1			T412	2		T782	3		T493	1
values[94]	78	1			T412	1		T782	4		T493	1
values[95]	90	1			T412	1		T782	3		T493	1
values[96]	79	1			T412	1		T782	3		T493	1
values[97]	79	1			T412	1		T782	3		T493	1
values[98]	90	1			T412	1		T782	2		T493	1
values[99]	99	1			T412	3		T782	1		T493	1
values[100]	79	1			T412	1		T782	1		T493	1
values[101]	90	1			T412	3		T782	5		T493	1
values[102]	93	1			T412	4		T782	2		T493	1
values[103]	122	1			T412	3		T782	1		T493	1
values[104]	110	1			T412	5		T782	2		T493	1
values[105]	110	1			T412	2		T782	1		T493	1
values[106]	91	1			T412	1		T782	2		T493	1
values[107]	106	1			T412	1		T782	2		T493	1
values[108]	104	1			T412	2		T782	1		T493	2
values[109]	80	1			T412	1		T782	1		T493	2
values[110]	87	1			T412	1		T782	2		T493	2
values[111]	83	1			T412	3		T782	1		T493	3
values[112]	101	1			T412	1		T782	1		T493	12
values[113]	73	1			T412	1		T782	1		T493	1
values[114]	71	1			T412	2		T782	2		T493	7
values[115]	85	1			T412	1		T782	2		T493	6
values[116]	66	1			T412	1		T782	2		T493	1
values[117]	82	1			T412	1		T782	1		T493	5
values[118]	93	1			T412	1		T782	2		T493	3
values[119]	89	1			T412	2		T782	2		T493	1
values[120]	73	1			T412	6		T782	1		T493	1
values[121]	89	1			T412	4		T782	5		T493	3
values[122]	96	1			T412	1		T782	3		T493	4
values[123]	70	1			T412	1		T782	2		T493	2
values[124]	84	1			T412	3		T782	3		T493	1
values[125]	88	1			T412	1		T782	1		T493	1
values[126]	190	1			T412	1		T782	2		T493	3
values[127]	1055	1			T412	32		T782	25		T493	31
values[128]	8599	1			T412	219		T782	262		T493	325