Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138188	1			T62	117		T63	8		T105	3
values[2]	8380	1			T62	4		T66	147		T234	2
values[3]	3091	1			T66	95		T395	60		T678	1
values[4]	1696	1			T66	65		T395	38		T405	16
values[5]	1149	1			T66	45		T395	35		T405	15
values[6]	635	1			T66	40		T395	13		T405	22
values[7]	511	1			T66	24		T395	8		T405	24
values[8]	450	1			T66	5		T395	1		T405	10
values[9]	388	1			T405	14		T402	7		T572	5
values[10]	373	1			T405	40		T402	3		T572	3
values[11]	370	1			T405	11		T402	8		T572	5
values[12]	336	1			T405	9		T402	1		T572	14
values[13]	310	1			T405	23		T572	8		T780	10
values[14]	321	1			T405	18		T572	6		T780	12
values[15]	262	1			T405	16		T572	4		T780	7
values[16]	291	1			T405	12		T572	6		T780	4
values[17]	244	1			T405	18		T572	4		T780	2
values[18]	260	1			T405	15		T572	6		T780	2
values[19]	282	1			T405	18		T572	15		T780	2
values[20]	315	1			T405	22		T572	9		T780	1
values[21]	228	1			T405	11		T572	6		T780	2
values[22]	248	1			T405	12		T572	13		T780	3
values[23]	241	1			T405	12		T572	6		T780	2
values[24]	264	1			T405	12		T572	4		T780	3
values[25]	259	1			T405	12		T572	6		T780	4
values[26]	257	1			T405	14		T572	10		T780	2
values[27]	273	1			T405	9		T572	5		T780	3
values[28]	250	1			T405	11		T572	12		T780	8
values[29]	250	1			T405	10		T572	14		T780	3
values[30]	248	1			T405	11		T572	7		T780	1
values[31]	251	1			T405	21		T572	5		T780	4
values[32]	257	1			T405	16		T572	8		T780	1
values[33]	283	1			T405	11		T572	7		T780	3
values[34]	260	1			T405	8		T572	4		T780	1
values[35]	240	1			T405	9		T572	6		T780	2
values[36]	243	1			T405	13		T572	11		T780	1
values[37]	274	1			T405	9		T572	3		T780	1
values[38]	242	1			T405	16		T572	11		T780	5
values[39]	272	1			T405	8		T572	7		T780	6
values[40]	195	1			T405	10		T572	7		T780	4
values[41]	216	1			T405	18		T572	7		T780	6
values[42]	244	1			T405	23		T572	9		T780	7
values[43]	223	1			T405	21		T572	18		T780	1
values[44]	233	1			T405	13		T572	10		T780	1
values[45]	226	1			T405	19		T572	13		T780	3
values[46]	185	1			T405	12		T572	7		T780	1
values[47]	213	1			T405	13		T572	4		T780	1
values[48]	244	1			T405	17		T572	5		T780	1
values[49]	222	1			T405	9		T572	8		T780	2
values[50]	202	1			T405	7		T572	2		T780	1
values[51]	204	1			T405	9		T572	6		T780	9
values[52]	198	1			T405	19		T572	4		T780	1
values[53]	263	1			T405	14		T572	3		T780	2
values[54]	207	1			T405	23		T572	4		T780	1
values[55]	171	1			T405	10		T572	11		T780	3
values[56]	182	1			T405	10		T572	8		T780	7
values[57]	175	1			T405	17		T572	14		T780	6
values[58]	192	1			T405	36		T572	2		T780	1
values[59]	203	1			T405	15		T572	3		T780	2
values[60]	201	1			T405	12		T572	9		T780	2
values[61]	180	1			T405	8		T572	12		T780	2
values[62]	200	1			T405	9		T572	6		T780	2
values[63]	188	1			T405	12		T572	5		T780	4
values[64]	205	1			T405	8		T572	4		T780	7
values[65]	176	1			T405	9		T572	4		T780	6
values[66]	138	1			T572	2		T780	3		T556	10
values[67]	135	1			T572	7		T780	2		T556	8
values[68]	115	1			T572	4		T780	5		T556	6
values[69]	114	1			T572	5		T780	2		T556	2
values[70]	133	1			T572	16		T780	2		T556	7
values[71]	110	1			T572	3		T780	3		T556	9
values[72]	117	1			T572	13		T780	3		T556	9
values[73]	123	1			T572	13		T780	12		T556	2
values[74]	98	1			T572	3		T780	10		T556	4
values[75]	124	1			T572	16		T780	19		T556	8
values[76]	87	1			T572	5		T780	6		T556	3
values[77]	107	1			T572	4		T780	8		T556	2
values[78]	108	1			T572	3		T780	7		T556	3
values[79]	125	1			T780	13		T556	3		T493	1
values[80]	106	1			T780	9		T556	15		T493	1
values[81]	97	1			T780	12		T556	10		T493	2
values[82]	94	1			T780	6		T556	6		T493	1
values[83]	105	1			T780	3		T556	5		T493	1
values[84]	73	1			T780	5		T556	3		T493	1
values[85]	78	1			T780	4		T556	5		T493	1
values[86]	83	1			T780	8		T556	4		T493	1
values[87]	92	1			T780	8		T556	6		T493	1
values[88]	132	1			T780	14		T556	5		T493	1
values[89]	99	1			T780	7		T556	6		T493	1
values[90]	86	1			T780	4		T556	6		T493	1
values[91]	85	1			T780	4		T556	1		T493	1
values[92]	82	1			T780	3		T556	3		T493	1
values[93]	81	1			T780	7		T556	3		T493	5
values[94]	78	1			T780	8		T556	3		T493	2
values[95]	90	1			T780	9		T556	2		T493	9
values[96]	88	1			T780	9		T556	5		T493	6
values[97]	65	1			T780	4		T556	7		T493	1
values[98]	81	1			T780	3		T556	2		T493	1
values[99]	82	1			T780	4		T556	4		T493	4
values[100]	85	1			T780	3		T556	6		T493	3
values[101]	84	1			T780	5		T556	2		T493	2
values[102]	105	1			T780	1		T556	3		T493	4
values[103]	82	1			T780	2		T556	9		T493	1
values[104]	73	1			T780	2		T556	8		T493	1
values[105]	78	1			T780	11		T556	4		T493	6
values[106]	72	1			T780	12		T556	6		T493	1
values[107]	83	1			T780	4		T556	5		T493	3
values[108]	72	1			T780	4		T556	8		T493	2
values[109]	55	1			T780	3		T556	2		T493	1
values[110]	80	1			T780	3		T556	2		T493	1
values[111]	75	1			T780	5		T556	6		T493	1
values[112]	76	1			T780	4		T556	2		T493	3
values[113]	64	1			T780	3		T556	3		T493	4
values[114]	75	1			T780	2		T556	2		T493	1
values[115]	69	1			T780	3		T556	6		T493	4
values[116]	56	1			T780	1		T556	2		T493	1
values[117]	74	1			T780	4		T556	3		T493	1
values[118]	75	1			T780	3		T556	1		T493	2
values[119]	69	1			T780	5		T556	6		T493	2
values[120]	60	1			T780	4		T556	1		T493	4
values[121]	58	1			T780	2		T556	3		T493	1
values[122]	75	1			T780	4		T556	4		T493	2
values[123]	74	1			T780	1		T556	2		T493	1
values[124]	63	1			T780	3		T493	1		T801	3
values[125]	86	1			T493	1		T801	5		T462	2
values[126]	155	1			T493	3		T801	5		T462	2
values[127]	681	1			T493	23		T801	16		T462	36
values[128]	5043	1			T493	297		T801	6		T462	372