Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	140980	1			T62	94		T63	4		T105	1
values[2]	9868	1			T62	2		T66	139		T234	125
values[3]	4025	1			T66	142		T234	23		T404	111
values[4]	2441	1			T66	69		T234	22		T404	93
values[5]	1526	1			T66	28		T234	11		T404	56
values[6]	1019	1			T66	25		T234	19		T404	13
values[7]	710	1			T66	13		T234	12		T404	4
values[8]	527	1			T234	13		T787	5		T572	4
values[9]	428	1			T234	9		T787	19		T572	15
values[10]	436	1			T234	30		T787	13		T572	11
values[11]	312	1			T234	8		T787	5		T572	4
values[12]	261	1			T234	8		T787	2		T572	7
values[13]	291	1			T234	8		T787	2		T572	5
values[14]	330	1			T234	14		T572	10		T782	1
values[15]	328	1			T234	16		T572	10		T782	1
values[16]	314	1			T234	21		T572	6		T782	1
values[17]	238	1			T234	18		T572	4		T782	1
values[18]	293	1			T234	15		T572	6		T782	1
values[19]	320	1			T234	11		T572	11		T782	1
values[20]	301	1			T234	15		T572	5		T782	1
values[21]	309	1			T234	23		T572	4		T782	1
values[22]	312	1			T234	14		T572	7		T782	1
values[23]	298	1			T234	12		T572	3		T782	1
values[24]	290	1			T234	12		T572	17		T782	1
values[25]	263	1			T234	6		T572	9		T782	1
values[26]	258	1			T234	13		T572	5		T782	1
values[27]	250	1			T234	18		T572	3		T782	1
values[28]	265	1			T234	24		T572	3		T782	1
values[29]	218	1			T234	14		T572	8		T782	1
values[30]	284	1			T234	23		T572	24		T782	1
values[31]	280	1			T234	10		T572	17		T782	1
values[32]	264	1			T234	16		T572	3		T782	1
values[33]	258	1			T234	10		T572	10		T782	1
values[34]	278	1			T234	11		T572	5		T782	1
values[35]	257	1			T234	16		T572	8		T782	1
values[36]	248	1			T234	10		T572	6		T782	1
values[37]	275	1			T234	10		T572	4		T782	1
values[38]	244	1			T234	13		T572	7		T782	1
values[39]	313	1			T234	15		T572	12		T782	1
values[40]	291	1			T234	27		T572	3		T782	1
values[41]	228	1			T234	16		T572	8		T782	1
values[42]	241	1			T234	20		T572	6		T782	1
values[43]	250	1			T234	13		T572	9		T782	1
values[44]	231	1			T234	10		T572	9		T782	1
values[45]	219	1			T234	8		T572	17		T782	1
values[46]	216	1			T234	12		T572	5		T782	1
values[47]	273	1			T234	11		T572	8		T782	1
values[48]	225	1			T234	11		T572	9		T782	1
values[49]	229	1			T234	15		T572	3		T782	1
values[50]	237	1			T234	20		T572	4		T782	1
values[51]	250	1			T234	14		T572	6		T782	1
values[52]	235	1			T234	17		T572	8		T782	1
values[53]	242	1			T234	14		T572	7		T782	1
values[54]	226	1			T234	22		T572	12		T782	1
values[55]	248	1			T234	15		T572	5		T782	1
values[56]	243	1			T234	23		T572	9		T782	1
values[57]	225	1			T234	17		T572	18		T782	1
values[58]	226	1			T234	18		T572	4		T782	1
values[59]	228	1			T234	24		T572	7		T782	1
values[60]	214	1			T234	14		T572	5		T782	1
values[61]	161	1			T234	10		T572	2		T782	1
values[62]	182	1			T234	19		T572	9		T782	1
values[63]	149	1			T234	18		T572	5		T782	1
values[64]	157	1			T234	9		T572	5		T782	1
values[65]	171	1			T234	16		T572	5		T782	1
values[66]	152	1			T234	14		T572	6		T782	1
values[67]	127	1			T234	7		T782	1		T418	10
values[68]	147	1			T234	10		T782	1		T418	10
values[69]	136	1			T234	12		T782	1		T418	2
values[70]	128	1			T234	4		T782	1		T778	1
values[71]	123	1			T234	3		T782	1		T778	1
values[72]	115	1			T234	5		T782	1		T778	1
values[73]	87	1			T234	8		T782	1		T778	1
values[74]	95	1			T234	11		T782	1		T778	1
values[75]	81	1			T782	1		T778	1		T462	1
values[76]	75	1			T782	1		T778	1		T462	1
values[77]	78	1			T782	1		T778	1		T462	1
values[78]	102	1			T782	1		T778	1		T462	1
values[79]	82	1			T782	1		T778	1		T462	1
values[80]	74	1			T782	3		T778	1		T462	1
values[81]	48	1			T782	2		T778	1		T462	1
values[82]	64	1			T782	10		T778	1		T462	1
values[83]	52	1			T782	2		T778	1		T462	1
values[84]	57	1			T782	2		T778	1		T462	1
values[85]	68	1			T782	8		T778	1		T462	1
values[86]	62	1			T782	1		T778	1		T462	1
values[87]	62	1			T782	4		T778	1		T462	1
values[88]	52	1			T782	4		T778	1		T462	1
values[89]	57	1			T782	1		T778	1		T462	2
values[90]	63	1			T782	3		T778	1		T462	1
values[91]	58	1			T782	1		T778	1		T462	1
values[92]	43	1			T782	2		T778	1		T462	1
values[93]	55	1			T782	4		T778	1		T462	1
values[94]	63	1			T782	3		T778	1		T462	1
values[95]	53	1			T782	2		T778	1		T462	1
values[96]	53	1			T782	1		T778	1		T462	1
values[97]	54	1			T782	1		T778	1		T462	1
values[98]	65	1			T782	2		T778	1		T462	2
values[99]	54	1			T782	6		T778	1		T462	1
values[100]	51	1			T782	3		T778	1		T462	3
values[101]	59	1			T782	8		T778	1		T462	2
values[102]	42	1			T782	2		T778	1		T462	1
values[103]	49	1			T782	6		T778	1		T462	1
values[104]	59	1			T782	2		T778	1		T462	1
values[105]	42	1			T782	1		T778	1		T462	2
values[106]	58	1			T782	5		T778	1		T462	1
values[107]	50	1			T782	3		T778	1		T462	1
values[108]	39	1			T782	2		T778	1		T462	1
values[109]	47	1			T782	1		T778	1		T462	2
values[110]	46	1			T782	1		T778	1		T462	3
values[111]	50	1			T782	1		T778	1		T462	6
values[112]	61	1			T782	3		T778	1		T462	3
values[113]	32	1			T782	1		T778	1		T462	1
values[114]	49	1			T782	6		T778	2		T462	2
values[115]	43	1			T782	2		T778	3		T462	2
values[116]	45	1			T782	4		T778	2		T462	2
values[117]	78	1			T782	5		T778	3		T462	8
values[118]	46	1			T782	1		T778	4		T462	1
values[119]	36	1			T782	2		T778	1		T462	1
values[120]	42	1			T782	3		T778	1		T462	1
values[121]	36	1			T782	2		T778	1		T462	1
values[122]	33	1			T782	1		T778	1		T462	1
values[123]	32	1			T782	1		T778	1		T462	1
values[124]	47	1			T782	1		T778	1		T462	1
values[125]	48	1			T782	3		T778	1		T462	4
values[126]	80	1			T782	1		T778	4		T462	2
values[127]	519	1			T782	24		T778	28		T462	35
values[128]	4611	1			T782	263		T778	323		T462	266