Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145013	1			T62	91		T63	9		T105	4
values[2]	10189	1			T62	1		T234	37		T395	167
values[3]	5189	1			T234	48		T395	130		T484	1
values[4]	3158	1			T234	28		T395	38		T787	38
values[5]	1953	1			T234	27		T395	11		T787	16
values[6]	1359	1			T234	36		T395	6		T787	22
values[7]	1033	1			T234	27		T787	18		T789	11
values[8]	771	1			T234	21		T787	5		T789	3
values[9]	618	1			T234	23		T556	2		T493	1
values[10]	644	1			T234	26		T556	9		T493	1
values[11]	535	1			T234	22		T556	9		T493	1
values[12]	602	1			T234	19		T556	4		T493	1
values[13]	573	1			T234	16		T556	16		T493	1
values[14]	589	1			T234	34		T556	21		T493	1
values[15]	540	1			T234	18		T556	4		T493	1
values[16]	496	1			T234	28		T556	1		T493	1
values[17]	525	1			T234	15		T556	2		T493	1
values[18]	513	1			T234	18		T556	13		T493	1
values[19]	519	1			T234	16		T556	8		T493	1
values[20]	462	1			T234	21		T556	4		T493	1
values[21]	498	1			T234	19		T556	3		T493	1
values[22]	506	1			T234	29		T556	5		T493	1
values[23]	538	1			T234	13		T556	9		T493	1
values[24]	510	1			T234	29		T556	5		T493	1
values[25]	542	1			T234	35		T556	5		T493	1
values[26]	470	1			T234	27		T556	2		T493	1
values[27]	443	1			T234	17		T556	2		T493	1
values[28]	405	1			T234	16		T556	2		T493	1
values[29]	358	1			T234	22		T556	2		T493	1
values[30]	395	1			T234	8		T556	2		T493	1
values[31]	363	1			T234	10		T556	2		T493	1
values[32]	400	1			T234	22		T556	3		T493	1
values[33]	338	1			T234	9		T556	1		T493	1
values[34]	417	1			T234	11		T556	2		T493	1
values[35]	373	1			T234	19		T556	2		T493	1
values[36]	375	1			T234	5		T556	3		T493	1
values[37]	388	1			T234	19		T556	2		T493	1
values[38]	433	1			T234	11		T556	3		T493	1
values[39]	458	1			T234	11		T556	1		T493	1
values[40]	355	1			T556	1		T493	1		T805	1
values[41]	369	1			T556	3		T493	1		T805	1
values[42]	381	1			T556	3		T493	1		T805	1
values[43]	362	1			T556	3		T493	1		T805	1
values[44]	310	1			T556	1		T493	1		T805	1
values[45]	285	1			T556	2		T493	1		T805	2
values[46]	298	1			T556	4		T493	1		T805	1
values[47]	260	1			T556	9		T493	1		T805	1
values[48]	245	1			T556	4		T493	1		T805	1
values[49]	252	1			T556	2		T493	1		T805	1
values[50]	215	1			T556	1		T493	1		T805	1
values[51]	203	1			T556	5		T493	1		T805	1
values[52]	146	1			T556	6		T493	1		T805	1
values[53]	143	1			T556	2		T493	1		T805	1
values[54]	166	1			T556	11		T493	1		T805	1
values[55]	153	1			T556	12		T493	1		T805	1
values[56]	153	1			T556	5		T493	1		T805	1
values[57]	134	1			T556	3		T493	1		T805	1
values[58]	111	1			T556	11		T493	1		T805	1
values[59]	78	1			T556	3		T493	2		T805	1
values[60]	82	1			T556	5		T493	1		T805	1
values[61]	88	1			T556	1		T493	1		T805	1
values[62]	106	1			T556	5		T493	1		T805	1
values[63]	162	1			T556	17		T493	1		T805	1
values[64]	114	1			T556	15		T493	1		T805	1
values[65]	121	1			T556	4		T493	1		T805	1
values[66]	153	1			T493	1		T805	1		T806	1
values[67]	96	1			T493	1		T805	1		T806	1
values[68]	97	1			T493	1		T805	1		T806	1
values[69]	95	1			T493	1		T805	1		T806	1
values[70]	96	1			T493	1		T805	1		T806	1
values[71]	89	1			T493	1		T805	1		T806	1
values[72]	101	1			T493	1		T805	1		T806	1
values[73]	99	1			T493	1		T805	1		T806	1
values[74]	102	1			T493	1		T805	3		T806	1
values[75]	97	1			T493	1		T805	5		T806	1
values[76]	115	1			T493	1		T805	1		T806	1
values[77]	130	1			T493	1		T805	1		T806	1
values[78]	101	1			T493	1		T805	2		T806	1
values[79]	93	1			T493	1		T805	5		T806	2
values[80]	91	1			T493	1		T805	3		T806	1
values[81]	92	1			T493	1		T805	9		T806	1
values[82]	88	1			T493	1		T805	4		T806	1
values[83]	81	1			T493	1		T805	6		T806	1
values[84]	88	1			T493	1		T805	1		T806	1
values[85]	99	1			T493	1		T805	6		T806	1
values[86]	108	1			T493	1		T805	6		T806	1
values[87]	104	1			T493	1		T805	1		T806	1
values[88]	82	1			T493	1		T805	1		T806	1
values[89]	119	1			T493	1		T805	3		T806	1
values[90]	109	1			T493	1		T805	1		T806	1
values[91]	104	1			T493	3		T805	4		T806	1
values[92]	122	1			T493	7		T805	1		T806	1
values[93]	98	1			T493	1		T805	2		T806	1
values[94]	96	1			T493	3		T805	1		T806	1
values[95]	106	1			T493	1		T805	2		T806	1
values[96]	88	1			T493	1		T805	2		T806	1
values[97]	104	1			T493	7		T805	1		T806	1
values[98]	78	1			T493	8		T805	5		T806	1
values[99]	70	1			T493	4		T805	2		T806	1
values[100]	70	1			T493	1		T805	4		T806	1
values[101]	68	1			T493	3		T805	5		T806	1
values[102]	89	1			T493	5		T805	1		T806	1
values[103]	80	1			T493	2		T805	2		T806	1
values[104]	102	1			T493	5		T805	2		T806	1
values[105]	97	1			T493	5		T805	2		T806	1
values[106]	81	1			T493	3		T805	5		T806	5
values[107]	84	1			T493	2		T805	3		T806	1
values[108]	94	1			T493	3		T805	1		T806	4
values[109]	63	1			T493	5		T805	2		T806	1
values[110]	72	1			T493	2		T805	5		T806	2
values[111]	59	1			T493	2		T805	2		T806	2
values[112]	62	1			T493	3		T805	1		T806	1
values[113]	65	1			T493	1		T805	2		T806	1
values[114]	61	1			T493	2		T805	2		T806	3
values[115]	71	1			T493	3		T805	1		T806	4
values[116]	64	1			T493	1		T805	1		T806	1
values[117]	59	1			T493	4		T805	1		T806	2
values[118]	71	1			T493	1		T805	1		T806	1
values[119]	73	1			T493	4		T805	3		T806	2
values[120]	81	1			T493	3		T805	2		T806	1
values[121]	62	1			T493	2		T805	1		T806	1
values[122]	68	1			T493	1		T805	2		T806	1
values[123]	71	1			T493	1		T805	2		T806	3
values[124]	76	1			T493	5		T805	2		T806	4
values[125]	67	1			T493	1		T805	3		T806	1
values[126]	153	1			T493	6		T805	9		T806	3
values[127]	1578	1			T493	39		T805	54		T806	43
values[128]	7911	1			T493	234		T805	227		T806	244