Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	158177	1			T62	94		T63	5		T64	1
values[2]	4153	1			T62	2		T64	5		T66	2
values[3]	2027	1			T64	3		T66	1		T395	22
values[4]	1713	1			T64	3		T66	2		T395	16
values[5]	1503	1			T64	5		T66	2		T395	11
values[6]	1277	1			T64	4		T66	4		T395	3
values[7]	1065	1			T64	3		T66	1		T395	6
values[8]	982	1			T64	1		T66	1		T395	1
values[9]	923	1			T64	1		T66	2		T395	12
values[10]	856	1			T64	3		T66	2		T395	41
values[11]	876	1			T64	2		T66	1		T395	23
values[12]	853	1			T64	1		T66	2		T395	20
values[13]	836	1			T64	1		T66	4		T395	20
values[14]	667	1			T64	2		T66	3		T395	12
values[15]	603	1			T64	1		T66	2		T395	13
values[16]	612	1			T64	1		T66	2		T395	18
values[17]	597	1			T64	5		T66	1		T395	13
values[18]	481	1			T64	1		T66	3		T395	4
values[19]	403	1			T64	4		T66	2		T402	25
values[20]	313	1			T64	1		T66	1		T402	20
values[21]	363	1			T64	1		T66	3		T402	18
values[22]	336	1			T64	7		T66	3		T402	34
values[23]	299	1			T64	4		T66	1		T402	39
values[24]	294	1			T64	3		T66	3		T402	36
values[25]	294	1			T64	4		T66	1		T402	12
values[26]	272	1			T64	2		T66	2		T402	9
values[27]	242	1			T64	4		T66	4		T402	7
values[28]	246	1			T64	3		T66	2		T402	16
values[29]	265	1			T64	3		T66	6		T402	19
values[30]	244	1			T64	1		T66	4		T402	36
values[31]	225	1			T64	3		T66	5		T402	16
values[32]	224	1			T64	6		T66	8		T402	21
values[33]	193	1			T64	7		T66	2		T402	13
values[34]	155	1			T64	5		T66	6		T402	5
values[35]	143	1			T64	8		T66	2		T435	1
values[36]	110	1			T64	3		T66	2		T435	1
values[37]	89	1			T64	2		T66	1		T435	1
values[38]	98	1			T64	2		T66	3		T435	1
values[39]	80	1			T64	1		T66	4		T435	1
values[40]	78	1			T64	2		T66	1		T435	1
values[41]	71	1			T64	4		T66	1		T435	1
values[42]	60	1			T64	3		T66	1		T435	1
values[43]	60	1			T64	2		T66	4		T435	1
values[44]	64	1			T64	1		T66	2		T435	1
values[45]	57	1			T64	2		T66	1		T435	1
values[46]	57	1			T64	1		T66	3		T435	1
values[47]	62	1			T64	4		T66	1		T435	1
values[48]	64	1			T64	2		T66	2		T435	1
values[49]	59	1			T64	1		T66	3		T435	1
values[50]	51	1			T64	1		T66	1		T435	1
values[51]	57	1			T64	1		T66	3		T435	1
values[52]	58	1			T64	3		T66	3		T435	1
values[53]	64	1			T64	2		T66	3		T435	1
values[54]	54	1			T64	1		T66	3		T435	1
values[55]	60	1			T64	2		T66	3		T435	1
values[56]	65	1			T64	1		T66	3		T435	1
values[57]	63	1			T64	2		T66	2		T435	1
values[58]	58	1			T64	1		T66	4		T435	1
values[59]	72	1			T64	7		T66	3		T435	1
values[60]	59	1			T64	5		T66	1		T435	1
values[61]	63	1			T64	8		T66	1		T435	1
values[62]	65	1			T64	8		T66	3		T435	1
values[63]	60	1			T64	5		T66	2		T435	1
values[64]	61	1			T64	4		T66	4		T435	1
values[65]	61	1			T64	7		T66	1		T435	1
values[66]	48	1			T64	2		T66	3		T435	1
values[67]	68	1			T64	4		T66	3		T435	1
values[68]	64	1			T64	4		T66	2		T435	1
values[69]	55	1			T64	4		T66	1		T435	1
values[70]	53	1			T64	1		T66	2		T435	1
values[71]	64	1			T64	2		T66	3		T435	1
values[72]	57	1			T64	2		T66	2		T435	1
values[73]	77	1			T64	3		T66	3		T435	1
values[74]	64	1			T64	1		T66	3		T435	1
values[75]	60	1			T64	2		T66	3		T435	1
values[76]	71	1			T64	1		T66	2		T435	1
values[77]	66	1			T64	1		T66	3		T435	1
values[78]	66	1			T64	2		T66	3		T435	1
values[79]	84	1			T64	2		T66	2		T435	1
values[80]	78	1			T64	1		T66	5		T435	1
values[81]	66	1			T64	2		T66	6		T435	1
values[82]	78	1			T64	5		T66	4		T435	1
values[83]	82	1			T64	3		T66	3		T435	1
values[84]	98	1			T64	7		T66	3		T435	1
values[85]	83	1			T64	7		T66	2		T435	1
values[86]	82	1			T64	3		T66	3		T435	1
values[87]	81	1			T64	6		T66	2		T435	1
values[88]	89	1			T64	12		T66	5		T435	1
values[89]	81	1			T64	4		T66	3		T435	1
values[90]	78	1			T64	2		T66	5		T435	1
values[91]	72	1			T64	2		T66	5		T435	2
values[92]	66	1			T64	1		T66	2		T435	1
values[93]	72	1			T64	3		T66	1		T435	1
values[94]	78	1			T64	5		T66	5		T435	1
values[95]	93	1			T64	3		T66	3		T435	1
values[96]	73	1			T64	5		T66	2		T435	1
values[97]	94	1			T64	4		T66	6		T435	1
values[98]	97	1			T64	5		T66	1		T435	1
values[99]	94	1			T64	5		T66	3		T435	1
values[100]	80	1			T64	3		T66	1		T435	1
values[101]	91	1			T64	4		T66	1		T435	1
values[102]	106	1			T64	2		T66	1		T435	1
values[103]	98	1			T64	5		T66	2		T435	1
values[104]	90	1			T64	4		T66	1		T435	1
values[105]	83	1			T64	2		T66	1		T435	1
values[106]	93	1			T64	3		T66	1		T435	1
values[107]	100	1			T64	1		T66	2		T435	1
values[108]	102	1			T64	7		T66	5		T435	1
values[109]	92	1			T64	2		T66	7		T435	1
values[110]	111	1			T64	5		T66	6		T435	1
values[111]	97	1			T64	2		T66	8		T435	1
values[112]	97	1			T64	2		T66	5		T435	1
values[113]	114	1			T64	3		T66	2		T435	1
values[114]	113	1			T64	7		T66	3		T435	1
values[115]	110	1			T64	7		T66	3		T435	1
values[116]	114	1			T64	4		T66	10		T435	1
values[117]	123	1			T64	6		T66	7		T435	1
values[118]	118	1			T64	2		T66	3		T435	3
values[119]	128	1			T64	2		T66	2		T435	2
values[120]	130	1			T64	2		T66	8		T435	1
values[121]	106	1			T64	1		T66	4		T435	1
values[122]	133	1			T64	1		T66	7		T435	3
values[123]	190	1			T64	4		T66	11		T435	4
values[124]	246	1			T64	13		T66	26		T435	2
values[125]	489	1			T64	25		T66	52		T435	2
values[126]	894	1			T64	27		T66	49		T435	15
values[127]	2933	1			T64	16		T66	40		T435	156
values[128]	4793	1			T64	1		T435	286		T782	356