Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	159694	1			T62	87		T63	7		T64	1
values[2]	4205	1			T62	3		T64	2		T66	1
values[3]	1930	1			T64	1		T404	39		T413	11
values[4]	1384	1			T64	1		T404	4		T413	21
values[5]	1120	1			T64	3		T413	15		T791	2
values[6]	829	1			T64	2		T413	5		T791	3
values[7]	781	1			T64	3		T791	2		T556	2
values[8]	780	1			T64	1		T791	6		T419	4
values[9]	617	1			T64	3		T791	2		T462	1
values[10]	588	1			T64	3		T791	1		T462	1
values[11]	525	1			T64	3		T791	1		T462	1
values[12]	449	1			T64	1		T791	3		T462	1
values[13]	360	1			T64	3		T791	5		T462	1
values[14]	328	1			T64	5		T791	3		T462	1
values[15]	369	1			T64	3		T791	2		T462	1
values[16]	373	1			T64	1		T791	6		T462	1
values[17]	339	1			T64	2		T791	2		T462	1
values[18]	331	1			T64	3		T791	4		T462	1
values[19]	324	1			T64	2		T791	4		T462	1
values[20]	261	1			T64	3		T791	1		T462	1
values[21]	210	1			T64	3		T791	5		T462	1
values[22]	209	1			T64	2		T791	3		T462	1
values[23]	191	1			T64	2		T791	1		T462	1
values[24]	207	1			T64	3		T791	2		T462	1
values[25]	160	1			T64	1		T791	4		T462	1
values[26]	176	1			T64	1		T791	4		T462	1
values[27]	163	1			T64	4		T791	5		T462	1
values[28]	165	1			T64	2		T791	6		T462	1
values[29]	153	1			T64	2		T791	1		T462	1
values[30]	136	1			T64	2		T791	2		T462	1
values[31]	138	1			T64	3		T791	1		T462	1
values[32]	110	1			T64	2		T791	4		T462	1
values[33]	70	1			T64	1		T791	3		T462	1
values[34]	52	1			T64	1		T791	4		T462	1
values[35]	53	1			T64	2		T791	3		T462	1
values[36]	44	1			T64	2		T791	3		T462	1
values[37]	62	1			T64	2		T791	5		T462	1
values[38]	45	1			T64	1		T791	6		T462	1
values[39]	49	1			T64	3		T791	4		T462	1
values[40]	45	1			T64	3		T791	2		T462	1
values[41]	46	1			T64	1		T791	1		T462	1
values[42]	55	1			T64	1		T791	4		T462	1
values[43]	51	1			T64	2		T791	1		T462	1
values[44]	45	1			T64	1		T791	1		T462	1
values[45]	44	1			T64	2		T791	5		T462	1
values[46]	46	1			T64	3		T791	1		T462	1
values[47]	43	1			T64	3		T791	2		T462	1
values[48]	68	1			T64	1		T791	6		T462	1
values[49]	53	1			T64	1		T791	2		T462	1
values[50]	54	1			T64	4		T791	1		T462	1
values[51]	44	1			T64	2		T791	2		T462	1
values[52]	43	1			T64	2		T791	3		T462	1
values[53]	49	1			T64	8		T791	1		T462	1
values[54]	48	1			T64	5		T791	1		T462	1
values[55]	45	1			T64	2		T791	1		T462	1
values[56]	58	1			T64	1		T791	5		T462	1
values[57]	45	1			T64	2		T791	2		T462	1
values[58]	44	1			T64	2		T791	3		T462	1
values[59]	45	1			T64	2		T791	2		T462	1
values[60]	43	1			T64	1		T791	1		T462	1
values[61]	47	1			T64	3		T791	2		T462	1
values[62]	58	1			T64	4		T791	2		T462	1
values[63]	62	1			T64	2		T791	1		T462	1
values[64]	49	1			T64	1		T791	2		T462	1
values[65]	47	1			T64	4		T791	2		T462	1
values[66]	44	1			T64	4		T791	1		T462	1
values[67]	45	1			T64	2		T791	2		T462	1
values[68]	55	1			T64	5		T791	1		T462	1
values[69]	49	1			T64	3		T791	3		T462	1
values[70]	50	1			T64	3		T791	3		T462	1
values[71]	57	1			T64	1		T791	2		T462	1
values[72]	55	1			T64	2		T791	3		T462	1
values[73]	42	1			T64	4		T791	1		T462	1
values[74]	39	1			T64	1		T791	3		T462	1
values[75]	43	1			T64	8		T791	1		T462	1
values[76]	59	1			T64	9		T791	1		T462	1
values[77]	50	1			T64	3		T791	4		T462	1
values[78]	52	1			T64	1		T791	3		T462	1
values[79]	44	1			T64	2		T791	1		T462	1
values[80]	45	1			T64	2		T791	1		T462	1
values[81]	43	1			T64	1		T791	4		T462	1
values[82]	46	1			T64	1		T791	2		T462	1
values[83]	43	1			T64	1		T791	1		T462	1
values[84]	49	1			T64	6		T791	1		T462	1
values[85]	61	1			T64	3		T791	5		T462	1
values[86]	53	1			T64	3		T791	5		T462	4
values[87]	63	1			T64	4		T791	1		T462	11
values[88]	57	1			T64	6		T791	5		T462	3
values[89]	62	1			T64	3		T791	1		T462	3
values[90]	53	1			T64	2		T791	2		T462	4
values[91]	53	1			T64	2		T791	2		T462	4
values[92]	63	1			T64	5		T791	1		T462	1
values[93]	68	1			T64	3		T791	3		T462	2
values[94]	79	1			T64	5		T791	4		T462	3
values[95]	83	1			T64	5		T791	1		T462	3
values[96]	90	1			T64	3		T791	4		T462	2
values[97]	91	1			T64	4		T791	1		T462	3
values[98]	78	1			T64	3		T791	3		T462	2
values[99]	84	1			T64	2		T791	2		T462	2
values[100]	85	1			T64	1		T791	4		T462	2
values[101]	67	1			T64	2		T791	5		T462	2
values[102]	87	1			T64	3		T791	2		T462	2
values[103]	67	1			T64	1		T791	4		T462	4
values[104]	79	1			T64	5		T791	7		T462	2
values[105]	63	1			T64	2		T791	3		T462	2
values[106]	78	1			T64	2		T791	3		T462	4
values[107]	78	1			T64	3		T791	4		T462	2
values[108]	67	1			T64	4		T791	3		T462	2
values[109]	72	1			T64	1		T791	2		T462	2
values[110]	66	1			T64	1		T791	3		T462	3
values[111]	85	1			T64	4		T791	2		T462	9
values[112]	90	1			T64	2		T791	5		T462	3
values[113]	77	1			T64	4		T791	3		T462	1
values[114]	84	1			T64	1		T791	4		T462	2
values[115]	76	1			T64	2		T791	2		T462	1
values[116]	76	1			T64	2		T791	1		T462	1
values[117]	79	1			T64	3		T791	2		T462	1
values[118]	97	1			T64	7		T791	2		T462	3
values[119]	95	1			T64	7		T791	3		T462	3
values[120]	97	1			T64	8		T791	6		T462	1
values[121]	101	1			T64	7		T791	7		T462	1
values[122]	95	1			T64	9		T791	7		T462	2
values[123]	116	1			T64	21		T791	2		T462	1
values[124]	145	1			T64	31		T791	6		T462	2
values[125]	313	1			T64	45		T791	46		T462	2
values[126]	679	1			T64	82		T791	73		T462	8
values[127]	2563	1			T64	44		T791	37		T462	106
values[128]	4667	1			T64	5		T791	3		T462	195