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Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T63 1 T484 1 T785 1
small_delay 665 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T63 1 T647 1 T573 1
small_delay 965 1 T62 1 T64 1 T105 1
zero 635 1 T72 1 T234 1 T409 1

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