Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	501	1			T64	1		T234	3		T395	1
all_values[1]	480	1			T234	3		T796	1		T404	5
all_values[2]	515	1			T234	3		T395	1		T796	1
all_values[3]	500	1			T234	3		T395	1		T455	1
all_values[4]	437	1			T64	2		T66	1		T234	2
all_values[5]	482	1			T234	5		T395	1		T560	1
all_values[6]	473	1			T64	1		T234	2		T404	2
all_values[7]	488	1			T234	5		T395	1		T796	1
all_values[8]	458	1			T64	1		T234	3		T395	2
all_values[9]	539	1			T234	2		T395	2		T404	7
all_values[10]	474	1			T234	2		T796	1		T404	9
all_values[11]	436	1			T105	1		T234	3		T404	2
all_values[12]	465	1			T234	3		T395	1		T404	9
all_values[13]	473	1			T64	1		T234	2		T404	2
all_values[14]	489	1			T234	2		T404	4		T830	1
all_values[15]	428	1			T234	3		T796	1		T404	3
all_values[16]	506	1			T64	1		T66	1		T234	1
all_values[17]	487	1			T66	1		T234	1		T395	2
all_values[18]	496	1			T64	1		T105	1		T234	6
all_values[19]	507	1			T64	1		T105	1		T234	1
all_values[20]	497	1			T64	1		T105	2		T234	6
all_values[21]	487	1			T64	1		T66	1		T234	2
all_values[22]	490	1			T64	2		T234	1		T796	2
all_values[23]	502	1			T234	1		T395	1		T404	3
all_values[24]	432	1			T395	2		T785	1		T796	1
all_values[25]	465	1			T234	3		T395	2		T404	5
all_values[26]	498	1			T64	2		T234	5		T796	1
all_values[27]	555	1			T234	3		T395	1		T404	2
all_values[28]	498	1			T66	1		T234	1		T796	2
all_values[29]	452	1			T234	1		T404	2		T455	2
all_values[30]	505	1			T105	1		T234	4		T395	1
all_values[31]	455	1			T64	1		T66	2		T234	1
all_values[32]	519	1			T64	1		T66	1		T234	5
all_values[33]	455	1			T66	1		T234	5		T796	1
all_values[34]	469	1			T66	1		T234	4		T395	1
all_values[35]	475	1			T105	1		T234	2		T395	3
all_values[36]	440	1			T105	1		T234	2		T404	3
all_values[37]	491	1			T66	1		T234	4		T404	3
all_values[38]	491	1			T234	3		T395	3		T796	1
all_values[39]	489	1			T66	1		T234	2		T395	2
all_values[40]	486	1			T234	3		T395	1		T785	1
all_values[41]	495	1			T234	1		T395	1		T796	1
all_values[42]	463	1			T64	1		T234	7		T395	1
all_values[43]	456	1			T66	1		T234	3		T796	1
all_values[44]	515	1			T66	3		T404	3		T455	1
all_values[45]	471	1			T66	2		T234	4		T395	2
all_values[46]	525	1			T66	1		T234	3		T785	1
all_values[47]	472	1			T234	3		T796	1		T404	3
all_values[48]	472	1			T64	1		T234	8		T395	2
all_values[49]	445	1			T234	5		T404	3		T455	1