Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3661	1			T105	4		T234	28		T395	1
all_values[1]	3590	1			T105	1		T234	36		T395	5
all_values[2]	3644	1			T105	6		T234	32		T395	1
all_values[3]	3676	1			T105	3		T234	30		T395	3
all_values[4]	3658	1			T105	1		T234	27		T395	1
all_values[5]	3664	1			T234	28		T395	1		T409	1
all_values[6]	3670	1			T105	1		T234	24		T395	1
all_values[7]	3722	1			T105	3		T234	40		T395	5
all_values[8]	3583	1			T105	3		T234	32		T395	1
all_values[9]	3649	1			T105	2		T234	42		T395	3
all_values[10]	3729	1			T105	3		T234	37		T395	2
all_values[11]	3568	1			T105	2		T234	22		T395	3
all_values[12]	3591	1			T105	2		T234	28		T395	3
all_values[13]	3618	1			T105	6		T234	34		T395	3
all_values[14]	3638	1			T105	1		T234	28		T395	3
all_values[15]	3633	1			T105	2		T234	30		T395	1
all_values[16]	3686	1			T105	2		T234	28		T395	3
all_values[17]	3656	1			T105	2		T234	30		T395	5
all_values[18]	3587	1			T105	3		T234	32		T395	3
all_values[19]	3606	1			T105	2		T234	26		T395	2
all_values[20]	3760	1			T234	41		T395	2		T409	2
all_values[21]	3606	1			T105	4		T234	19		T395	5
all_values[22]	3579	1			T105	2		T234	22		T395	1
all_values[23]	3724	1			T105	1		T234	28		T395	2
all_values[24]	3661	1			T105	3		T234	32		T395	4
all_values[25]	3646	1			T105	4		T234	36		T395	5
all_values[26]	3578	1			T105	2		T234	33		T395	4
all_values[27]	3679	1			T105	2		T234	47		T395	4
all_values[28]	3670	1			T234	36		T395	2		T410	3
all_values[29]	3684	1			T105	7		T234	27		T395	1
all_values[30]	3692	1			T105	4		T234	33		T395	1
all_values[31]	3588	1			T105	3		T234	22		T395	3
all_values[32]	3554	1			T105	4		T234	32		T395	2
all_values[33]	3758	1			T105	4		T234	32		T395	1
all_values[34]	3634	1			T234	33		T395	1		T448	4
all_values[35]	3639	1			T105	2		T234	20		T395	1
all_values[36]	3589	1			T105	2		T234	31		T395	5
all_values[37]	3621	1			T105	2		T234	27		T395	2
all_values[38]	3749	1			T105	1		T234	23		T395	5
all_values[39]	3646	1			T105	1		T234	30		T395	1
all_values[40]	3704	1			T105	5		T234	34		T395	1
all_values[41]	3638	1			T105	2		T234	33		T395	1
all_values[42]	3576	1			T234	28		T395	4		T409	1
all_values[43]	3540	1			T105	4		T234	26		T395	3
all_values[44]	3759	1			T105	5		T234	34		T395	4
all_values[45]	3567	1			T105	2		T234	40		T395	2
all_values[46]	3764	1			T105	4		T234	29		T395	3
all_values[47]	3617	1			T105	2		T234	19		T395	1
all_values[48]	3544	1			T105	1		T234	25		T395	2
all_values[49]	3574	1			T105	1		T234	21		T395	1
all_values[50]	3600	1			T105	4		T234	19		T395	1
all_values[51]	3686	1			T105	3		T234	39		T395	5
all_values[52]	3656	1			T105	7		T234	33		T395	3
all_values[53]	3595	1			T105	4		T234	25		T395	3
all_values[54]	3566	1			T234	35		T395	3		T410	5
all_values[55]	3637	1			T105	4		T234	30		T395	1
all_values[56]	3566	1			T105	2		T234	25		T409	1
all_values[57]	3703	1			T105	2		T234	26		T395	2
all_values[58]	3719	1			T105	5		T234	44		T395	2
all_values[59]	3555	1			T105	4		T234	32		T395	5
all_values[60]	3639	1			T105	2		T234	28		T395	4
all_values[61]	3683	1			T105	1		T234	38		T410	2
all_values[62]	3605	1			T105	1		T234	33		T395	3
all_values[63]	3636	1			T105	1		T234	29		T395	1