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 LINE       36663
 EXPRESSION (addr_hit[558] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T65,T425,T487
1	1	1	Covered	T51,T54,T179

 LINE       36665
 EXPRESSION (addr_hit[559] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T540,T528,T442
1	1	1	Covered	T13,T51,T57

 LINE       36668
 EXPRESSION (addr_hit[560] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T495,T418,T499
1	1	1	Covered	T51,T54,T481

 LINE       36671
 EXPRESSION (addr_hit[561] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T558,T495,T499
1	1	1	Covered	T51,T54,T395

 LINE       36674
 EXPRESSION (addr_hit[562] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T496,T450,T499
1	1	1	Covered	T51,T54,T395

 LINE       36677
 EXPRESSION (addr_hit[563] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T460,T534,T495
1	1	1	Covered	T51,T54,T55

 LINE       36680
 EXPRESSION (addr_hit[564] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T499,T486,T475
1	1	1	Covered	T16,T49,T19

 LINE       36683
 EXPRESSION (addr_hit[565] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T486,T439,T501
1	1	1	Covered	T51,T54,T62

 LINE       36686
 EXPRESSION (addr_hit[566] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T65,T395,T535
1	1	1	Covered	T51,T54,T482

 LINE       36689
 EXPRESSION (addr_hit[567] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T499,T501,T588
1	1	1	Covered	T13,T16,T49

 LINE       40162
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T13,T16,T49