Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	133588	1			T61	93		T62	1		T63	239
values[2]	8704	1			T61	4		T62	1		T63	4
values[3]	3504	1			T62	1		T230	31		T403	110
values[4]	2216	1			T62	1		T230	23		T403	45
values[5]	1451	1			T62	1		T230	9		T403	24
values[6]	1200	1			T62	1		T230	10		T403	6
values[7]	950	1			T62	1		T230	7		T406	4
values[8]	810	1			T62	1		T230	8		T406	8
values[9]	539	1			T62	1		T230	7		T406	3
values[10]	537	1			T62	1		T230	10		T406	11
values[11]	504	1			T62	1		T230	7		T406	9
values[12]	439	1			T62	1		T230	12		T406	4
values[13]	435	1			T62	1		T230	9		T406	8
values[14]	355	1			T62	1		T230	3		T406	12
values[15]	346	1			T62	1		T230	5		T406	15
values[16]	347	1			T62	1		T230	5		T406	5
values[17]	341	1			T62	1		T230	10		T406	7
values[18]	399	1			T62	1		T230	8		T406	8
values[19]	383	1			T62	1		T230	9		T406	7
values[20]	370	1			T62	1		T230	9		T406	6
values[21]	337	1			T62	1		T230	6		T406	10
values[22]	377	1			T62	1		T230	8		T406	12
values[23]	331	1			T62	1		T230	10		T406	2
values[24]	328	1			T62	1		T230	6		T406	14
values[25]	298	1			T62	1		T230	4		T406	3
values[26]	331	1			T62	1		T230	5		T406	3
values[27]	293	1			T62	1		T230	3		T406	2
values[28]	321	1			T62	1		T230	7		T406	6
values[29]	374	1			T62	1		T230	7		T406	8
values[30]	312	1			T62	1		T230	4		T406	9
values[31]	348	1			T62	1		T230	15		T406	7
values[32]	311	1			T62	1		T230	6		T406	17
values[33]	326	1			T62	1		T230	5		T406	4
values[34]	348	1			T62	1		T230	5		T406	6
values[35]	306	1			T62	1		T230	8		T406	8
values[36]	316	1			T62	1		T230	10		T406	18
values[37]	358	1			T62	1		T230	7		T406	16
values[38]	345	1			T62	1		T230	12		T406	9
values[39]	306	1			T62	1		T230	12		T406	8
values[40]	320	1			T62	1		T230	4		T406	12
values[41]	285	1			T62	1		T230	4		T406	11
values[42]	329	1			T62	1		T230	6		T406	4
values[43]	310	1			T62	1		T230	6		T406	2
values[44]	352	1			T62	1		T230	3		T406	4
values[45]	297	1			T62	1		T230	4		T406	3
values[46]	338	1			T62	1		T230	5		T406	9
values[47]	265	1			T62	2		T230	7		T406	4
values[48]	255	1			T62	1		T230	5		T406	2
values[49]	248	1			T62	1		T406	3		T451	9
values[50]	262	1			T62	1		T451	10		T801	1
values[51]	255	1			T62	1		T451	8		T801	2
values[52]	263	1			T62	1		T451	12		T801	1
values[53]	245	1			T62	1		T451	14		T801	1
values[54]	232	1			T62	1		T451	13		T801	1
values[55]	192	1			T62	1		T451	8		T801	1
values[56]	237	1			T62	1		T451	2		T801	1
values[57]	227	1			T62	1		T451	5		T801	1
values[58]	195	1			T62	1		T451	4		T801	1
values[59]	161	1			T62	1		T451	4		T801	1
values[60]	186	1			T62	1		T451	6		T801	1
values[61]	195	1			T62	1		T451	4		T801	1
values[62]	195	1			T62	1		T451	7		T801	1
values[63]	173	1			T62	1		T451	7		T801	1
values[64]	225	1			T62	1		T451	4		T801	1
values[65]	183	1			T62	1		T451	8		T801	1
values[66]	196	1			T62	1		T451	7		T801	1
values[67]	162	1			T62	1		T451	11		T801	1
values[68]	142	1			T62	1		T451	11		T801	1
values[69]	117	1			T62	1		T451	12		T801	1
values[70]	121	1			T62	1		T451	7		T801	1
values[71]	118	1			T62	1		T451	11		T801	1
values[72]	116	1			T62	1		T451	13		T801	1
values[73]	96	1			T62	1		T451	7		T801	1
values[74]	81	1			T62	1		T451	9		T801	1
values[75]	82	1			T62	1		T451	9		T801	1
values[76]	95	1			T62	1		T451	8		T801	1
values[77]	92	1			T62	1		T451	7		T801	1
values[78]	75	1			T62	1		T451	3		T801	5
values[79]	80	1			T62	1		T451	7		T801	2
values[80]	76	1			T62	1		T451	12		T801	4
values[81]	69	1			T62	1		T801	3		T514	1
values[82]	72	1			T62	1		T801	9		T514	1
values[83]	63	1			T62	1		T801	1		T514	1
values[84]	60	1			T62	1		T801	2		T514	1
values[85]	70	1			T62	1		T801	5		T514	1
values[86]	75	1			T62	1		T801	3		T514	1
values[87]	66	1			T62	1		T801	2		T514	1
values[88]	64	1			T62	1		T801	3		T514	1
values[89]	66	1			T62	1		T801	3		T514	1
values[90]	90	1			T62	1		T801	9		T514	1
values[91]	70	1			T62	1		T801	6		T514	1
values[92]	61	1			T62	1		T801	2		T514	1
values[93]	74	1			T62	2		T801	5		T514	1
values[94]	66	1			T62	1		T801	4		T514	1
values[95]	63	1			T62	1		T801	3		T514	1
values[96]	54	1			T62	1		T801	5		T514	1
values[97]	49	1			T62	1		T801	1		T514	1
values[98]	54	1			T62	1		T801	1		T514	1
values[99]	67	1			T62	1		T801	4		T514	1
values[100]	56	1			T62	1		T801	2		T514	1
values[101]	59	1			T62	1		T801	2		T514	1
values[102]	41	1			T62	1		T801	5		T514	1
values[103]	43	1			T62	1		T801	1		T514	1
values[104]	56	1			T62	1		T801	1		T514	1
values[105]	46	1			T62	1		T801	1		T514	1
values[106]	37	1			T62	1		T801	2		T514	2
values[107]	64	1			T62	1		T801	4		T514	8
values[108]	68	1			T62	1		T801	7		T514	6
values[109]	58	1			T62	1		T801	1		T514	1
values[110]	65	1			T62	1		T801	4		T514	1
values[111]	53	1			T62	1		T801	4		T514	3
values[112]	56	1			T62	1		T801	1		T514	2
values[113]	38	1			T62	1		T801	3		T514	1
values[114]	38	1			T62	1		T801	4		T514	2
values[115]	49	1			T62	1		T801	1		T514	1
values[116]	49	1			T62	3		T801	1		T514	3
values[117]	45	1			T62	2		T801	3		T514	1
values[118]	36	1			T62	3		T801	1		T514	2
values[119]	53	1			T62	1		T801	1		T514	1
values[120]	66	1			T62	3		T801	3		T514	4
values[121]	52	1			T62	1		T801	1		T514	3
values[122]	51	1			T62	2		T801	3		T514	3
values[123]	57	1			T62	1		T801	3		T514	7
values[124]	41	1			T62	3		T801	1		T514	3
values[125]	59	1			T62	1		T801	3		T514	3
values[126]	90	1			T62	3		T801	2		T514	5
values[127]	678	1			T62	30		T801	28		T514	42
values[128]	5585	1			T62	317		T801	247		T514	316