Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.36	95.29	93.66	91.79		94.46	97.38	99.57

Total tests in report: 2795

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.29	40.29	45.20	45.20	43.18	43.18	31.97	31.97			58.02	58.02	62.96	62.96	0.39	0.39	/workspace/coverage/default/52.chip_sw_all_escalation_resets.3304293029
49.54	9.25	50.39	5.20	55.34	12.16	32.47	0.50			68.08	10.06	89.63	26.67	1.33	0.94	/workspace/coverage/cover_reg_top/17.chip_csr_rw.3310313138
57.48	7.94	62.75	12.36	58.68	3.34	36.16	3.70			68.79	0.71	89.63	0.00	28.88	27.55	/workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1433385696
62.86	5.38	74.29	11.53	66.46	7.78	38.71	2.55			79.18	10.39	89.63	0.00	28.88	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2700316282
66.30	3.44	74.62	0.33	68.55	2.09	43.20	4.49			79.83	0.65	89.63	0.00	41.95	13.07	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.1593965230
69.24	2.94	74.62	0.00	68.76	0.21	43.20	0.00			79.88	0.05	89.63	0.00	59.35	17.40	/workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.410621604
71.96	2.72	80.60	5.98	73.06	4.30	47.16	3.97			81.94	2.06	89.63	0.00	59.35	0.00	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2294048328
74.64	2.68	80.60	0.00	73.06	0.00	63.26	16.10			81.94	0.00	89.63	0.00	59.35	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.955590053
76.82	2.18	82.58	1.99	75.58	2.52	69.67	6.41			83.75	1.82	90.00	0.37	59.35	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3049913192
78.88	2.06	82.58	0.00	75.58	0.00	69.67	0.00			83.75	0.00	90.00	0.00	71.70	12.35	/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1823857494
80.29	1.41	84.19	1.60	76.80	1.22	72.10	2.43			85.05	1.30	91.85	1.85	71.74	0.05	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3637039414
81.60	1.31	84.19	0.00	77.06	0.26	72.10	0.00			85.15	0.10	91.85	0.00	79.27	7.53	/workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3177059690
82.79	1.19	85.81	1.62	79.77	2.71	72.32	0.22			87.73	2.58	91.85	0.00	79.27	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3138213521
83.86	1.07	85.81	0.00	79.77	0.00	72.32	0.00			87.73	0.00	91.85	0.00	85.67	6.39	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.207501741
84.89	1.04	87.23	1.42	80.92	1.15	74.65	2.33			88.55	0.82	92.04	0.19	85.98	0.32	/workspace/coverage/default/0.chip_jtag_csr_rw.454854722
85.79	0.90	87.98	0.75	81.17	0.26	74.68	0.03			88.82	0.27	96.11	4.07	85.98	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3935293249
86.61	0.82	87.98	0.00	81.17	0.00	74.68	0.00			88.82	0.00	96.11	0.00	90.88	4.90	/workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1483457228
87.32	0.71	88.03	0.05	81.23	0.06	77.09	2.42			88.82	0.00	96.11	0.00	92.63	1.75	/workspace/coverage/default/1.chip_sw_alert_test.522658139
87.96	0.64	89.12	1.09	82.45	1.21	77.66	0.57			89.78	0.96	96.11	0.00	92.63	0.00	/workspace/coverage/default/2.chip_sw_gpio.1844084320
88.57	0.61	89.15	0.03	82.45	0.00	81.31	3.65			89.78	0.00	96.11	0.00	92.63	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3089277872
89.14	0.56	90.25	1.10	83.31	0.87	81.70	0.39			90.81	1.03	96.11	0.00	92.63	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.856786436
89.67	0.53	91.07	0.82	83.92	0.61	82.55	0.84			91.73	0.92	96.11	0.00	92.63	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.696603447
90.19	0.52	91.79	0.72	86.00	2.08	82.61	0.06			91.97	0.25	96.11	0.00	92.64	0.01	/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1139996317
90.70	0.51	91.80	0.01	88.62	2.62	82.62	0.01			91.97	0.00	96.11	0.00	93.07	0.42	/workspace/coverage/cover_reg_top/8.chip_tl_errors.806201182
91.05	0.35	91.80	0.00	88.62	0.00	82.62	0.00			91.97	0.00	96.11	0.00	95.19	2.13	/workspace/coverage/cover_reg_top/61.xbar_access_same_device.1387263375
91.39	0.34	92.32	0.52	89.10	0.49	83.15	0.53			92.46	0.49	96.11	0.00	95.19	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.3376422369
91.69	0.30	92.32	0.00	89.10	0.00	83.15	0.00			92.46	0.00	96.11	0.00	97.00	1.81	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.887445815
91.97	0.27	92.34	0.01	89.11	0.01	84.73	1.58			92.46	0.00	96.11	0.00	97.05	0.05	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1921539857
92.21	0.25	93.11	0.77	89.28	0.17	85.19	0.46			92.54	0.07	96.11	0.00	97.05	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2897536630
92.41	0.19	93.11	0.00	89.28	0.00	86.35	1.16			92.54	0.00	96.11	0.00	97.05	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3053325900
92.58	0.18	93.17	0.06	89.76	0.47	86.37	0.02			93.05	0.52	96.11	0.00	97.05	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.687512588
92.76	0.17	93.53	0.36	90.08	0.32	86.73	0.36			93.05	0.00	96.11	0.00	97.05	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1484948014
92.92	0.16	93.53	0.00	90.08	0.00	87.62	0.89			93.05	0.00	96.11	0.00	97.10	0.05	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3900701486
93.05	0.13	93.58	0.05	90.21	0.13	87.91	0.29			93.15	0.10	96.30	0.19	97.14	0.05	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.530301973
93.18	0.13	93.58	0.00	91.00	0.79	87.91	0.00			93.15	0.00	96.30	0.00	97.14	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.1065330339
93.30	0.12	93.58	0.00	91.00	0.00	88.65	0.74			93.15	0.00	96.30	0.00	97.14	0.00	/workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1102977361
93.42	0.12	93.58	0.00	91.00	0.00	89.35	0.69			93.15	0.00	96.30	0.00	97.18	0.04	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3624709211
93.54	0.12	93.58	0.00	91.03	0.04	89.35	0.00			93.15	0.00	96.30	0.00	97.85	0.67	/workspace/coverage/cover_reg_top/39.xbar_random_large_delays.868888457
93.66	0.12	93.78	0.21	91.21	0.18	89.36	0.01			93.45	0.30	96.30	0.00	97.85	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2763778075
93.74	0.08	93.78	0.00	91.35	0.14	89.62	0.26			93.48	0.02	96.30	0.00	97.93	0.08	/workspace/coverage/cover_reg_top/98.xbar_stress_all.2886722386
93.83	0.08	93.93	0.15	91.47	0.12	89.72	0.10			93.61	0.13	96.30	0.00	97.93	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3323233969
93.91	0.08	94.00	0.07	91.70	0.22	89.72	0.00			93.79	0.18	96.30	0.00	97.93	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2721016229
93.97	0.06	94.12	0.12	91.83	0.14	89.72	0.00			93.92	0.13	96.30	0.00	97.93	0.00	/workspace/coverage/cover_reg_top/9.chip_csr_rw.468169379
94.02	0.05	94.16	0.04	91.92	0.09	89.86	0.14			93.97	0.05	96.30	0.00	97.93	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2215265074
94.07	0.05	94.16	0.00	92.06	0.14	89.86	0.00			94.13	0.16	96.30	0.00	97.93	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1611438967
94.12	0.05	94.18	0.02	92.06	0.00	90.14	0.28			94.13	0.00	96.30	0.00	97.93	0.00	/workspace/coverage/default/0.chip_sw_power_sleep_load.1676664886
94.17	0.05	94.19	0.01	92.10	0.04	90.16	0.02			94.16	0.03	96.48	0.19	97.94	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.979172664
94.22	0.05	94.22	0.03	92.13	0.02	90.19	0.03			94.19	0.02	96.67	0.19	97.94	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3909231381
94.27	0.05	94.22	0.00	92.13	0.00	90.46	0.28			94.19	0.00	96.67	0.00	97.94	0.00	/workspace/coverage/default/1.chip_sw_edn_auto_mode.439304902
94.31	0.04	94.24	0.02	92.16	0.03	90.46	0.00			94.20	0.02	96.85	0.19	97.96	0.01	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3655147862
94.36	0.04	94.36	0.13	92.16	0.01	90.58	0.12			94.22	0.02	96.85	0.00	97.96	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.532501481
94.40	0.04	94.37	0.01	92.17	0.01	90.58	0.00			94.24	0.02	97.04	0.19	97.97	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2067067300
94.44	0.04	94.37	0.00	92.28	0.10	90.58	0.00			94.26	0.02	97.04	0.00	98.08	0.12	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3886669489
94.47	0.04	94.38	0.01	92.29	0.01	90.59	0.01			94.27	0.01	97.22	0.19	98.10	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.1882689573
94.51	0.04	94.38	0.00	92.29	0.00	90.63	0.04			94.27	0.00	97.41	0.19	98.10	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3381536733
94.55	0.04	94.38	0.01	92.30	0.01	90.82	0.19			94.27	0.00	97.41	0.00	98.11	0.01	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2652006075
94.58	0.04	94.38	0.00	92.35	0.05	90.82	0.00			94.29	0.02	97.41	0.00	98.25	0.14	/workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2776553209
94.62	0.03	94.42	0.03	92.41	0.06	90.91	0.09			94.31	0.02	97.41	0.00	98.25	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2924409781
94.65	0.03	94.42	0.00	92.41	0.00	91.11	0.20			94.31	0.00	97.41	0.00	98.25	0.00	/workspace/coverage/default/0.chip_sw_flash_init.909911296
94.68	0.03	94.42	0.00	92.47	0.05	91.11	0.00			94.33	0.02	97.41	0.00	98.34	0.09	/workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3255166364
94.70	0.03	94.42	0.00	92.63	0.16	91.11	0.00			94.33	0.00	97.41	0.00	98.34	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.453391292
94.73	0.02	94.42	0.00	92.69	0.07	91.11	0.00			94.34	0.02	97.41	0.00	98.40	0.06	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3338624771
94.75	0.02	94.48	0.07	92.74	0.05	91.11	0.00			94.36	0.02	97.41	0.00	98.40	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3063851259
94.77	0.02	94.55	0.07	92.79	0.05	91.11	0.00			94.37	0.02	97.41	0.00	98.40	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1372930314
94.79	0.02	94.58	0.03	92.83	0.03	91.16	0.06			94.39	0.02	97.41	0.00	98.40	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1903429077
94.81	0.02	94.59	0.01	92.83	0.01	91.25	0.09			94.40	0.01	97.41	0.00	98.40	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2002419403
94.83	0.02	94.59	0.00	92.83	0.01	91.25	0.00			94.40	0.00	97.41	0.00	98.51	0.11	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.858372555
94.85	0.02	94.59	0.00	92.93	0.10	91.25	0.00			94.40	0.00	97.41	0.00	98.51	0.00	/workspace/coverage/cover_reg_top/6.chip_tl_errors.3647988606
94.86	0.01	94.59	0.00	92.93	0.00	91.34	0.09			94.40	0.00	97.41	0.00	98.51	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.892371571
94.88	0.01	94.59	0.00	92.93	0.00	91.42	0.08			94.40	0.00	97.41	0.00	98.51	0.00	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3041191601
94.89	0.01	94.59	0.00	93.00	0.07	91.42	0.00			94.40	0.00	97.41	0.00	98.52	0.01	/workspace/coverage/cover_reg_top/1.xbar_stress_all.1844574392
94.90	0.01	94.59	0.00	93.06	0.06	91.42	0.00			94.40	0.00	97.41	0.00	98.53	0.01	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.157428281
94.91	0.01	94.59	0.00	93.06	0.00	91.42	0.00			94.40	0.00	97.41	0.00	98.60	0.07	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.889357937
94.92	0.01	94.59	0.00	93.06	0.00	91.49	0.07			94.40	0.00	97.41	0.00	98.60	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.4080775004
94.93	0.01	94.59	0.00	93.12	0.06	91.49	0.00			94.40	0.00	97.41	0.00	98.60	0.00	/workspace/coverage/cover_reg_top/5.chip_tl_errors.2598038562
94.94	0.01	94.59	0.00	93.17	0.06	91.49	0.00			94.40	0.00	97.41	0.00	98.60	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.3430378318
94.95	0.01	94.62	0.02	93.18	0.01	91.49	0.01			94.42	0.02	97.41	0.00	98.60	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.171149316
94.96	0.01	94.62	0.00	93.20	0.02	91.49	0.00			94.42	0.00	97.41	0.00	98.64	0.04	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.4229308229
94.97	0.01	94.62	0.00	93.23	0.03	91.49	0.00			94.42	0.00	97.41	0.00	98.66	0.02	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2789627037
94.98	0.01	94.62	0.01	93.23	0.01	91.51	0.01			94.43	0.02	97.41	0.00	98.66	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3302032073
94.98	0.01	94.62	0.00	93.28	0.04	91.51	0.00			94.43	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3627395911
94.99	0.01	94.62	0.00	93.32	0.04	91.51	0.00			94.43	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2213646323
95.00	0.01	94.63	0.01	93.35	0.04	91.51	0.00			94.43	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.164029686
95.00	0.01	94.63	0.00	93.39	0.04	91.51	0.00			94.43	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.3012453103
95.01	0.01	94.63	0.00	93.41	0.02	91.51	0.00			94.43	0.00	97.41	0.00	98.67	0.01	/workspace/coverage/cover_reg_top/81.xbar_access_same_device.2990043000
95.01	0.01	94.63	0.00	93.41	0.00	91.54	0.03			94.43	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/1.chip_sw_flash_init.640526433
95.02	0.01	94.63	0.00	93.44	0.03	91.54	0.00			94.43	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.961521805
95.03	0.01	94.63	0.00	93.44	0.00	91.57	0.03			94.43	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.4267332843
95.03	0.01	94.65	0.02	93.44	0.00	91.58	0.01			94.43	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2998702852
95.04	0.01	94.65	0.00	93.44	0.00	91.61	0.03			94.43	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.3393813172
95.04	0.01	94.66	0.01	93.45	0.01	91.61	0.01			94.43	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/2.chip_sw_pattgen_ios.966671424
95.04	0.01	94.66	0.00	93.45	0.00	91.61	0.00			94.43	0.00	97.41	0.00	98.70	0.02	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3359346270
95.05	0.01	94.66	0.00	93.45	0.00	91.61	0.00			94.43	0.00	97.41	0.00	98.72	0.02	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1589925428
95.05	0.01	94.66	0.00	93.45	0.00	91.61	0.00			94.43	0.00	97.41	0.00	98.74	0.02	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.4002423762
95.05	0.01	94.66	0.00	93.47	0.02	91.61	0.00			94.43	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.4217534310
95.06	0.01	94.66	0.00	93.47	0.00	91.64	0.02			94.43	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.652763408
95.06	0.01	94.66	0.00	93.47	0.01	91.64	0.00			94.45	0.02	97.41	0.00	98.74	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.26761078
95.06	0.01	94.66	0.00	93.47	0.00	91.65	0.02			94.45	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3180339220
95.07	0.01	94.66	0.00	93.47	0.00	91.67	0.02			94.45	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3834151617
95.07	0.01	94.66	0.00	93.49	0.02	91.67	0.00			94.45	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.746510004
95.07	0.01	94.66	0.00	93.51	0.02	91.67	0.00			94.45	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2738748920
95.08	0.01	94.66	0.00	93.53	0.02	91.67	0.00			94.45	0.00	97.41	0.00	98.74	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.4112834951
95.08	0.01	94.66	0.01	93.53	0.00	91.67	0.01			94.45	0.00	97.41	0.00	98.75	0.01	/workspace/coverage/default/82.chip_sw_all_escalation_resets.1129826246
95.08	0.01	94.66	0.00	93.53	0.01	91.67	0.00			94.45	0.00	97.41	0.00	98.77	0.01	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3736850932
95.08	0.01	94.66	0.00	93.53	0.01	91.67	0.00			94.45	0.00	97.41	0.00	98.78	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.3257885180
95.09	0.01	94.67	0.01	93.53	0.00	91.69	0.01			94.45	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.829312639
95.09	0.01	94.67	0.00	93.54	0.01	91.69	0.01			94.45	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2759463919
95.09	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.79	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2561145544
95.09	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.80	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.575312016
95.09	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.81	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.715587098
95.10	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.83	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1572939954
95.10	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.84	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.82233230
95.10	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.85	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.63983307
95.10	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.86	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4074454980
95.10	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.87	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.457754442
95.11	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.88	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3301813181
95.11	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.90	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.72963553
95.11	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.91	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1617320973
95.11	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.92	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.2871995230
95.11	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.93	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.578481456
95.12	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.94	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.666605384
95.12	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.95	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2275805851
95.12	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.97	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.288632786
95.12	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.98	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.1795013602
95.12	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	98.99	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1743504795
95.13	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.00	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.1792933182
95.13	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.01	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3895724159
95.13	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.02	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.1242639867
95.13	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.04	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2867852332
95.13	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.05	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.246139733
95.14	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.06	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.659098774
95.14	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.07	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.4252346706
95.14	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.08	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.672267179
95.14	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.10	0.01	/workspace/coverage/default/30.chip_sw_all_escalation_resets.1806569895
95.14	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.11	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.1118703312
95.15	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.12	0.01	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3583543569
95.15	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.13	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.3833607743
95.15	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.14	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.298216421
95.15	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.15	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2238911544
95.15	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.17	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.1145879312
95.16	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.18	0.01	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3162495608
95.16	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.19	0.01	/workspace/coverage/default/39.chip_sw_all_escalation_resets.676257258
95.16	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.20	0.01	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1615786702
95.16	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.21	0.01	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2107425850
95.16	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.22	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.543313039
95.17	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.24	0.01	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2504029448
95.17	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.25	0.01	/workspace/coverage/default/41.chip_sw_all_escalation_resets.3201695554
95.17	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.26	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.906420011
95.17	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.27	0.01	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2331127706
95.17	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.28	0.01	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3753571663
95.17	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.30	0.01	/workspace/coverage/default/45.chip_sw_all_escalation_resets.3452298756
95.18	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.31	0.01	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1873116876
95.18	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.32	0.01	/workspace/coverage/default/47.chip_sw_all_escalation_resets.1822085923
95.18	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.33	0.01	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3380207654
95.18	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.34	0.01	/workspace/coverage/default/48.chip_sw_all_escalation_resets.3038718159
95.18	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.35	0.01	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1147667378
95.19	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.37	0.01	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3431926911
95.19	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.38	0.01	/workspace/coverage/default/5.chip_sw_all_escalation_resets.3669441757
95.19	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.39	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1712729329
95.19	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.40	0.01	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3665029712
95.19	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.41	0.01	/workspace/coverage/default/54.chip_sw_all_escalation_resets.3797770326
95.20	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.42	0.01	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2605818372
95.20	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.44	0.01	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1835239124
95.20	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.45	0.01	/workspace/coverage/default/62.chip_sw_all_escalation_resets.588203679
95.20	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.46	0.01	/workspace/coverage/default/64.chip_sw_all_escalation_resets.868165320
95.20	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.47	0.01	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.853212958
95.21	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.48	0.01	/workspace/coverage/default/71.chip_sw_all_escalation_resets.4041552822
95.21	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4265217903
95.21	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/73.chip_sw_all_escalation_resets.2179330138
95.21	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119714434
95.21	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/77.chip_sw_all_escalation_resets.2942465131
95.22	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.54	0.01	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.4117366369
95.22	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.55	0.01	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3032503145
95.22	0.01	94.67	0.00	93.54	0.00	91.69	0.00			94.45	0.00	97.41	0.00	99.57	0.01	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2731237060
95.22	0.01	94.67	0.00	93.54	0.00	91.70	0.01			94.45	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.940154837
95.22	0.01	94.67	0.00	93.55	0.01	91.70	0.00			94.45	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.3584974226
95.23	0.01	94.67	0.00	93.56	0.01	91.70	0.00			94.45	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1450259403
95.23	0.01	94.67	0.00	93.57	0.01	91.70	0.00			94.45	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.927546086
95.23	0.01	94.67	0.01	93.58	0.01	91.70	0.00			94.45	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2248866704
95.23	0.01	94.68	0.01	93.58	0.00	91.71	0.01			94.45	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/31.chip_sw_all_escalation_resets.1288079922
95.23	0.01	94.69	0.01	93.58	0.00	91.71	0.00			94.45	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.3950173667
95.23	0.01	94.69	0.00	93.58	0.00	91.72	0.01			94.45	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3151507977
95.24	0.01	94.69	0.00	93.58	0.00	91.73	0.01			94.45	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2153079855
95.24	0.01	94.69	0.00	93.58	0.00	91.74	0.01			94.45	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2251543037
95.24	0.01	94.69	0.00	93.58	0.00	91.74	0.00			94.46	0.01	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2494662517
95.24	0.01	94.69	0.00	93.58	0.00	91.74	0.00			94.46	0.01	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.3016689014
95.24	0.01	94.69	0.01	93.58	0.00	91.74	0.01			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2267020228
95.24	0.01	94.69	0.00	93.58	0.01	91.74	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/10.xbar_stress_all.570945719
95.24	0.01	94.69	0.00	93.59	0.01	91.74	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/13.xbar_same_source.777747594
95.24	0.01	94.69	0.00	93.60	0.01	91.74	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.3612790298
95.25	0.01	94.69	0.00	93.60	0.01	91.74	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4272191761
95.25	0.01	94.69	0.00	93.61	0.01	91.74	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.138112954
95.25	0.01	94.70	0.01	93.62	0.01	91.74	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.914483416
95.25	0.01	94.70	0.00	93.62	0.00	91.75	0.01			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.350593149
95.25	0.01	94.70	0.00	93.62	0.00	91.76	0.01			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3490706592
95.25	0.01	94.70	0.01	93.62	0.00	91.76	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1766704677
95.25	0.01	94.70	0.00	93.62	0.00	91.76	0.01			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.1996319953
95.25	0.01	94.70	0.00	93.62	0.00	91.76	0.01			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.561131037
95.25	0.01	94.70	0.00	93.62	0.00	91.77	0.01			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.201636179
95.26	0.01	94.70	0.00	93.62	0.00	91.77	0.01			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_flash_init.2311147741
95.26	0.01	94.70	0.00	93.62	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_rw.2066784065
95.26	0.01	94.70	0.00	93.62	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1875389162
95.26	0.01	94.70	0.00	93.63	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/12.xbar_stress_all.1076159760
95.26	0.01	94.70	0.00	93.63	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.3860555743
95.26	0.01	94.70	0.00	93.63	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.3497967136
95.26	0.01	94.70	0.00	93.64	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.3768302726
95.26	0.01	94.70	0.00	93.64	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.2647021682
95.26	0.01	94.70	0.00	93.64	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.3852322175
95.26	0.01	94.70	0.00	93.65	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.4001366342
95.26	0.01	94.70	0.00	93.65	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.1129912513
95.26	0.01	94.70	0.00	93.65	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_gpio.3114753284
95.26	0.01	94.70	0.00	93.66	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3308532894
95.26	0.01	94.70	0.00	93.66	0.00	91.78	0.01			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/1.chip_tap_straps_testunlock0.2332161911
95.26	0.01	94.71	0.01	93.66	0.00	91.78	0.00			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.754228468
95.26	0.01	94.71	0.00	93.66	0.00	91.78	0.01			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.56929040
95.26	0.01	94.71	0.00	93.66	0.00	91.78	0.01			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1231578434
95.26	0.01	94.71	0.00	93.66	0.00	91.78	0.01			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.440062918
95.26	0.01	94.71	0.00	93.66	0.00	91.79	0.01			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3424327679
95.27	0.01	94.71	0.00	93.66	0.00	91.79	0.01			94.46	0.00	97.41	0.00	99.57	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.635156723

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.561581149
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.499302682
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2110774042
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.223542966
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2227982198
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1163996330
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1553223588
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2983355644
/workspace/coverage/cover_reg_top/0.xbar_error_random.2342513394
/workspace/coverage/cover_reg_top/0.xbar_random.4162339539
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.126823105
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1939944430
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3076961855
/workspace/coverage/cover_reg_top/0.xbar_same_source.458448989
/workspace/coverage/cover_reg_top/0.xbar_smoke.2629008460
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3524205403
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2882330544
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.963234251
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3925236187
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2322758979
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3324237447
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1422701998
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1317718808
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2593131450
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1556416611
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1448432933
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.493277416
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.4130602865
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1561105533
/workspace/coverage/cover_reg_top/1.chip_tl_errors.944404154
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1832086079
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3155062147
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3677102263
/workspace/coverage/cover_reg_top/1.xbar_error_random.3100498724
/workspace/coverage/cover_reg_top/1.xbar_random.1894721036
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3389231564
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.4159912777
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3577414778
/workspace/coverage/cover_reg_top/1.xbar_same_source.2225709043
/workspace/coverage/cover_reg_top/1.xbar_smoke.777930192
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3149676930
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2745885263
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2393239150
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.674626220
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3965647205
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.311082104
/workspace/coverage/cover_reg_top/10.chip_csr_rw.893392169
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.329161734
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1980860578
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3798777879
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1785862690
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2194329132
/workspace/coverage/cover_reg_top/10.xbar_error_random.1302761674
/workspace/coverage/cover_reg_top/10.xbar_random.3899057116
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.563270781
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2873144355
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1404079586
/workspace/coverage/cover_reg_top/10.xbar_same_source.3274114637
/workspace/coverage/cover_reg_top/10.xbar_smoke.81604234
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.246370481
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1500223602
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2273698934
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1447145513
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3377865936
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3385788961
/workspace/coverage/cover_reg_top/11.chip_csr_rw.436556632
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.4154291848
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1726147375
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3745297550
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3888715665
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2178697099
/workspace/coverage/cover_reg_top/11.xbar_error_random.3318060675
/workspace/coverage/cover_reg_top/11.xbar_random.988412442
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3287657946
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3703911496
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3144978214
/workspace/coverage/cover_reg_top/11.xbar_same_source.2876986043
/workspace/coverage/cover_reg_top/11.xbar_smoke.2262625526
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.4150274421
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1147627090
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1734099708
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2961087174
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2723918988
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1542559617
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2818567544
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1070793218
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1669175998
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1018259979
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3547414798
/workspace/coverage/cover_reg_top/12.xbar_error_random.3628942843
/workspace/coverage/cover_reg_top/12.xbar_random.3977116006
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2201173535
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.790328706
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.970442404
/workspace/coverage/cover_reg_top/12.xbar_same_source.3415560438
/workspace/coverage/cover_reg_top/12.xbar_smoke.4227570573
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1737194765
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2792852529
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3640887745
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2853013916
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1784138454
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2920169670
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.815642830
/workspace/coverage/cover_reg_top/13.chip_csr_rw.1731151160
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2004137114
/workspace/coverage/cover_reg_top/13.chip_tl_errors.240501082
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.4011014750
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3573799244
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1200685479
/workspace/coverage/cover_reg_top/13.xbar_error_random.4213644043
/workspace/coverage/cover_reg_top/13.xbar_random.705022255
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1299369866
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3183948495
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3338101799
/workspace/coverage/cover_reg_top/13.xbar_smoke.1884568218
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2499764022
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3320169414
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.96048198
/workspace/coverage/cover_reg_top/13.xbar_stress_all.2170161685
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2417497675
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1676718544
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.294197926
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.329663631
/workspace/coverage/cover_reg_top/14.chip_csr_rw.1983379625
/workspace/coverage/cover_reg_top/14.chip_tl_errors.158546647
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.243602535
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.103006065
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2556122203
/workspace/coverage/cover_reg_top/14.xbar_error_random.3584080833
/workspace/coverage/cover_reg_top/14.xbar_random.1616951351
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2142522882
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1560216835
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2783154685
/workspace/coverage/cover_reg_top/14.xbar_same_source.2771638306
/workspace/coverage/cover_reg_top/14.xbar_smoke.718422070
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.545324442
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.4241908875
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2513211437
/workspace/coverage/cover_reg_top/14.xbar_stress_all.708719068
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3229798427
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.587978676
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1856212081
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.1906178702
/workspace/coverage/cover_reg_top/15.chip_csr_rw.3137091565
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3894915119
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/workspace/coverage/default/55.chip_sw_all_escalation_resets.3124750293
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4082811271
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2111707211
/workspace/coverage/default/57.chip_sw_all_escalation_resets.834857818
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2453222260
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1277132488
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2551201893
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3023255753
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3440109763
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.303935991
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.41678948
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2441876059
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2184454217
/workspace/coverage/default/61.chip_sw_all_escalation_resets.3977448186
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2885380439
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3998846600
/workspace/coverage/default/63.chip_sw_all_escalation_resets.626096625
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.462633070
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3328743057
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2102699373
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1046714284
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2415301594
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1544729200
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2187734843
/workspace/coverage/default/68.chip_sw_all_escalation_resets.1398881682
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3826813012
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2246668929
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3697228921
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2951510846
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3906139686
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630867366
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1756113753
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.98667452
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2890460665
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3247443727
/workspace/coverage/default/74.chip_sw_all_escalation_resets.3277430869
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1609935916
/workspace/coverage/default/75.chip_sw_all_escalation_resets.667258504
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1902056989
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3403536497
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2677920712
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.809661147
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2736227688
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3189677972
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3481769986
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.975333971
/workspace/coverage/default/8.chip_sw_all_escalation_resets.926318667
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3538284374
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3818701916
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2142744697
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.877819755
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2797801421
/workspace/coverage/default/83.chip_sw_all_escalation_resets.2743253358
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2910327611
/workspace/coverage/default/84.chip_sw_all_escalation_resets.741707404
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3338736551
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3650875251
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2854754530
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3450309856
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3495703233
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600861087
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2305642969
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3240789011
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3086250892
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1742834157
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1245341684
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3805943258
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1108833303
/workspace/coverage/default/92.chip_sw_all_escalation_resets.188689122
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3546746851
/workspace/coverage/default/95.chip_sw_all_escalation_resets.4082855303
/workspace/coverage/default/96.chip_sw_all_escalation_resets.774350506
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1845764305
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1400257482
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3035888752
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3268550083
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.131794214
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2836425607
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3144469789
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3469005737
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1414883327
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3243960771
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1192918173

---

Total test records in report: 2795

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/34.chip_sw_all_escalation_resets.3833607743			May 21 04:18:57 PM PDT 24	May 21 04:28:09 PM PDT 24	4846272800 ps
T2	/workspace/coverage/default/2.chip_sw_pattgen_ios.966671424			May 21 04:07:25 PM PDT 24	May 21 04:12:02 PM PDT 24	3066695420 ps
T3	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.696603447			May 21 03:53:26 PM PDT 24	May 21 04:06:38 PM PDT 24	4516371044 ps
T92	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1919876498			May 21 04:11:35 PM PDT 24	May 21 04:19:32 PM PDT 24	3895410720 ps
T115	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3632645090			May 21 04:13:35 PM PDT 24	May 21 04:17:55 PM PDT 24	3260164208 ps
T44	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3049913192			May 21 04:02:10 PM PDT 24	May 21 04:55:42 PM PDT 24	14558687832 ps
T95	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.561131037			May 21 03:54:50 PM PDT 24	May 21 04:59:19 PM PDT 24	24584487745 ps
T31	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.847578948			May 21 04:11:49 PM PDT 24	May 21 04:28:24 PM PDT 24	9931453800 ps
T32	/workspace/coverage/default/52.chip_sw_all_escalation_resets.3304293029			May 21 04:20:22 PM PDT 24	May 21 04:30:33 PM PDT 24	5704307456 ps
T4	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2652006075			May 21 04:05:11 PM PDT 24	May 21 05:15:24 PM PDT 24	13479156133 ps
T103	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2238911544			May 21 04:19:46 PM PDT 24	May 21 04:25:29 PM PDT 24	3626572892 ps
T104	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.730678689			May 21 04:20:01 PM PDT 24	May 21 04:26:54 PM PDT 24	4113456280 ps
T378	/workspace/coverage/default/2.chip_sw_aes_smoketest.3999159789			May 21 04:17:06 PM PDT 24	May 21 04:22:57 PM PDT 24	2249371852 ps
T91	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1921539857			May 21 04:06:01 PM PDT 24	May 21 04:21:07 PM PDT 24	5757471088 ps
T238	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3308532894			May 21 04:05:15 PM PDT 24	May 21 04:17:56 PM PDT 24	4377781896 ps
T5	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3900701486			May 21 04:03:33 PM PDT 24	May 21 04:32:41 PM PDT 24	21941199147 ps
T49	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2729923575			May 21 04:02:02 PM PDT 24	May 21 04:12:31 PM PDT 24	5225653370 ps
T16	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3637039414			May 21 04:11:40 PM PDT 24	May 21 04:35:21 PM PDT 24	20175312642 ps
T10	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2897536630			May 21 03:59:55 PM PDT 24	May 21 04:10:20 PM PDT 24	3729839709 ps
T45	/workspace/coverage/default/2.rom_e2e_smoke.2777155974			May 21 04:19:46 PM PDT 24	May 21 05:05:38 PM PDT 24	15006794600 ps
T50	/workspace/coverage/default/2.chip_tap_straps_prod.3399944079			May 21 04:11:09 PM PDT 24	May 21 04:13:32 PM PDT 24	2321850479 ps
T81	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.666605384			May 21 04:18:43 PM PDT 24	May 21 04:22:54 PM PDT 24	2847561664 ps
T132	/workspace/coverage/default/0.chip_sw_edn_kat.907280670			May 21 03:54:13 PM PDT 24	May 21 04:05:20 PM PDT 24	3613919730 ps
T98	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3041191601			May 21 04:04:42 PM PDT 24	May 21 04:30:21 PM PDT 24	10044107608 ps
T6	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2828055772			May 21 04:10:39 PM PDT 24	May 21 04:25:54 PM PDT 24	9446238272 ps
T133	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1776082339			May 21 04:00:10 PM PDT 24	May 21 04:11:08 PM PDT 24	4932238352 ps
T75	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3624709211			May 21 03:57:56 PM PDT 24	May 21 04:20:58 PM PDT 24	11486148978 ps
T187	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3909231381			May 21 03:53:33 PM PDT 24	May 21 04:08:01 PM PDT 24	5771783134 ps
T249	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2352438303			May 21 04:14:38 PM PDT 24	May 21 04:34:57 PM PDT 24	5018986290 ps
T250	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1777530442			May 21 04:01:23 PM PDT 24	May 21 04:52:21 PM PDT 24	14460761920 ps
T175	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.541557170			May 21 03:53:31 PM PDT 24	May 21 03:57:28 PM PDT 24	3199433590 ps
T251	/workspace/coverage/default/1.chip_sw_example_flash.1529440714			May 21 03:59:03 PM PDT 24	May 21 04:02:19 PM PDT 24	3056255348 ps
T88	/workspace/coverage/default/0.rom_e2e_asm_init_prod.1290260736			May 21 04:00:05 PM PDT 24	May 21 05:05:36 PM PDT 24	14197263250 ps
T13	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3837461574			May 21 04:06:32 PM PDT 24	May 21 04:30:46 PM PDT 24	7628113760 ps
T145	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3935293249			May 21 04:12:13 PM PDT 24	May 21 04:16:07 PM PDT 24	2144849920 ps
T252	/workspace/coverage/default/2.chip_sw_aes_masking_off.3741872245			May 21 04:12:49 PM PDT 24	May 21 04:17:51 PM PDT 24	2912853778 ps
T188	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.531115497			May 21 04:03:08 PM PDT 24	May 21 04:06:51 PM PDT 24	2890003400 ps
T96	/workspace/coverage/default/22.chip_sw_all_escalation_resets.1795013602			May 21 04:19:11 PM PDT 24	May 21 04:30:45 PM PDT 24	4897452500 ps
T68	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3089277872			May 21 04:04:14 PM PDT 24	May 21 04:14:44 PM PDT 24	6613262798 ps
T225	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.973383322			May 21 04:11:20 PM PDT 24	May 21 04:19:39 PM PDT 24	5121007344 ps
T110	/workspace/coverage/default/1.chip_tap_straps_prod.843980491			May 21 04:01:15 PM PDT 24	May 21 04:18:22 PM PDT 24	8803019998 ps
T288	/workspace/coverage/default/2.chip_sw_aes_enc.1734491246			May 21 04:12:00 PM PDT 24	May 21 04:16:38 PM PDT 24	2871215862 ps
T239	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2749705977			May 21 03:53:25 PM PDT 24	May 21 04:50:26 PM PDT 24	40090254143 ps
T46	/workspace/coverage/default/0.chip_jtag_csr_rw.454854722			May 21 03:46:31 PM PDT 24	May 21 04:22:12 PM PDT 24	18908761873 ps
T429	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2634747302			May 21 03:56:37 PM PDT 24	May 21 04:18:36 PM PDT 24	6578381180 ps
T210	/workspace/coverage/default/29.chip_sw_all_escalation_resets.672267179			May 21 04:20:10 PM PDT 24	May 21 04:29:05 PM PDT 24	5328420434 ps
T14	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2680823497			May 21 04:18:43 PM PDT 24	May 21 04:59:23 PM PDT 24	12803384126 ps
T303	/workspace/coverage/default/46.chip_sw_all_escalation_resets.236465218			May 21 04:22:03 PM PDT 24	May 21 04:30:52 PM PDT 24	5088771444 ps
T99	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1945084416			May 21 04:11:01 PM PDT 24	May 21 04:19:13 PM PDT 24	4787525840 ps
T158	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3151507977			May 21 03:54:00 PM PDT 24	May 21 04:02:28 PM PDT 24	9000429160 ps
T108	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.326968945			May 21 04:11:52 PM PDT 24	May 21 04:19:16 PM PDT 24	3620857200 ps
T308	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2288075184			May 21 04:00:00 PM PDT 24	May 21 04:44:09 PM PDT 24	22814477799 ps
T74	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3695209137			May 21 04:12:52 PM PDT 24	May 21 04:22:05 PM PDT 24	4177151050 ps
T183	/workspace/coverage/default/2.chip_sw_power_idle_load.1747172748			May 21 04:13:25 PM PDT 24	May 21 04:23:41 PM PDT 24	4486914848 ps
T309	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.825003057			May 21 04:19:41 PM PDT 24	May 21 04:27:56 PM PDT 24	3565485398 ps
T206	/workspace/coverage/default/0.chip_sw_uart_tx_rx.4112834951			May 21 03:52:37 PM PDT 24	May 21 04:04:00 PM PDT 24	4267861462 ps
T153	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1415741864			May 21 04:04:49 PM PDT 24	May 21 04:09:23 PM PDT 24	2726543324 ps
T189	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.955590053			May 21 04:10:18 PM PDT 24	May 21 04:33:13 PM PDT 24	7933461206 ps
T418	/workspace/coverage/default/2.chip_sw_edn_sw_mode.1383288865			May 21 04:11:56 PM PDT 24	May 21 04:29:19 PM PDT 24	6471958552 ps
T17	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2262154163			May 21 04:06:04 PM PDT 24	May 21 04:14:16 PM PDT 24	5812410968 ps
T87	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1912286811			May 21 04:00:58 PM PDT 24	May 21 04:45:58 PM PDT 24	10990402934 ps
T332	/workspace/coverage/default/82.chip_sw_all_escalation_resets.1129826246			May 21 04:21:48 PM PDT 24	May 21 04:31:26 PM PDT 24	4607379702 ps
T155	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.831374370			May 21 03:52:14 PM PDT 24	May 21 04:14:59 PM PDT 24	8330873152 ps
T42	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2914937194			May 21 04:00:00 PM PDT 24	May 21 04:57:13 PM PDT 24	13291666186 ps
T661	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2504029448			May 21 04:20:30 PM PDT 24	May 21 04:26:53 PM PDT 24	4407004080 ps
T47	/workspace/coverage/default/0.chip_tap_straps_testunlock0.1041723875			May 21 03:57:18 PM PDT 24	May 21 04:13:45 PM PDT 24	8135244789 ps
T659	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.543313039			May 21 04:20:05 PM PDT 24	May 21 04:25:08 PM PDT 24	3750990188 ps
T191	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.4124635675			May 21 04:11:28 PM PDT 24	May 21 04:31:21 PM PDT 24	7555048210 ps
T665	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1873116876			May 21 04:20:50 PM PDT 24	May 21 04:27:14 PM PDT 24	4431058624 ps
T314	/workspace/coverage/default/2.chip_sw_hmac_enc.1117655098			May 21 04:11:25 PM PDT 24	May 21 04:15:10 PM PDT 24	2553846116 ps
T870	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.3620853530			May 21 03:59:47 PM PDT 24	May 21 04:17:48 PM PDT 24	5866860560 ps
T83	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2950194362			May 21 04:00:11 PM PDT 24	May 21 07:22:05 PM PDT 24	254824384664 ps
T381	/workspace/coverage/default/2.chip_sw_kmac_app_rom.3514091748			May 21 04:13:05 PM PDT 24	May 21 04:17:59 PM PDT 24	2643541520 ps
T157	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2414834527			May 21 04:10:55 PM PDT 24	May 21 04:59:01 PM PDT 24	14741542336 ps
T48	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3280311288			May 21 04:02:55 PM PDT 24	May 21 04:14:46 PM PDT 24	5960712204 ps
T646	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.578481456			May 21 04:10:45 PM PDT 24	May 21 04:17:57 PM PDT 24	3836882652 ps
T242	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.4117366369			May 21 04:23:51 PM PDT 24	May 21 04:30:00 PM PDT 24	3416903734 ps
T298	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.4207959528			May 21 04:03:31 PM PDT 24	May 21 04:12:54 PM PDT 24	5531010538 ps
T140	/workspace/coverage/default/41.chip_sw_all_escalation_resets.3201695554			May 21 04:19:23 PM PDT 24	May 21 04:29:17 PM PDT 24	4874689494 ps
T299	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2579666540			May 21 04:12:19 PM PDT 24	May 21 04:18:14 PM PDT 24	3064938216 ps
T300	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2708038629			May 21 03:59:20 PM PDT 24	May 21 04:15:56 PM PDT 24	6264464681 ps
T211	/workspace/coverage/default/60.chip_sw_all_escalation_resets.2441876059			May 21 04:21:52 PM PDT 24	May 21 04:31:20 PM PDT 24	4592406576 ps
T199	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.754228468			May 21 03:51:54 PM PDT 24	May 21 04:02:52 PM PDT 24	5278163762 ps
T301	/workspace/coverage/default/83.chip_sw_all_escalation_resets.2743253358			May 21 04:21:48 PM PDT 24	May 21 04:32:24 PM PDT 24	4123066708 ps
T302	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3457598957			May 21 04:16:39 PM PDT 24	May 21 04:38:06 PM PDT 24	9122965889 ps
T19	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3323233969			May 21 04:08:53 PM PDT 24	May 21 04:33:16 PM PDT 24	22526801260 ps
T53	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3302032073			May 21 03:58:53 PM PDT 24	May 21 04:07:43 PM PDT 24	4549062370 ps
T419	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.3486081463			May 21 04:08:23 PM PDT 24	May 21 04:26:58 PM PDT 24	5721996776 ps
T15	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2215265074			May 21 03:57:27 PM PDT 24	May 21 04:40:37 PM PDT 24	13250069951 ps
T84	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1891322210			May 21 04:03:35 PM PDT 24	May 21 04:32:35 PM PDT 24	7358459032 ps
T190	/workspace/coverage/default/1.chip_sw_kmac_entropy.3800113890			May 21 03:59:20 PM PDT 24	May 21 04:02:25 PM PDT 24	2615862000 ps
T152	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.186205371			May 21 04:02:20 PM PDT 24	May 21 04:21:47 PM PDT 24	6474137298 ps
T159	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2522538663			May 21 04:10:45 PM PDT 24	May 21 04:19:38 PM PDT 24	5692634592 ps
T342	/workspace/coverage/default/1.chip_sw_aon_timer_irq.2036828149			May 21 04:05:47 PM PDT 24	May 21 04:11:45 PM PDT 24	4018588152 ps
T373	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3826813012			May 21 04:21:45 PM PDT 24	May 21 04:29:40 PM PDT 24	3419571464 ps
T174	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4003120195			May 21 04:12:18 PM PDT 24	May 21 04:21:50 PM PDT 24	5840759564 ps
T326	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2687207277			May 21 04:16:28 PM PDT 24	May 21 04:23:03 PM PDT 24	2913495250 ps
T240	/workspace/coverage/default/1.chip_sw_edn_auto_mode.439304902			May 21 04:01:59 PM PDT 24	May 21 04:19:37 PM PDT 24	4598513750 ps
T362	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.4056656386			May 21 04:22:02 PM PDT 24	May 21 04:28:16 PM PDT 24	3565693678 ps
T871	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2223006885			May 21 04:02:26 PM PDT 24	May 21 04:13:29 PM PDT 24	4518557898 ps
T89	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2117891447			May 21 04:09:12 PM PDT 24	May 21 04:29:46 PM PDT 24	7090801224 ps
T657	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3328743057			May 21 04:21:04 PM PDT 24	May 21 04:26:02 PM PDT 24	3669565650 ps
T134	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1223722176			May 21 04:00:56 PM PDT 24	May 21 05:01:20 PM PDT 24	17225125300 ps
T73	/workspace/coverage/default/0.chip_tap_straps_rma.532501481			May 21 03:53:59 PM PDT 24	May 21 04:00:55 PM PDT 24	4192889241 ps
T36	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2912392058			May 21 03:59:33 PM PDT 24	May 21 04:09:19 PM PDT 24	5205819320 ps
T291	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.927546086			May 21 03:58:04 PM PDT 24	May 21 04:07:16 PM PDT 24	5767044040 ps
T114	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.975333971			May 21 04:16:09 PM PDT 24	May 21 04:25:24 PM PDT 24	3632922792 ps
T122	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3597847116			May 21 04:15:52 PM PDT 24	May 21 04:29:40 PM PDT 24	4272424662 ps
T123	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3925589514			May 21 03:55:43 PM PDT 24	May 21 04:02:25 PM PDT 24	4235804072 ps
T124	/workspace/coverage/default/30.chip_sw_all_escalation_resets.1806569895			May 21 04:23:37 PM PDT 24	May 21 04:33:34 PM PDT 24	5062797356 ps
T125	/workspace/coverage/default/27.chip_sw_all_escalation_resets.979172664			May 21 04:19:37 PM PDT 24	May 21 04:29:13 PM PDT 24	4769959392 ps
T18	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.2292642253			May 21 03:52:18 PM PDT 24	May 21 04:01:45 PM PDT 24	4290804502 ps
T126	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3996051289			May 21 04:00:38 PM PDT 24	May 21 04:08:32 PM PDT 24	4432467100 ps
T127	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2248866704			May 21 03:53:46 PM PDT 24	May 21 04:09:35 PM PDT 24	4914898602 ps
T128	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.462633070			May 21 04:21:48 PM PDT 24	May 21 04:27:51 PM PDT 24	3687219356 ps
T129	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2458180785			May 21 04:12:52 PM PDT 24	May 21 04:32:40 PM PDT 24	6958702884 ps
T43	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2549618361			May 21 04:04:41 PM PDT 24	May 21 05:20:58 PM PDT 24	13884896760 ps
T385	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1572939954			May 21 04:17:35 PM PDT 24	May 21 04:24:58 PM PDT 24	4339691904 ps
T872	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4001397528			May 21 04:02:49 PM PDT 24	May 21 04:21:18 PM PDT 24	8528820383 ps
T181	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3538284374			May 21 04:17:59 PM PDT 24	May 21 04:26:28 PM PDT 24	4113049874 ps
T873	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1897382723			May 21 04:06:50 PM PDT 24	May 21 04:17:55 PM PDT 24	4188058110 ps
T185	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.4268141227			May 21 04:12:59 PM PDT 24	May 21 04:21:48 PM PDT 24	4731604925 ps
T337	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.38728309			May 21 03:56:04 PM PDT 24	May 21 04:01:18 PM PDT 24	2962564214 ps
T212	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2251543037			May 21 04:03:12 PM PDT 24	May 21 04:23:38 PM PDT 24	7484002028 ps
T874	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2056200094			May 21 04:08:51 PM PDT 24	May 21 05:04:45 PM PDT 24	16127746324 ps
T875	/workspace/coverage/default/1.chip_sw_kmac_smoketest.264067540			May 21 04:07:16 PM PDT 24	May 21 04:11:58 PM PDT 24	2600887286 ps
T876	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.194211095			May 21 03:52:33 PM PDT 24	May 21 03:56:36 PM PDT 24	2615834500 ps
T877	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.217272862			May 21 03:59:47 PM PDT 24	May 21 04:16:10 PM PDT 24	5529523293 ps
T658	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1743504795			May 21 04:19:45 PM PDT 24	May 21 04:25:52 PM PDT 24	2868725478 ps
T196	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3088422366			May 21 03:59:58 PM PDT 24	May 21 04:06:19 PM PDT 24	2921516335 ps
T221	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2172906616			May 21 04:14:45 PM PDT 24	May 21 04:26:22 PM PDT 24	5567042280 ps
T260	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2331127706			May 21 04:22:06 PM PDT 24	May 21 04:29:04 PM PDT 24	3603922536 ps
T261	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.4092839834			May 21 04:12:18 PM PDT 24	May 21 05:04:06 PM PDT 24	14754049176 ps
T262	/workspace/coverage/default/1.rom_e2e_smoke.947052862			May 21 04:10:46 PM PDT 24	May 21 04:56:56 PM PDT 24	14076475296 ps
T263	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3169620093			May 21 04:02:06 PM PDT 24	May 21 04:29:29 PM PDT 24	8227357480 ps
T264	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3915174159			May 21 04:14:11 PM PDT 24	May 21 04:21:41 PM PDT 24	5219783672 ps
T265	/workspace/coverage/default/74.chip_sw_all_escalation_resets.3277430869			May 21 04:21:08 PM PDT 24	May 21 04:29:29 PM PDT 24	5329319530 ps
T11	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.2629836492			May 21 04:06:59 PM PDT 24	May 21 04:17:14 PM PDT 24	6284803919 ps
T266	/workspace/coverage/default/49.chip_sw_all_escalation_resets.1372661404			May 21 04:20:06 PM PDT 24	May 21 04:29:54 PM PDT 24	6131344958 ps
T267	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2725493146			May 21 03:54:08 PM PDT 24	May 21 04:02:15 PM PDT 24	5215337440 ps
T222	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2241219287			May 21 03:50:57 PM PDT 24	May 21 03:58:17 PM PDT 24	4884028680 ps
T135	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.936909731			May 21 04:17:48 PM PDT 24	May 21 05:18:50 PM PDT 24	25036050586 ps
T274	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3431926911			May 21 04:17:52 PM PDT 24	May 21 04:26:36 PM PDT 24	3831105236 ps
T275	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.443556105			May 21 04:08:48 PM PDT 24	May 21 04:57:31 PM PDT 24	31897326469 ps
T276	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1731757474			May 21 04:14:48 PM PDT 24	May 21 04:58:22 PM PDT 24	13122558781 ps
T277	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.4211844752			May 21 04:01:51 PM PDT 24	May 21 04:07:14 PM PDT 24	3482496845 ps
T182	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2924409781			May 21 03:59:05 PM PDT 24	May 21 04:08:28 PM PDT 24	3726066216 ps
T278	/workspace/coverage/default/1.rom_keymgr_functest.1916487707			May 21 04:06:19 PM PDT 24	May 21 04:15:55 PM PDT 24	5127568872 ps
T223	/workspace/coverage/default/25.chip_sw_all_escalation_resets.246139733			May 21 04:18:29 PM PDT 24	May 21 04:30:43 PM PDT 24	5458485476 ps
T79	/workspace/coverage/default/2.chip_sw_all_escalation_resets.310424720			May 21 04:06:09 PM PDT 24	May 21 04:19:29 PM PDT 24	5573601740 ps
T878	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.797318731			May 21 04:12:06 PM PDT 24	May 21 05:14:22 PM PDT 24	14470681558 ps
T156	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2749926542			May 21 04:01:09 PM PDT 24	May 21 04:11:59 PM PDT 24	5274845312 ps
T226	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.298216421			May 21 04:21:22 PM PDT 24	May 21 04:27:34 PM PDT 24	3735658180 ps
T116	/workspace/coverage/default/78.chip_sw_all_escalation_resets.2736227688			May 21 04:22:17 PM PDT 24	May 21 04:33:48 PM PDT 24	5298631170 ps
T207	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3906139686			May 21 04:17:48 PM PDT 24	May 21 04:31:24 PM PDT 24	3553241162 ps
T160	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.784823413			May 21 04:05:20 PM PDT 24	May 21 04:15:24 PM PDT 24	6707187706 ps
T281	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.2691813446			May 21 04:12:21 PM PDT 24	May 21 04:29:17 PM PDT 24	6032299016 ps
T282	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1242509898			May 21 04:03:56 PM PDT 24	May 21 04:35:03 PM PDT 24	9880484224 ps
T177	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1934624117			May 21 03:59:04 PM PDT 24	May 21 07:02:40 PM PDT 24	63726000862 ps
T283	/workspace/coverage/default/0.chip_plic_all_irqs_0.2700316282			May 21 03:53:35 PM PDT 24	May 21 04:12:14 PM PDT 24	5839366908 ps
T51	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2634616914			May 21 03:58:09 PM PDT 24	May 21 04:16:37 PM PDT 24	16821261162 ps
T284	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.4189193852			May 21 04:16:39 PM PDT 24	May 21 04:29:13 PM PDT 24	4646808056 ps
T879	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.895682710			May 21 03:52:49 PM PDT 24	May 21 03:57:53 PM PDT 24	2464651960 ps
T209	/workspace/coverage/default/3.chip_tap_straps_prod.18261927			May 21 04:14:36 PM PDT 24	May 21 04:17:13 PM PDT 24	2501460095 ps
T660	/workspace/coverage/default/8.chip_sw_all_escalation_resets.926318667			May 21 04:17:23 PM PDT 24	May 21 04:26:58 PM PDT 24	5014974040 ps
T880	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2234032525			May 21 03:59:55 PM PDT 24	May 21 04:54:34 PM PDT 24	14198230360 ps
T52	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.493206782			May 21 03:54:29 PM PDT 24	May 21 04:27:11 PM PDT 24	23589623800 ps
T139	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3652973158			May 21 04:09:09 PM PDT 24	May 21 04:37:14 PM PDT 24	11812237820 ps
T881	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1305579001			May 21 04:12:04 PM PDT 24	May 21 04:19:50 PM PDT 24	3238665560 ps
T64	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3583733116			May 21 04:04:20 PM PDT 24	May 21 04:14:03 PM PDT 24	5247940860 ps
T424	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3013232983			May 21 04:13:52 PM PDT 24	May 21 04:17:14 PM PDT 24	2267495302 ps
T882	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3816635101			May 21 04:05:30 PM PDT 24	May 21 04:15:08 PM PDT 24	5136569572 ps
T154	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.940154837			May 21 03:54:32 PM PDT 24	May 21 04:13:33 PM PDT 24	6231636497 ps
T304	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2453222260			May 21 04:21:48 PM PDT 24	May 21 04:28:22 PM PDT 24	4048205976 ps
T725	/workspace/coverage/default/28.chip_sw_all_escalation_resets.4252346706			May 21 04:20:26 PM PDT 24	May 21 04:31:28 PM PDT 24	5547484900 ps
T39	/workspace/coverage/default/0.chip_sw_spi_device_tpm.2688709502			May 21 03:57:11 PM PDT 24	May 21 04:05:40 PM PDT 24	3831650255 ps
T883	/workspace/coverage/default/2.chip_sw_aes_idle.329377381			May 21 04:12:12 PM PDT 24	May 21 04:16:32 PM PDT 24	2541230080 ps
T357	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.95334487			May 21 04:02:38 PM PDT 24	May 21 05:10:03 PM PDT 24	18169385674 ps
T662	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3189677972			May 21 04:22:07 PM PDT 24	May 21 04:27:57 PM PDT 24	3861231240 ps
T235	/workspace/coverage/default/2.chip_sw_rv_timer_irq.121247352			May 21 04:08:16 PM PDT 24	May 21 04:12:55 PM PDT 24	2472083432 ps
T213	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2910319066			May 21 04:02:24 PM PDT 24	May 21 04:48:09 PM PDT 24	10762665250 ps
T884	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4065761634			May 21 04:05:49 PM PDT 24	May 21 04:26:58 PM PDT 24	7093615128 ps
T22	/workspace/coverage/default/0.chip_sw_usbdev_config_host.3393813172			May 21 03:55:56 PM PDT 24	May 21 04:29:20 PM PDT 24	7681045518 ps
T885	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.120148219			May 21 04:14:27 PM PDT 24	May 21 04:22:32 PM PDT 24	4618992968 ps
T327	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1548827452			May 21 04:15:25 PM PDT 24	May 21 04:39:28 PM PDT 24	8288640155 ps
T886	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2546675360			May 21 03:53:40 PM PDT 24	May 21 03:57:19 PM PDT 24	3717686933 ps
T887	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2433456972			May 21 03:59:46 PM PDT 24	May 21 04:08:43 PM PDT 24	6480015502 ps
T888	/workspace/coverage/default/1.chip_sw_edn_sw_mode.3058414897			May 21 04:01:29 PM PDT 24	May 21 04:28:18 PM PDT 24	8134016766 ps
T97	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.135414296			May 21 04:01:41 PM PDT 24	May 21 04:54:31 PM PDT 24	13987627610 ps
T889	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3046080349			May 21 03:54:56 PM PDT 24	May 21 04:02:09 PM PDT 24	5618217400 ps
T890	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3282409577			May 21 03:56:44 PM PDT 24	May 21 04:11:27 PM PDT 24	8013875994 ps
T142	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1739420485			May 21 03:56:23 PM PDT 24	May 21 04:06:44 PM PDT 24	5378777589 ps
T80	/workspace/coverage/default/38.chip_sw_all_escalation_resets.2172505845			May 21 04:20:46 PM PDT 24	May 21 04:29:42 PM PDT 24	4804498862 ps
T69	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1964301843			May 21 04:01:32 PM PDT 24	May 21 04:13:48 PM PDT 24	8043694965 ps
T320	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3218343692			May 21 04:11:32 PM PDT 24	May 21 04:32:14 PM PDT 24	6672041126 ps
T366	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2677920712			May 21 04:26:17 PM PDT 24	May 21 04:31:32 PM PDT 24	3813790962 ps
T143	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2303324606			May 21 04:12:06 PM PDT 24	May 21 04:24:18 PM PDT 24	5849124575 ps
T315	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3153934379			May 21 03:53:25 PM PDT 24	May 21 04:04:08 PM PDT 24	3852199232 ps
T65	/workspace/coverage/default/2.chip_jtag_csr_rw.107144833			May 21 04:04:24 PM PDT 24	May 21 04:42:39 PM PDT 24	19024952352 ps
T649	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2867852332			May 21 04:20:04 PM PDT 24	May 21 04:26:12 PM PDT 24	3210964482 ps
T663	/workspace/coverage/default/87.chip_sw_all_escalation_resets.3495703233			May 21 04:23:50 PM PDT 24	May 21 04:30:53 PM PDT 24	4905471088 ps
T316	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2213646323			May 21 04:00:03 PM PDT 24	May 21 04:12:05 PM PDT 24	4467418066 ps
T891	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2011012384			May 21 04:03:36 PM PDT 24	May 21 04:08:10 PM PDT 24	2136547656 ps
T892	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1045822166			May 21 04:02:16 PM PDT 24	May 21 04:11:30 PM PDT 24	4612173296 ps
T144	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3921848736			May 21 04:10:21 PM PDT 24	May 21 04:20:57 PM PDT 24	5363307419 ps
T893	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1816875120			May 21 04:00:10 PM PDT 24	May 21 04:19:03 PM PDT 24	6719199860 ps
T340	/workspace/coverage/default/7.chip_sw_all_escalation_resets.2951510846			May 21 04:16:50 PM PDT 24	May 21 04:30:47 PM PDT 24	5918303320 ps
T894	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3272066627			May 21 04:13:04 PM PDT 24	May 21 04:22:59 PM PDT 24	4701443876 ps
T715	/workspace/coverage/default/70.chip_sw_all_escalation_resets.1756113753			May 21 04:21:27 PM PDT 24	May 21 04:30:42 PM PDT 24	4886387640 ps
T350	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4079535717			May 21 03:54:38 PM PDT 24	May 21 04:01:46 PM PDT 24	5901563704 ps
T895	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2786972126			May 21 04:02:25 PM PDT 24	May 21 04:05:39 PM PDT 24	2554165036 ps
T896	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1010210511			May 21 04:09:22 PM PDT 24	May 21 04:23:50 PM PDT 24	5323197120 ps
T897	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2388337594			May 21 03:52:00 PM PDT 24	May 21 04:13:39 PM PDT 24	8722710876 ps
T339	/workspace/coverage/default/58.chip_sw_all_escalation_resets.1277132488			May 21 04:25:30 PM PDT 24	May 21 04:35:51 PM PDT 24	5908367680 ps
T664	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.853212958			May 21 04:21:26 PM PDT 24	May 21 04:27:38 PM PDT 24	3395494312 ps
T379	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1474221717			May 21 03:56:17 PM PDT 24	May 21 04:05:14 PM PDT 24	5837524180 ps
T382	/workspace/coverage/default/1.chip_sw_kmac_app_rom.1414649909			May 21 04:02:50 PM PDT 24	May 21 04:06:08 PM PDT 24	2576632700 ps
T898	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3995373291			May 21 04:07:34 PM PDT 24	May 21 04:17:06 PM PDT 24	3629034678 ps
T899	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.471543633			May 21 04:21:46 PM PDT 24	May 21 04:44:24 PM PDT 24	8869327004 ps
T900	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.863503346			May 21 03:59:14 PM PDT 24	May 21 04:02:19 PM PDT 24	2476763566 ps
T109	/workspace/coverage/default/1.chip_tap_straps_rma.3387331706			May 21 04:03:55 PM PDT 24	May 21 04:06:13 PM PDT 24	2346582873 ps
T901	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2440641066			May 21 04:04:05 PM PDT 24	May 21 04:15:06 PM PDT 24	3444340102 ps
T902	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2432266175			May 21 03:55:22 PM PDT 24	May 21 04:23:48 PM PDT 24	10037942043 ps
T903	/workspace/coverage/default/0.chip_sw_aes_idle.3986974201			May 21 04:04:21 PM PDT 24	May 21 04:08:42 PM PDT 24	3193119962 ps
T161	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1484948014			May 21 03:56:03 PM PDT 24	May 21 04:03:35 PM PDT 24	5351423724 ps
T768	/workspace/coverage/default/92.chip_sw_all_escalation_resets.188689122			May 21 04:22:59 PM PDT 24	May 21 04:32:37 PM PDT 24	6018363720 ps
T904	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3842698336			May 21 04:00:44 PM PDT 24	May 21 04:56:15 PM PDT 24	11171884168 ps
T905	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1504519955			May 21 03:54:24 PM PDT 24	May 21 04:26:55 PM PDT 24	8145441298 ps
T906	/workspace/coverage/default/2.chip_sw_edn_kat.2594705905			May 21 04:09:25 PM PDT 24	May 21 04:21:01 PM PDT 24	3615716990 ps
T672	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1661886162			May 21 04:10:16 PM PDT 24	May 21 04:15:17 PM PDT 24	3039983576 ps
T907	/workspace/coverage/default/0.chip_sw_kmac_smoketest.3221951898			May 21 04:01:36 PM PDT 24	May 21 04:07:14 PM PDT 24	3090805284 ps
T908	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.758143682			May 21 03:55:31 PM PDT 24	May 21 04:25:47 PM PDT 24	8258410960 ps
T257	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.801942860			May 21 03:56:59 PM PDT 24	May 21 04:06:40 PM PDT 24	8605314294 ps
T268	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.530301973			May 21 03:53:16 PM PDT 24	May 21 04:04:09 PM PDT 24	5126573374 ps
T200	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2933737460			May 21 04:07:15 PM PDT 24	May 21 04:21:37 PM PDT 24	5800299004 ps
T236	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3884372596			May 21 04:17:13 PM PDT 24	May 21 04:23:46 PM PDT 24	3269897048 ps
T909	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2093649191			May 21 04:04:42 PM PDT 24	May 21 04:09:38 PM PDT 24	2888398064 ps
T656	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2553680208			May 21 04:20:00 PM PDT 24	May 21 04:27:28 PM PDT 24	3734896106 ps
T70	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1054259816			May 21 04:10:48 PM PDT 24	May 21 04:23:00 PM PDT 24	5306940456 ps
T910	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3902129441			May 21 04:05:51 PM PDT 24	May 21 04:09:27 PM PDT 24	2793567504 ps
T351	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.167764163			May 21 04:11:48 PM PDT 24	May 21 04:18:08 PM PDT 24	4720578390 ps
T911	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.32146992			May 21 03:57:02 PM PDT 24	May 21 04:02:50 PM PDT 24	4599390406 ps
T333	/workspace/coverage/default/36.chip_sw_all_escalation_resets.516677568			May 21 04:24:32 PM PDT 24	May 21 04:35:44 PM PDT 24	5286764880 ps
T718	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3380207654			May 21 04:22:10 PM PDT 24	May 21 04:28:03 PM PDT 24	3667268556 ps
T24	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3176531683			May 21 04:06:35 PM PDT 24	May 21 04:13:07 PM PDT 24	4088129106 ps
T386	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3697228921			May 21 04:18:00 PM PDT 24	May 21 04:26:10 PM PDT 24	3415606240 ps
T388	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2605818372			May 21 04:20:28 PM PDT 24	May 21 04:28:05 PM PDT 24	4009121370 ps
T369	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3589522985			May 21 03:55:36 PM PDT 24	May 21 04:12:00 PM PDT 24	10915143720 ps
T389	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.715587098			May 21 04:16:49 PM PDT 24	May 21 04:26:30 PM PDT 24	4032498652 ps
T390	/workspace/coverage/default/96.chip_sw_all_escalation_resets.774350506			May 21 04:23:38 PM PDT 24	May 21 04:33:16 PM PDT 24	4625063208 ps