Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	140639	1			T61	86		T62	1		T63	240
values[2]	11857	1			T61	1		T62	1		T63	3
values[3]	4604	1			T62	1		T230	11		T403	83
values[4]	2638	1			T62	1		T230	13		T403	48
values[5]	1839	1			T62	1		T230	8		T403	31
values[6]	1308	1			T62	1		T230	14		T403	12
values[7]	982	1			T62	1		T230	5		T403	5
values[8]	702	1			T62	1		T230	7		T403	4
values[9]	665	1			T62	1		T230	7		T430	1
values[10]	507	1			T62	1		T230	3		T430	1
values[11]	453	1			T62	1		T230	7		T430	1
values[12]	427	1			T62	1		T230	4		T430	1
values[13]	405	1			T62	1		T230	5		T430	1
values[14]	404	1			T62	1		T230	13		T430	1
values[15]	408	1			T62	2		T230	9		T430	1
values[16]	375	1			T62	1		T230	8		T430	1
values[17]	397	1			T62	1		T230	4		T430	1
values[18]	414	1			T62	1		T230	9		T430	1
values[19]	349	1			T62	1		T230	13		T430	1
values[20]	381	1			T62	1		T230	11		T430	1
values[21]	338	1			T62	1		T230	11		T430	1
values[22]	323	1			T62	1		T230	6		T430	1
values[23]	382	1			T62	1		T230	7		T430	1
values[24]	336	1			T62	1		T230	5		T430	1
values[25]	342	1			T62	1		T230	4		T430	1
values[26]	307	1			T62	1		T230	7		T430	1
values[27]	349	1			T62	1		T230	8		T430	1
values[28]	323	1			T62	1		T230	8		T430	1
values[29]	332	1			T62	1		T230	4		T430	1
values[30]	320	1			T62	1		T230	6		T430	1
values[31]	344	1			T62	1		T230	2		T430	1
values[32]	322	1			T62	1		T230	8		T430	1
values[33]	319	1			T62	1		T230	3		T430	1
values[34]	336	1			T62	1		T230	8		T430	1
values[35]	314	1			T62	1		T230	4		T430	1
values[36]	298	1			T62	1		T230	5		T430	1
values[37]	319	1			T62	1		T230	7		T430	1
values[38]	369	1			T62	1		T230	10		T430	1
values[39]	350	1			T62	1		T230	8		T430	1
values[40]	332	1			T62	1		T230	11		T430	1
values[41]	330	1			T62	1		T230	22		T430	1
values[42]	336	1			T62	1		T230	5		T430	1
values[43]	333	1			T62	1		T430	1		T468	18
values[44]	315	1			T62	1		T430	2		T468	13
values[45]	330	1			T62	1		T430	1		T468	20
values[46]	343	1			T62	1		T430	1		T468	19
values[47]	301	1			T62	1		T430	1		T468	10
values[48]	346	1			T62	1		T430	1		T468	11
values[49]	340	1			T62	1		T430	1		T468	9
values[50]	295	1			T62	1		T430	1		T468	16
values[51]	321	1			T62	1		T430	1		T468	13
values[52]	294	1			T62	1		T430	1		T468	10
values[53]	294	1			T62	1		T430	1		T468	11
values[54]	250	1			T62	1		T430	1		T468	8
values[55]	261	1			T62	1		T430	1		T468	10
values[56]	247	1			T62	1		T430	1		T468	12
values[57]	299	1			T62	1		T430	1		T468	17
values[58]	255	1			T62	1		T430	1		T468	15
values[59]	246	1			T62	1		T430	1		T468	14
values[60]	209	1			T62	2		T430	1		T468	9
values[61]	216	1			T62	1		T430	1		T468	13
values[62]	191	1			T62	1		T430	1		T468	15
values[63]	199	1			T62	1		T430	1		T468	24
values[64]	203	1			T62	1		T430	1		T468	32
values[65]	180	1			T62	1		T430	1		T468	25
values[66]	145	1			T62	1		T430	1		T468	11
values[67]	135	1			T62	1		T430	1		T468	16
values[68]	140	1			T62	1		T430	1		T468	9
values[69]	124	1			T62	1		T430	1		T468	9
values[70]	105	1			T62	1		T430	1		T468	8
values[71]	140	1			T62	1		T430	1		T468	12
values[72]	123	1			T62	1		T430	1		T468	16
values[73]	141	1			T62	1		T430	1		T468	7
values[74]	113	1			T62	1		T430	1		T804	2
values[75]	108	1			T62	1		T430	1		T804	2
values[76]	102	1			T62	1		T430	1		T804	2
values[77]	84	1			T62	1		T430	1		T804	4
values[78]	84	1			T62	1		T430	1		T804	2
values[79]	87	1			T62	1		T430	1		T804	6
values[80]	90	1			T62	1		T430	2		T804	6
values[81]	103	1			T62	1		T430	1		T804	5
values[82]	93	1			T62	1		T430	1		T804	2
values[83]	103	1			T62	1		T430	1		T804	3
values[84]	84	1			T62	1		T430	1		T804	2
values[85]	80	1			T62	1		T430	1		T804	3
values[86]	83	1			T62	1		T430	1		T804	4
values[87]	87	1			T62	1		T430	1		T804	1
values[88]	87	1			T62	1		T430	1		T804	5
values[89]	101	1			T62	1		T430	1		T804	4
values[90]	91	1			T62	1		T430	1		T804	1
values[91]	115	1			T62	1		T430	1		T804	1
values[92]	90	1			T62	2		T430	1		T804	2
values[93]	83	1			T62	2		T430	1		T804	6
values[94]	101	1			T62	1		T430	1		T804	8
values[95]	87	1			T62	1		T430	1		T804	1
values[96]	103	1			T62	1		T430	1		T804	2
values[97]	89	1			T62	1		T430	1		T804	1
values[98]	66	1			T62	2		T430	1		T804	1
values[99]	85	1			T62	7		T430	1		T804	3
values[100]	92	1			T62	3		T430	2		T804	3
values[101]	78	1			T62	2		T430	1		T804	4
values[102]	79	1			T62	5		T430	1		T804	2
values[103]	77	1			T62	2		T430	1		T804	5
values[104]	85	1			T62	3		T430	1		T804	5
values[105]	77	1			T62	1		T430	1		T804	3
values[106]	67	1			T62	6		T430	1		T804	2
values[107]	85	1			T62	4		T430	1		T804	1
values[108]	83	1			T62	3		T430	1		T804	2
values[109]	82	1			T62	1		T430	1		T804	2
values[110]	60	1			T62	4		T430	1		T804	2
values[111]	85	1			T62	5		T430	1		T804	2
values[112]	80	1			T62	6		T430	1		T804	1
values[113]	51	1			T62	1		T430	1		T804	2
values[114]	60	1			T62	1		T430	1		T804	2
values[115]	72	1			T62	1		T430	1		T804	5
values[116]	78	1			T62	3		T430	1		T804	14
values[117]	64	1			T62	2		T430	2		T804	8
values[118]	72	1			T62	2		T430	2		T804	6
values[119]	49	1			T62	1		T430	2		T804	2
values[120]	52	1			T62	1		T430	1		T804	6
values[121]	55	1			T62	1		T430	2		T804	2
values[122]	53	1			T62	2		T430	3		T804	1
values[123]	60	1			T62	1		T430	1		T804	2
values[124]	51	1			T62	1		T430	3		T804	1
values[125]	69	1			T62	2		T430	4		T455	8
values[126]	147	1			T62	1		T430	1		T455	34
values[127]	718	1			T62	31		T430	32		T455	50
values[128]	5480	1			T62	304		T430	391		T455	17