Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	144482	1			T61	96		T62	1		T63	243
values[2]	12762	1			T61	4		T62	1		T63	5
values[3]	4852	1			T62	1		T230	45		T487	1
values[4]	2669	1			T62	1		T230	28		T487	1
values[5]	1649	1			T62	1		T230	16		T487	1
values[6]	1186	1			T62	1		T230	25		T487	1
values[7]	792	1			T62	1		T230	18		T487	1
values[8]	642	1			T62	1		T230	11		T487	1
values[9]	534	1			T62	1		T230	22		T487	1
values[10]	502	1			T62	1		T230	23		T487	1
values[11]	395	1			T62	1		T230	10		T487	1
values[12]	319	1			T62	1		T230	6		T487	1
values[13]	306	1			T62	1		T230	8		T487	1
values[14]	275	1			T62	1		T487	1		T421	1
values[15]	212	1			T62	1		T487	1		T421	1
values[16]	262	1			T62	1		T487	1		T421	1
values[17]	264	1			T62	1		T487	1		T421	1
values[18]	233	1			T62	1		T487	1		T421	1
values[19]	265	1			T62	1		T487	1		T421	1
values[20]	261	1			T62	1		T487	1		T421	1
values[21]	234	1			T62	1		T487	1		T421	1
values[22]	282	1			T62	1		T487	1		T421	1
values[23]	243	1			T62	1		T487	1		T421	1
values[24]	231	1			T62	1		T487	1		T421	1
values[25]	228	1			T62	1		T487	1		T421	1
values[26]	270	1			T62	1		T487	1		T421	1
values[27]	217	1			T62	1		T487	1		T421	1
values[28]	258	1			T62	1		T487	1		T421	1
values[29]	251	1			T62	1		T487	1		T421	1
values[30]	249	1			T62	1		T487	1		T421	1
values[31]	254	1			T62	1		T487	1		T421	1
values[32]	216	1			T62	1		T487	1		T421	1
values[33]	278	1			T62	1		T487	1		T421	1
values[34]	218	1			T62	1		T487	2		T421	1
values[35]	258	1			T62	1		T487	1		T421	1
values[36]	249	1			T62	1		T487	1		T421	1
values[37]	201	1			T62	1		T487	1		T421	1
values[38]	215	1			T62	1		T487	1		T421	1
values[39]	234	1			T62	1		T487	1		T421	1
values[40]	228	1			T62	1		T487	1		T421	1
values[41]	221	1			T62	1		T487	1		T421	1
values[42]	220	1			T62	1		T487	2		T421	1
values[43]	235	1			T62	1		T487	1		T421	1
values[44]	225	1			T62	1		T487	1		T421	1
values[45]	203	1			T62	1		T487	1		T421	1
values[46]	185	1			T62	1		T487	1		T421	1
values[47]	161	1			T62	1		T487	1		T421	1
values[48]	172	1			T62	1		T487	1		T421	1
values[49]	205	1			T62	1		T487	1		T421	1
values[50]	175	1			T62	1		T487	1		T421	1
values[51]	204	1			T62	1		T487	1		T421	1
values[52]	183	1			T62	1		T487	1		T421	1
values[53]	180	1			T62	1		T487	1		T421	1
values[54]	205	1			T62	1		T487	1		T421	1
values[55]	180	1			T62	1		T487	1		T421	1
values[56]	148	1			T62	1		T487	1		T421	1
values[57]	170	1			T62	1		T487	1		T421	1
values[58]	195	1			T62	1		T487	1		T421	1
values[59]	190	1			T62	1		T487	1		T421	1
values[60]	144	1			T62	1		T487	1		T421	1
values[61]	160	1			T62	1		T487	1		T421	1
values[62]	125	1			T62	1		T487	1		T421	1
values[63]	118	1			T62	1		T487	1		T421	1
values[64]	142	1			T62	1		T487	1		T421	1
values[65]	134	1			T62	1		T487	1		T421	1
values[66]	130	1			T62	1		T487	1		T421	1
values[67]	101	1			T62	1		T487	1		T421	1
values[68]	104	1			T62	1		T487	1		T421	1
values[69]	122	1			T62	1		T487	1		T421	1
values[70]	109	1			T62	1		T487	1		T421	1
values[71]	100	1			T62	1		T487	1		T421	1
values[72]	103	1			T62	2		T487	1		T421	1
values[73]	81	1			T62	1		T487	1		T421	1
values[74]	71	1			T62	1		T487	1		T421	1
values[75]	96	1			T62	1		T487	1		T421	1
values[76]	85	1			T62	1		T487	1		T421	1
values[77]	107	1			T62	1		T487	1		T421	2
values[78]	81	1			T62	1		T487	1		T421	1
values[79]	79	1			T62	1		T487	1		T421	1
values[80]	70	1			T62	1		T487	1		T421	1
values[81]	70	1			T62	1		T487	1		T421	1
values[82]	58	1			T62	1		T487	1		T421	1
values[83]	55	1			T62	1		T487	1		T421	1
values[84]	66	1			T62	1		T487	2		T421	1
values[85]	68	1			T62	1		T487	4		T421	1
values[86]	49	1			T62	1		T487	3		T421	1
values[87]	81	1			T62	1		T487	2		T421	1
values[88]	64	1			T62	1		T487	1		T421	1
values[89]	69	1			T62	1		T487	2		T421	1
values[90]	68	1			T62	1		T487	2		T421	1
values[91]	67	1			T62	1		T487	1		T421	1
values[92]	77	1			T62	1		T487	3		T421	1
values[93]	76	1			T62	1		T487	1		T421	1
values[94]	72	1			T62	1		T487	1		T421	1
values[95]	77	1			T62	1		T487	2		T421	1
values[96]	90	1			T62	1		T487	4		T421	1
values[97]	68	1			T62	1		T487	1		T421	1
values[98]	81	1			T62	1		T487	2		T421	1
values[99]	91	1			T62	1		T487	1		T421	1
values[100]	90	1			T62	1		T487	1		T421	1
values[101]	105	1			T62	2		T487	1		T421	1
values[102]	60	1			T62	4		T487	1		T421	1
values[103]	72	1			T62	1		T487	1		T421	1
values[104]	70	1			T62	1		T487	1		T421	1
values[105]	71	1			T62	2		T487	4		T421	1
values[106]	91	1			T62	1		T487	3		T421	1
values[107]	82	1			T62	1		T487	1		T421	1
values[108]	75	1			T62	3		T487	4		T421	1
values[109]	67	1			T62	1		T487	1		T421	1
values[110]	67	1			T62	1		T487	3		T421	4
values[111]	54	1			T62	3		T487	2		T421	1
values[112]	62	1			T62	2		T487	2		T421	3
values[113]	63	1			T62	2		T487	2		T421	1
values[114]	48	1			T62	1		T487	3		T421	2
values[115]	62	1			T62	3		T487	4		T421	1
values[116]	54	1			T62	2		T487	2		T421	1
values[117]	56	1			T62	2		T487	1		T421	2
values[118]	58	1			T62	6		T487	1		T421	2
values[119]	51	1			T62	1		T487	3		T421	5
values[120]	42	1			T62	1		T487	4		T421	1
values[121]	45	1			T62	1		T487	3		T421	1
values[122]	52	1			T62	1		T487	1		T421	1
values[123]	49	1			T62	1		T487	1		T421	1
values[124]	54	1			T62	1		T487	2		T421	1
values[125]	63	1			T62	1		T487	1		T421	1
values[126]	119	1			T62	2		T487	1		T421	2
values[127]	788	1			T62	34		T487	29		T421	28
values[128]	6247	1			T62	355		T487	298		T421	345