Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	155105	1			T61	125		T63	258		T67	85
values[2]	5034	1			T61	5		T63	3		T426	1
values[3]	2449	1			T432	2		T667	3		T427	1
values[4]	1711	1			T432	1		T667	4		T427	1
values[5]	1282	1			T432	1		T667	5		T819	68
values[6]	1118	1			T432	1		T667	5		T819	70
values[7]	993	1			T432	2		T667	4		T819	80
values[8]	811	1			T432	1		T667	3		T819	93
values[9]	739	1			T432	3		T667	1		T819	81
values[10]	721	1			T432	2		T667	6		T819	44
values[11]	605	1			T432	1		T667	4		T819	34
values[12]	576	1			T432	1		T667	4		T819	17
values[13]	513	1			T432	2		T667	2		T819	15
values[14]	515	1			T432	1		T667	1		T819	27
values[15]	613	1			T432	1		T667	3		T819	38
values[16]	557	1			T432	1		T667	1		T819	37
values[17]	534	1			T432	2		T667	4		T819	18
values[18]	513	1			T432	2		T667	1		T819	2
values[19]	521	1			T432	2		T667	1		T430	1
values[20]	466	1			T432	4		T667	1		T430	1
values[21]	372	1			T432	5		T667	7		T430	1
values[22]	308	1			T432	1		T667	1		T430	1
values[23]	252	1			T432	4		T667	2		T430	1
values[24]	195	1			T432	1		T667	2		T430	1
values[25]	187	1			T432	1		T667	2		T430	1
values[26]	180	1			T432	2		T667	1		T430	1
values[27]	177	1			T432	1		T667	1		T430	1
values[28]	193	1			T432	3		T667	2		T430	1
values[29]	195	1			T432	7		T667	1		T430	1
values[30]	213	1			T432	7		T667	1		T430	1
values[31]	204	1			T432	2		T667	3		T430	1
values[32]	174	1			T432	1		T667	1		T430	1
values[33]	164	1			T432	2		T667	1		T430	1
values[34]	141	1			T432	2		T667	4		T430	2
values[35]	155	1			T432	3		T667	2		T430	1
values[36]	125	1			T432	2		T667	1		T430	1
values[37]	170	1			T432	4		T667	3		T430	1
values[38]	164	1			T432	5		T667	1		T430	1
values[39]	132	1			T432	3		T667	2		T430	1
values[40]	111	1			T432	1		T667	2		T430	1
values[41]	95	1			T432	3		T667	1		T430	1
values[42]	99	1			T432	1		T667	1		T430	1
values[43]	104	1			T432	2		T667	2		T430	1
values[44]	99	1			T432	2		T667	2		T430	1
values[45]	97	1			T432	1		T667	7		T430	1
values[46]	120	1			T432	3		T667	1		T430	1
values[47]	108	1			T432	1		T667	3		T430	1
values[48]	68	1			T432	1		T667	1		T430	1
values[49]	69	1			T432	1		T667	2		T430	1
values[50]	64	1			T432	4		T667	1		T430	1
values[51]	63	1			T432	5		T667	3		T430	1
values[52]	66	1			T432	5		T667	4		T430	1
values[53]	63	1			T432	2		T667	1		T430	1
values[54]	79	1			T432	1		T667	3		T430	1
values[55]	59	1			T432	2		T667	6		T430	1
values[56]	60	1			T432	4		T667	3		T430	1
values[57]	58	1			T432	5		T667	4		T430	1
values[58]	57	1			T432	2		T667	3		T430	1
values[59]	67	1			T432	3		T667	1		T430	1
values[60]	61	1			T432	1		T667	3		T430	1
values[61]	64	1			T432	5		T667	1		T430	1
values[62]	68	1			T432	8		T667	2		T430	1
values[63]	71	1			T432	3		T667	2		T430	1
values[64]	67	1			T432	6		T667	3		T430	1
values[65]	67	1			T432	2		T667	2		T430	1
values[66]	58	1			T432	1		T667	2		T430	1
values[67]	55	1			T432	1		T667	2		T430	1
values[68]	54	1			T432	2		T667	2		T430	1
values[69]	60	1			T432	2		T667	1		T430	1
values[70]	55	1			T432	1		T667	3		T430	1
values[71]	59	1			T432	3		T667	1		T430	1
values[72]	66	1			T432	1		T667	2		T430	1
values[73]	56	1			T432	1		T667	5		T430	1
values[74]	64	1			T432	5		T667	2		T430	1
values[75]	69	1			T432	5		T667	2		T430	1
values[76]	65	1			T432	2		T667	3		T430	1
values[77]	60	1			T432	3		T667	4		T430	1
values[78]	68	1			T432	1		T667	5		T430	1
values[79]	72	1			T432	3		T667	3		T430	3
values[80]	63	1			T432	1		T667	1		T430	5
values[81]	71	1			T432	3		T667	1		T430	1
values[82]	75	1			T432	2		T667	4		T430	2
values[83]	83	1			T432	3		T667	3		T430	4
values[84]	92	1			T432	4		T667	2		T430	2
values[85]	79	1			T432	6		T667	1		T430	1
values[86]	91	1			T432	6		T667	5		T430	2
values[87]	88	1			T432	2		T667	7		T430	2
values[88]	85	1			T432	5		T667	5		T430	2
values[89]	83	1			T432	4		T667	11		T430	4
values[90]	106	1			T432	3		T667	7		T430	11
values[91]	100	1			T432	1		T667	4		T430	5
values[92]	78	1			T432	2		T667	5		T430	1
values[93]	86	1			T432	1		T667	8		T430	3
values[94]	80	1			T432	3		T667	4		T430	8
values[95]	72	1			T432	3		T667	3		T430	2
values[96]	75	1			T432	2		T667	2		T430	2
values[97]	88	1			T432	1		T667	3		T430	3
values[98]	97	1			T432	6		T667	3		T430	4
values[99]	102	1			T432	6		T667	2		T430	1
values[100]	88	1			T432	1		T667	3		T430	2
values[101]	96	1			T432	2		T667	3		T430	1
values[102]	95	1			T432	5		T667	5		T430	3
values[103]	93	1			T432	7		T667	4		T430	2
values[104]	101	1			T432	11		T667	6		T430	2
values[105]	80	1			T432	7		T667	5		T430	1
values[106]	81	1			T432	3		T667	5		T430	1
values[107]	102	1			T432	5		T667	7		T430	2
values[108]	94	1			T432	4		T667	3		T430	1
values[109]	100	1			T432	4		T667	1		T430	4
values[110]	109	1			T432	5		T667	2		T430	2
values[111]	105	1			T432	1		T667	1		T430	1
values[112]	119	1			T432	4		T667	1		T430	3
values[113]	102	1			T432	9		T667	6		T430	1
values[114]	111	1			T432	5		T667	19		T430	1
values[115]	119	1			T432	3		T667	14		T430	1
values[116]	130	1			T432	6		T667	8		T430	2
values[117]	132	1			T432	1		T667	17		T430	5
values[118]	125	1			T432	3		T667	18		T430	2
values[119]	115	1			T432	2		T667	13		T430	1
values[120]	99	1			T432	3		T667	9		T430	1
values[121]	83	1			T432	2		T667	3		T430	2
values[122]	88	1			T432	3		T667	5		T430	2
values[123]	130	1			T432	9		T667	5		T430	3
values[124]	191	1			T432	10		T667	13		T430	2
values[125]	348	1			T432	36		T667	32		T430	4
values[126]	793	1			T432	49		T667	36		T430	8
values[127]	3007	1			T432	30		T667	11		T430	93
values[128]	4860	1			T432	1		T430	213		T809	216