Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139054	1			T61	100		T63	229		T67	80
values[2]	10414	1			T61	1		T63	4		T67	1
values[3]	4075	1			T487	1		T489	23		T406	17
values[4]	2424	1			T487	1		T489	5		T406	7
values[5]	1574	1			T487	1		T406	2		T432	9
values[6]	972	1			T487	1		T432	2		T417	2
values[7]	687	1			T487	1		T432	5		T417	3
values[8]	567	1			T487	1		T432	13		T417	1
values[9]	450	1			T487	1		T432	15		T417	2
values[10]	430	1			T487	1		T432	12		T417	1
values[11]	368	1			T487	1		T432	16		T451	6
values[12]	319	1			T487	1		T432	14		T451	7
values[13]	330	1			T487	1		T432	7		T451	8
values[14]	271	1			T487	1		T432	2		T451	7
values[15]	237	1			T487	1		T451	8		T823	4
values[16]	253	1			T487	1		T451	5		T823	4
values[17]	255	1			T487	1		T451	5		T823	7
values[18]	258	1			T487	1		T451	18		T823	4
values[19]	252	1			T487	1		T451	11		T823	10
values[20]	296	1			T487	1		T451	6		T823	13
values[21]	230	1			T487	1		T451	5		T823	4
values[22]	272	1			T487	1		T451	8		T823	5
values[23]	239	1			T487	1		T451	8		T823	4
values[24]	281	1			T487	1		T451	9		T823	11
values[25]	271	1			T487	1		T451	8		T823	7
values[26]	288	1			T487	1		T451	11		T823	5
values[27]	274	1			T487	1		T451	11		T823	6
values[28]	238	1			T487	1		T451	7		T823	5
values[29]	217	1			T487	1		T451	8		T823	3
values[30]	212	1			T487	1		T451	9		T823	11
values[31]	206	1			T487	1		T451	6		T823	8
values[32]	220	1			T487	1		T451	7		T823	7
values[33]	270	1			T487	1		T451	4		T823	6
values[34]	278	1			T487	1		T451	5		T823	10
values[35]	278	1			T487	1		T451	12		T823	10
values[36]	267	1			T487	1		T451	14		T823	7
values[37]	285	1			T487	1		T451	14		T823	6
values[38]	248	1			T487	1		T451	12		T823	8
values[39]	259	1			T487	1		T451	5		T823	6
values[40]	300	1			T487	1		T451	3		T823	5
values[41]	253	1			T487	1		T451	6		T823	3
values[42]	227	1			T487	1		T451	11		T823	14
values[43]	233	1			T487	1		T451	9		T823	11
values[44]	241	1			T487	1		T451	10		T823	14
values[45]	260	1			T487	1		T451	11		T823	8
values[46]	203	1			T487	1		T451	10		T823	10
values[47]	219	1			T487	1		T451	10		T823	7
values[48]	244	1			T487	1		T451	6		T805	1
values[49]	231	1			T487	1		T451	6		T805	1
values[50]	239	1			T487	1		T451	5		T805	1
values[51]	219	1			T487	1		T451	5		T805	1
values[52]	227	1			T487	1		T451	3		T805	1
values[53]	216	1			T487	1		T451	6		T805	1
values[54]	214	1			T487	1		T451	2		T805	1
values[55]	219	1			T487	1		T451	7		T805	1
values[56]	206	1			T487	1		T451	6		T805	1
values[57]	231	1			T487	1		T451	3		T805	1
values[58]	185	1			T487	1		T451	7		T805	1
values[59]	229	1			T487	1		T451	6		T805	1
values[60]	216	1			T487	1		T451	7		T805	1
values[61]	188	1			T487	1		T451	6		T805	1
values[62]	189	1			T487	1		T451	4		T805	1
values[63]	172	1			T487	1		T451	8		T805	1
values[64]	148	1			T487	1		T451	9		T805	1
values[65]	152	1			T487	1		T451	6		T805	1
values[66]	130	1			T487	1		T451	10		T805	1
values[67]	110	1			T487	1		T451	12		T805	1
values[68]	98	1			T487	1		T805	1		T600	5
values[69]	82	1			T487	2		T805	1		T600	10
values[70]	107	1			T487	1		T805	1		T600	7
values[71]	101	1			T487	1		T805	1		T600	6
values[72]	85	1			T487	1		T805	1		T600	3
values[73]	54	1			T487	1		T805	1		T600	11
values[74]	42	1			T487	1		T805	1		T600	3
values[75]	51	1			T487	1		T805	1		T828	1
values[76]	54	1			T487	1		T805	1		T828	1
values[77]	54	1			T487	1		T805	1		T828	1
values[78]	60	1			T487	1		T805	1		T828	1
values[79]	57	1			T487	1		T805	1		T828	1
values[80]	44	1			T487	1		T805	1		T828	1
values[81]	44	1			T487	1		T805	1		T828	1
values[82]	57	1			T487	1		T805	1		T828	1
values[83]	46	1			T487	1		T805	1		T828	1
values[84]	54	1			T487	1		T805	1		T828	2
values[85]	52	1			T487	1		T805	1		T828	1
values[86]	66	1			T487	1		T805	1		T828	1
values[87]	43	1			T487	1		T805	1		T828	1
values[88]	49	1			T487	1		T805	1		T828	1
values[89]	42	1			T487	1		T805	1		T828	1
values[90]	41	1			T487	1		T805	1		T828	1
values[91]	52	1			T487	1		T805	2		T828	1
values[92]	43	1			T487	1		T805	2		T828	1
values[93]	42	1			T487	1		T805	1		T828	1
values[94]	51	1			T487	1		T805	1		T828	1
values[95]	62	1			T487	1		T805	1		T828	1
values[96]	50	1			T487	1		T805	1		T828	1
values[97]	65	1			T487	1		T805	2		T828	1
values[98]	53	1			T487	1		T805	1		T828	1
values[99]	60	1			T487	1		T805	2		T828	1
values[100]	49	1			T487	1		T805	1		T828	1
values[101]	62	1			T487	1		T805	3		T828	1
values[102]	68	1			T487	1		T805	1		T828	1
values[103]	54	1			T487	1		T805	2		T828	1
values[104]	51	1			T487	1		T805	2		T828	2
values[105]	53	1			T487	1		T805	2		T828	1
values[106]	50	1			T487	1		T805	1		T828	1
values[107]	60	1			T487	1		T805	2		T828	2
values[108]	60	1			T487	1		T805	1		T828	5
values[109]	59	1			T487	1		T805	3		T828	2
values[110]	47	1			T487	1		T805	2		T828	3
values[111]	58	1			T487	1		T805	2		T828	1
values[112]	48	1			T487	1		T805	1		T828	1
values[113]	63	1			T487	2		T805	3		T828	1
values[114]	69	1			T487	1		T805	3		T828	2
values[115]	60	1			T487	3		T805	4		T828	4
values[116]	49	1			T487	2		T805	1		T828	1
values[117]	54	1			T487	4		T805	1		T828	7
values[118]	51	1			T487	1		T805	1		T828	2
values[119]	57	1			T487	4		T805	3		T828	2
values[120]	48	1			T487	1		T805	1		T828	3
values[121]	49	1			T487	2		T805	2		T828	1
values[122]	50	1			T487	4		T805	1		T828	1
values[123]	66	1			T487	4		T805	2		T828	1
values[124]	62	1			T487	4		T805	2		T828	1
values[125]	79	1			T487	3		T805	2		T828	1
values[126]	121	1			T487	2		T805	4		T828	1
values[127]	786	1			T487	32		T805	34		T828	36
values[128]	6162	1			T487	280		T805	340		T828	330