Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	135824	1			T61	106		T62	1		T63	219
values[2]	10164	1			T61	2		T62	1		T63	4
values[3]	4133	1			T62	1		T230	33		T487	1
values[4]	2369	1			T62	1		T230	19		T487	1
values[5]	1467	1			T62	1		T230	29		T487	1
values[6]	969	1			T62	1		T230	24		T487	1
values[7]	771	1			T62	2		T230	14		T487	1
values[8]	635	1			T62	1		T230	4		T487	1
values[9]	477	1			T62	1		T230	5		T487	1
values[10]	385	1			T62	1		T230	11		T487	1
values[11]	366	1			T62	1		T230	5		T487	1
values[12]	335	1			T62	1		T230	10		T487	1
values[13]	328	1			T62	1		T230	4		T487	1
values[14]	359	1			T62	1		T230	9		T487	1
values[15]	278	1			T62	1		T230	5		T487	1
values[16]	366	1			T62	1		T230	8		T487	1
values[17]	338	1			T62	1		T230	7		T487	1
values[18]	384	1			T62	1		T230	5		T487	1
values[19]	308	1			T62	1		T230	7		T487	1
values[20]	289	1			T62	1		T230	3		T487	1
values[21]	293	1			T62	1		T230	4		T487	1
values[22]	279	1			T62	1		T230	4		T487	1
values[23]	301	1			T62	1		T230	5		T487	1
values[24]	322	1			T62	1		T230	7		T487	1
values[25]	289	1			T62	1		T230	10		T487	1
values[26]	280	1			T62	1		T230	10		T487	1
values[27]	304	1			T62	1		T230	8		T487	1
values[28]	315	1			T62	1		T230	8		T487	1
values[29]	266	1			T62	1		T230	12		T487	1
values[30]	273	1			T62	1		T230	11		T487	1
values[31]	310	1			T62	1		T230	10		T487	1
values[32]	299	1			T62	1		T230	8		T487	1
values[33]	308	1			T62	1		T230	6		T487	1
values[34]	289	1			T62	1		T230	3		T487	1
values[35]	309	1			T62	1		T230	4		T487	2
values[36]	345	1			T62	1		T230	6		T487	1
values[37]	266	1			T62	1		T230	3		T487	1
values[38]	241	1			T62	1		T230	4		T487	1
values[39]	265	1			T62	1		T230	6		T487	1
values[40]	268	1			T62	1		T230	4		T487	1
values[41]	270	1			T62	1		T230	8		T487	1
values[42]	283	1			T62	1		T230	22		T487	1
values[43]	319	1			T62	1		T230	4		T487	1
values[44]	248	1			T62	1		T230	11		T487	1
values[45]	240	1			T62	1		T230	6		T487	1
values[46]	235	1			T62	1		T230	10		T487	1
values[47]	231	1			T62	1		T230	4		T487	1
values[48]	250	1			T62	1		T230	7		T487	1
values[49]	282	1			T62	1		T230	4		T487	1
values[50]	289	1			T62	1		T230	5		T487	1
values[51]	255	1			T62	1		T230	9		T487	1
values[52]	210	1			T62	1		T230	5		T487	1
values[53]	211	1			T62	1		T230	6		T487	1
values[54]	212	1			T62	1		T230	8		T487	1
values[55]	254	1			T62	1		T230	9		T487	1
values[56]	223	1			T62	1		T230	11		T487	1
values[57]	226	1			T62	1		T230	6		T487	1
values[58]	240	1			T62	1		T230	3		T487	1
values[59]	177	1			T62	1		T230	9		T487	1
values[60]	194	1			T62	1		T230	6		T487	1
values[61]	246	1			T62	1		T230	7		T487	1
values[62]	246	1			T62	1		T230	7		T487	1
values[63]	206	1			T62	1		T230	5		T487	1
values[64]	238	1			T62	1		T230	5		T487	1
values[65]	207	1			T62	1		T230	5		T487	1
values[66]	156	1			T62	1		T230	4		T487	1
values[67]	150	1			T62	1		T230	8		T487	1
values[68]	180	1			T62	1		T230	3		T487	1
values[69]	181	1			T62	1		T230	9		T487	1
values[70]	142	1			T62	1		T230	7		T487	1
values[71]	88	1			T62	2		T230	3		T487	1
values[72]	124	1			T62	1		T487	1		T421	1
values[73]	126	1			T62	1		T487	1		T421	1
values[74]	95	1			T62	1		T487	1		T421	1
values[75]	99	1			T62	1		T487	1		T421	1
values[76]	98	1			T62	1		T487	1		T421	1
values[77]	66	1			T62	1		T487	1		T421	1
values[78]	68	1			T62	1		T487	1		T421	1
values[79]	68	1			T62	1		T487	1		T421	1
values[80]	84	1			T62	1		T487	1		T421	1
values[81]	68	1			T62	1		T487	1		T421	1
values[82]	59	1			T62	1		T487	1		T421	1
values[83]	67	1			T62	1		T487	1		T421	1
values[84]	64	1			T62	1		T487	1		T421	3
values[85]	81	1			T62	1		T487	1		T421	4
values[86]	95	1			T62	1		T487	1		T421	4
values[87]	90	1			T62	1		T487	1		T421	7
values[88]	70	1			T62	1		T487	1		T421	2
values[89]	63	1			T62	1		T487	1		T421	1
values[90]	84	1			T62	1		T487	1		T421	4
values[91]	97	1			T62	1		T487	1		T421	2
values[92]	85	1			T62	1		T487	1		T421	5
values[93]	56	1			T62	1		T487	1		T421	1
values[94]	67	1			T62	1		T487	1		T421	2
values[95]	77	1			T62	1		T487	1		T421	6
values[96]	70	1			T62	1		T487	1		T421	2
values[97]	82	1			T62	1		T487	1		T421	3
values[98]	68	1			T62	1		T487	1		T421	1
values[99]	79	1			T62	1		T487	1		T421	3
values[100]	83	1			T62	1		T487	1		T421	2
values[101]	81	1			T62	1		T487	1		T421	2
values[102]	76	1			T62	1		T487	1		T421	3
values[103]	74	1			T62	1		T487	1		T421	1
values[104]	64	1			T62	1		T487	1		T421	4
values[105]	73	1			T62	1		T487	1		T421	5
values[106]	69	1			T62	1		T487	1		T421	6
values[107]	75	1			T62	1		T487	1		T421	2
values[108]	66	1			T62	1		T487	1		T421	1
values[109]	67	1			T62	1		T487	1		T421	4
values[110]	61	1			T62	1		T487	1		T421	2
values[111]	62	1			T62	1		T487	1		T421	6
values[112]	64	1			T62	1		T487	1		T421	4
values[113]	59	1			T62	1		T487	1		T421	3
values[114]	71	1			T62	1		T487	1		T421	4
values[115]	55	1			T62	1		T487	1		T421	1
values[116]	65	1			T62	1		T487	1		T421	2
values[117]	64	1			T62	1		T487	1		T421	2
values[118]	59	1			T62	1		T487	1		T421	3
values[119]	73	1			T62	1		T487	1		T421	4
values[120]	59	1			T62	1		T487	3		T421	4
values[121]	51	1			T62	1		T487	4		T421	1
values[122]	52	1			T62	1		T487	2		T421	1
values[123]	57	1			T62	2		T487	1		T421	4
values[124]	60	1			T62	6		T487	2		T421	2
values[125]	78	1			T62	1		T487	2		T421	2
values[126]	104	1			T62	1		T487	2		T421	2
values[127]	770	1			T62	44		T487	29		T421	33
values[128]	6784	1			T62	396		T487	330		T421	235