Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139710	1			T61	109		T62	1		T63	240
values[2]	10776	1			T61	4		T62	1		T63	3
values[3]	5386	1			T62	1		T487	1		T403	85
values[4]	2912	1			T62	1		T487	1		T403	27
values[5]	1860	1			T62	1		T487	1		T403	20
values[6]	1246	1			T62	1		T487	1		T403	11
values[7]	857	1			T62	1		T487	1		T403	1
values[8]	828	1			T62	1		T487	1		T406	14
values[9]	670	1			T62	1		T487	1		T404	32
values[10]	523	1			T62	1		T487	1		T404	12
values[11]	622	1			T62	1		T487	1		T404	23
values[12]	595	1			T62	1		T487	1		T404	27
values[13]	540	1			T62	1		T487	1		T404	10
values[14]	525	1			T62	1		T487	1		T404	25
values[15]	537	1			T62	1		T487	1		T404	13
values[16]	490	1			T62	1		T487	1		T404	16
values[17]	462	1			T62	1		T487	1		T404	15
values[18]	456	1			T62	1		T487	1		T404	9
values[19]	468	1			T62	1		T487	1		T404	9
values[20]	447	1			T62	1		T487	1		T404	7
values[21]	435	1			T62	1		T487	1		T404	14
values[22]	438	1			T62	1		T487	1		T404	12
values[23]	457	1			T62	1		T487	1		T404	15
values[24]	416	1			T62	1		T487	1		T404	10
values[25]	403	1			T62	1		T487	1		T404	7
values[26]	496	1			T62	1		T487	1		T404	14
values[27]	496	1			T62	1		T487	1		T404	15
values[28]	435	1			T62	1		T487	1		T404	11
values[29]	384	1			T62	1		T487	1		T404	6
values[30]	391	1			T62	1		T487	1		T404	6
values[31]	386	1			T62	1		T487	1		T404	12
values[32]	475	1			T62	1		T487	1		T404	24
values[33]	359	1			T62	1		T487	1		T404	5
values[34]	404	1			T62	1		T487	1		T404	3
values[35]	347	1			T62	1		T487	1		T404	6
values[36]	365	1			T62	1		T487	1		T404	9
values[37]	376	1			T62	1		T487	1		T404	21
values[38]	332	1			T62	1		T487	1		T404	16
values[39]	330	1			T62	1		T487	1		T404	5
values[40]	324	1			T62	1		T487	1		T823	9
values[41]	287	1			T62	1		T487	1		T823	3
values[42]	285	1			T62	2		T487	1		T823	7
values[43]	226	1			T62	1		T487	1		T823	7
values[44]	287	1			T62	1		T487	1		T823	8
values[45]	278	1			T62	1		T487	1		T823	19
values[46]	216	1			T62	1		T487	1		T823	16
values[47]	189	1			T62	1		T487	1		T823	17
values[48]	185	1			T62	1		T487	1		T823	5
values[49]	204	1			T62	1		T487	1		T823	8
values[50]	191	1			T62	1		T487	1		T823	7
values[51]	183	1			T62	1		T487	1		T823	8
values[52]	176	1			T62	1		T487	1		T823	8
values[53]	129	1			T62	1		T487	1		T823	8
values[54]	158	1			T62	1		T487	1		T823	10
values[55]	123	1			T62	1		T487	1		T823	8
values[56]	118	1			T62	1		T487	1		T823	12
values[57]	90	1			T62	1		T487	1		T823	7
values[58]	79	1			T62	1		T487	1		T805	1
values[59]	75	1			T62	1		T487	1		T805	1
values[60]	65	1			T62	1		T487	1		T805	1
values[61]	51	1			T62	2		T487	1		T805	1
values[62]	67	1			T62	1		T487	1		T805	1
values[63]	66	1			T62	1		T487	1		T805	1
values[64]	78	1			T62	1		T487	1		T805	1
values[65]	74	1			T62	1		T487	1		T805	1
values[66]	84	1			T62	1		T487	1		T805	1
values[67]	54	1			T62	1		T487	1		T805	1
values[68]	84	1			T62	1		T487	1		T805	1
values[69]	110	1			T62	1		T487	1		T805	1
values[70]	100	1			T62	1		T487	1		T805	1
values[71]	79	1			T62	1		T487	1		T805	1
values[72]	52	1			T62	1		T487	1		T805	1
values[73]	63	1			T62	1		T487	1		T805	1
values[74]	68	1			T62	1		T487	1		T805	1
values[75]	60	1			T62	1		T487	1		T805	1
values[76]	50	1			T62	1		T487	1		T805	1
values[77]	49	1			T62	1		T487	1		T805	1
values[78]	62	1			T62	1		T487	1		T805	1
values[79]	77	1			T62	1		T487	1		T805	1
values[80]	67	1			T62	1		T487	1		T805	1
values[81]	72	1			T62	1		T487	1		T805	1
values[82]	62	1			T62	1		T487	1		T805	1
values[83]	71	1			T62	1		T487	1		T805	1
values[84]	82	1			T62	1		T487	1		T805	1
values[85]	86	1			T62	1		T487	1		T805	1
values[86]	73	1			T62	1		T487	1		T805	1
values[87]	80	1			T62	1		T487	1		T805	1
values[88]	67	1			T62	1		T487	1		T805	1
values[89]	77	1			T62	1		T487	1		T805	1
values[90]	66	1			T62	1		T487	1		T805	1
values[91]	69	1			T62	4		T487	1		T805	1
values[92]	61	1			T62	3		T487	1		T805	1
values[93]	46	1			T62	2		T487	1		T805	1
values[94]	69	1			T62	5		T487	1		T805	1
values[95]	51	1			T62	2		T487	2		T805	1
values[96]	46	1			T62	1		T487	1		T805	1
values[97]	46	1			T62	6		T487	1		T805	1
values[98]	55	1			T62	3		T487	1		T805	1
values[99]	73	1			T62	3		T487	1		T805	1
values[100]	62	1			T62	2		T487	1		T805	1
values[101]	57	1			T62	2		T487	1		T805	1
values[102]	45	1			T62	2		T487	1		T805	1
values[103]	61	1			T62	2		T487	1		T805	1
values[104]	44	1			T62	5		T487	1		T805	1
values[105]	52	1			T62	1		T487	1		T805	1
values[106]	65	1			T62	2		T487	1		T805	1
values[107]	65	1			T62	2		T487	1		T805	1
values[108]	58	1			T62	2		T487	1		T805	1
values[109]	52	1			T62	4		T487	1		T805	1
values[110]	50	1			T62	1		T487	1		T805	2
values[111]	54	1			T62	2		T487	1		T805	1
values[112]	46	1			T62	5		T487	1		T805	1
values[113]	44	1			T62	1		T487	1		T805	1
values[114]	50	1			T62	1		T487	2		T805	1
values[115]	55	1			T62	3		T487	2		T805	1
values[116]	58	1			T62	4		T487	1		T805	1
values[117]	42	1			T62	1		T487	2		T805	1
values[118]	42	1			T62	3		T487	3		T805	1
values[119]	44	1			T62	1		T487	4		T805	2
values[120]	47	1			T62	1		T487	5		T805	1
values[121]	39	1			T62	2		T487	1		T805	1
values[122]	47	1			T62	4		T487	1		T805	1
values[123]	40	1			T62	2		T487	1		T805	1
values[124]	52	1			T62	4		T487	1		T805	1
values[125]	50	1			T62	3		T487	1		T805	1
values[126]	105	1			T62	4		T487	4		T805	2
values[127]	1526	1			T62	55		T487	63		T805	65
values[128]	7162	1			T62	278		T487	302		T805	323