Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	514	1			T230	3		T489	1		T403	4
all_values[1]	481	1			T230	5		T489	1		T403	2
all_values[2]	503	1			T230	5		T489	3		T406	2
all_values[3]	517	1			T230	4		T489	1		T406	1
all_values[4]	461	1			T62	1		T230	4		T489	1
all_values[5]	522	1			T62	1		T230	4		T489	1
all_values[6]	518	1			T62	1		T230	4		T487	1
all_values[7]	454	1			T63	1		T230	5		T489	1
all_values[8]	479	1			T230	6		T489	1		T403	1
all_values[9]	521	1			T230	9		T489	1		T432	1
all_values[10]	496	1			T230	3		T489	2		T403	3
all_values[11]	504	1			T230	1		T489	2		T403	2
all_values[12]	497	1			T230	1		T489	1		T403	1
all_values[13]	494	1			T230	2		T403	2		T406	2
all_values[14]	495	1			T230	2		T727	1		T489	5
all_values[15]	473	1			T230	1		T489	2		T403	1
all_values[16]	489	1			T230	4		T489	1		T406	1
all_values[17]	476	1			T230	7		T727	1		T406	2
all_values[18]	467	1			T63	1		T230	4		T489	1
all_values[19]	514	1			T230	2		T489	2		T403	1
all_values[20]	452	1			T230	1		T489	3		T403	1
all_values[21]	519	1			T230	4		T406	1		T432	1
all_values[22]	503	1			T62	1		T230	4		T487	1
all_values[23]	488	1			T230	8		T489	1		T432	1
all_values[24]	496	1			T230	4		T406	4		T416	3
all_values[25]	483	1			T62	1		T63	1		T230	2
all_values[26]	488	1			T230	3		T727	1		T406	3
all_values[27]	486	1			T230	1		T403	1		T406	4
all_values[28]	504	1			T230	3		T489	2		T403	1
all_values[29]	474	1			T62	1		T230	8		T727	1
all_values[30]	514	1			T230	6		T489	1		T406	1
all_values[31]	489	1			T230	6		T487	1		T406	2
all_values[32]	493	1			T62	1		T230	8		T403	1
all_values[33]	514	1			T62	1		T230	4		T487	1
all_values[34]	473	1			T230	6		T432	1		T416	2
all_values[35]	491	1			T62	1		T230	7		T489	1
all_values[36]	443	1			T230	1		T489	2		T403	1
all_values[37]	488	1			T62	1		T230	4		T487	1
all_values[38]	505	1			T230	2		T403	3		T406	1
all_values[39]	509	1			T62	1		T230	2		T489	1
all_values[40]	492	1			T230	7		T403	1		T406	1
all_values[41]	468	1			T230	5		T403	1		T406	1
all_values[42]	482	1			T63	1		T230	5		T403	2
all_values[43]	473	1			T230	4		T489	4		T403	2
all_values[44]	482	1			T230	4		T727	2		T403	1
all_values[45]	480	1			T230	3		T487	1		T489	1
all_values[46]	480	1			T62	1		T63	1		T230	3
all_values[47]	486	1			T230	6		T403	1		T406	1
all_values[48]	507	1			T230	5		T489	2		T403	1
all_values[49]	468	1			T62	1		T63	1		T230	6