Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3653	1			T63	1		T67	6		T230	22
all_values[1]	3477	1			T63	2		T67	3		T230	22
all_values[2]	3442	1			T63	1		T67	6		T230	25
all_values[3]	3511	1			T63	2		T67	4		T230	25
all_values[4]	3572	1			T63	4		T67	3		T230	22
all_values[5]	3442	1			T63	1		T67	1		T230	22
all_values[6]	3390	1			T63	4		T67	4		T230	19
all_values[7]	3479	1			T63	1		T67	3		T230	27
all_values[8]	3563	1			T63	4		T67	1		T230	31
all_values[9]	3466	1			T63	2		T67	6		T230	26
all_values[10]	3578	1			T63	5		T230	23		T405	1
all_values[11]	3575	1			T63	3		T67	2		T230	24
all_values[12]	3576	1			T63	6		T67	3		T230	22
all_values[13]	3550	1			T63	5		T67	2		T230	22
all_values[14]	3524	1			T63	4		T230	31		T405	2
all_values[15]	3395	1			T63	3		T67	1		T230	28
all_values[16]	3455	1			T63	2		T67	2		T230	25
all_values[17]	3542	1			T63	2		T67	4		T230	28
all_values[18]	3614	1			T67	3		T230	29		T405	1
all_values[19]	3573	1			T63	3		T67	3		T230	28
all_values[20]	3501	1			T63	1		T67	6		T230	22
all_values[21]	3473	1			T63	4		T67	3		T230	24
all_values[22]	3534	1			T67	1		T230	31		T405	1
all_values[23]	3563	1			T63	3		T67	3		T230	32
all_values[24]	3540	1			T67	1		T230	27		T405	1
all_values[25]	3499	1			T63	4		T67	3		T230	18
all_values[26]	3553	1			T67	4		T230	21		T489	3
all_values[27]	3476	1			T63	5		T67	3		T230	24
all_values[28]	3622	1			T63	4		T230	22		T489	1
all_values[29]	3414	1			T63	2		T67	1		T230	27
all_values[30]	3566	1			T63	2		T67	1		T230	25
all_values[31]	3475	1			T63	6		T67	2		T230	24
all_values[32]	3468	1			T63	3		T67	1		T230	24
all_values[33]	3579	1			T63	4		T67	3		T230	36
all_values[34]	3566	1			T63	5		T67	3		T230	31
all_values[35]	3497	1			T63	3		T67	4		T230	23
all_values[36]	3472	1			T63	5		T67	2		T230	31
all_values[37]	3514	1			T63	1		T67	3		T230	26
all_values[38]	3536	1			T63	5		T67	3		T230	28
all_values[39]	3435	1			T63	5		T67	2		T230	19
all_values[40]	3640	1			T63	1		T67	1		T230	27
all_values[41]	3471	1			T63	2		T67	2		T230	30
all_values[42]	3438	1			T63	4		T67	5		T230	22
all_values[43]	3467	1			T63	4		T67	2		T230	25
all_values[44]	3554	1			T63	3		T67	2		T230	21
all_values[45]	3592	1			T63	2		T67	2		T230	26
all_values[46]	3569	1			T63	3		T67	1		T230	27
all_values[47]	3547	1			T63	2		T67	5		T230	26
all_values[48]	3518	1			T63	1		T67	2		T230	26
all_values[49]	3549	1			T63	2		T67	4		T230	29
all_values[50]	3537	1			T63	2		T230	18		T405	2
all_values[51]	3526	1			T67	1		T230	28		T405	1
all_values[52]	3459	1			T63	4		T67	5		T230	23
all_values[53]	3607	1			T63	2		T67	1		T230	37
all_values[54]	3593	1			T63	3		T67	1		T230	30
all_values[55]	3511	1			T63	2		T67	3		T230	32
all_values[56]	3464	1			T63	4		T67	2		T230	20
all_values[57]	3543	1			T63	1		T67	2		T230	29
all_values[58]	3503	1			T63	2		T67	2		T230	30
all_values[59]	3522	1			T63	4		T67	8		T230	16
all_values[60]	3480	1			T63	1		T230	26		T405	3
all_values[61]	3528	1			T67	3		T230	27		T489	5
all_values[62]	3504	1			T63	2		T67	2		T230	24
all_values[63]	3567	1			T63	4		T67	1		T230	30