Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	140509	1			T54	8		T55	27		T56	1
values[2]	9873	1			T103	2		T507	1		T414	1
values[3]	3592	1			T504	38		T505	1		T430	8
values[4]	2254	1			T504	28		T782	1		T407	12
values[5]	1513	1			T504	21		T782	2		T407	23
values[6]	1074	1			T504	14		T782	2		T407	7
values[7]	752	1			T504	15		T782	1		T407	7
values[8]	588	1			T504	12		T782	3		T407	5
values[9]	426	1			T504	4		T782	1		T407	11
values[10]	334	1			T504	1		T782	1		T407	11
values[11]	336	1			T782	2		T407	10		T432	1
values[12]	270	1			T782	2		T407	7		T432	1
values[13]	277	1			T782	2		T407	5		T432	1
values[14]	256	1			T782	3		T407	7		T432	1
values[15]	271	1			T782	1		T407	4		T432	1
values[16]	318	1			T782	1		T407	14		T432	1
values[17]	221	1			T782	3		T407	6		T432	1
values[18]	214	1			T782	3		T407	6		T432	1
values[19]	213	1			T782	4		T407	11		T432	1
values[20]	246	1			T782	8		T407	13		T432	1
values[21]	233	1			T782	3		T407	4		T432	1
values[22]	204	1			T782	1		T407	3		T432	1
values[23]	224	1			T782	3		T407	7		T432	1
values[24]	229	1			T782	11		T407	7		T432	1
values[25]	270	1			T782	13		T407	23		T432	1
values[26]	242	1			T782	9		T407	7		T432	1
values[27]	196	1			T782	5		T407	4		T432	1
values[28]	220	1			T782	3		T407	6		T432	1
values[29]	231	1			T782	5		T407	14		T432	1
values[30]	209	1			T782	2		T407	8		T432	1
values[31]	230	1			T782	2		T407	7		T432	1
values[32]	192	1			T782	1		T407	6		T432	1
values[33]	212	1			T782	4		T407	2		T432	1
values[34]	173	1			T782	1		T407	3		T432	1
values[35]	214	1			T782	3		T407	3		T432	1
values[36]	266	1			T782	1		T407	9		T432	1
values[37]	213	1			T782	1		T407	11		T432	1
values[38]	182	1			T782	3		T407	7		T432	1
values[39]	209	1			T782	2		T407	3		T432	1
values[40]	244	1			T782	2		T407	5		T432	2
values[41]	226	1			T782	3		T407	9		T432	1
values[42]	247	1			T782	7		T407	4		T432	1
values[43]	220	1			T782	4		T407	4		T432	1
values[44]	199	1			T782	3		T407	5		T432	1
values[45]	216	1			T782	2		T407	6		T432	1
values[46]	190	1			T782	2		T407	4		T432	1
values[47]	198	1			T782	5		T407	19		T432	1
values[48]	233	1			T782	6		T407	19		T432	1
values[49]	185	1			T782	3		T407	5		T432	1
values[50]	201	1			T782	1		T407	17		T432	2
values[51]	208	1			T782	3		T407	3		T432	1
values[52]	202	1			T782	1		T407	3		T432	1
values[53]	214	1			T782	3		T407	6		T432	1
values[54]	183	1			T782	1		T407	4		T432	1
values[55]	185	1			T782	3		T407	8		T432	1
values[56]	147	1			T782	3		T407	6		T432	1
values[57]	160	1			T782	1		T407	5		T432	1
values[58]	170	1			T782	4		T407	7		T432	1
values[59]	191	1			T782	3		T407	5		T432	1
values[60]	156	1			T782	1		T407	3		T432	1
values[61]	133	1			T782	2		T407	10		T432	1
values[62]	145	1			T782	2		T407	11		T432	1
values[63]	194	1			T782	2		T407	16		T432	1
values[64]	175	1			T782	1		T407	9		T432	1
values[65]	171	1			T782	9		T407	14		T432	1
values[66]	171	1			T782	12		T407	3		T432	1
values[67]	159	1			T782	16		T407	11		T432	1
values[68]	171	1			T782	24		T407	4		T432	1
values[69]	138	1			T782	11		T407	2		T432	1
values[70]	173	1			T782	17		T407	18		T432	1
values[71]	133	1			T782	21		T407	10		T432	1
values[72]	140	1			T782	7		T432	1		T433	1
values[73]	148	1			T782	3		T432	1		T433	1
values[74]	128	1			T782	2		T432	1		T433	1
values[75]	114	1			T782	6		T432	1		T433	1
values[76]	88	1			T782	10		T432	1		T433	1
values[77]	108	1			T782	7		T432	1		T433	1
values[78]	83	1			T782	7		T432	1		T433	1
values[79]	67	1			T782	4		T432	1		T433	1
values[80]	89	1			T782	7		T432	1		T433	1
values[81]	105	1			T782	5		T432	1		T433	1
values[82]	91	1			T782	4		T432	1		T433	1
values[83]	89	1			T782	2		T432	1		T433	1
values[84]	71	1			T782	3		T432	1		T433	1
values[85]	72	1			T782	4		T432	1		T433	1
values[86]	92	1			T782	8		T432	1		T433	1
values[87]	89	1			T782	7		T432	1		T433	1
values[88]	74	1			T782	10		T432	1		T433	1
values[89]	97	1			T782	5		T432	1		T433	1
values[90]	75	1			T782	1		T432	1		T433	1
values[91]	87	1			T432	1		T433	1		T801	1
values[92]	90	1			T432	1		T433	1		T801	1
values[93]	73	1			T432	1		T433	1		T801	1
values[94]	77	1			T432	1		T433	1		T801	1
values[95]	88	1			T432	1		T433	1		T801	1
values[96]	92	1			T432	1		T433	1		T801	1
values[97]	98	1			T432	1		T433	1		T801	1
values[98]	87	1			T432	1		T433	1		T801	1
values[99]	100	1			T432	1		T433	1		T801	1
values[100]	89	1			T432	1		T433	1		T801	1
values[101]	79	1			T432	1		T433	1		T801	2
values[102]	73	1			T432	1		T433	1		T801	1
values[103]	74	1			T432	3		T433	1		T801	2
values[104]	73	1			T432	3		T433	1		T801	1
values[105]	75	1			T432	1		T433	1		T801	1
values[106]	90	1			T432	1		T433	1		T801	1
values[107]	85	1			T432	1		T433	1		T801	1
values[108]	90	1			T432	5		T433	1		T801	1
values[109]	71	1			T432	2		T433	1		T801	1
values[110]	69	1			T432	2		T433	1		T801	1
values[111]	57	1			T432	2		T433	1		T801	1
values[112]	70	1			T432	1		T433	1		T801	1
values[113]	80	1			T432	2		T433	1		T801	1
values[114]	94	1			T432	3		T433	1		T801	1
values[115]	89	1			T432	4		T433	1		T801	1
values[116]	82	1			T432	2		T433	1		T801	1
values[117]	84	1			T432	3		T433	1		T801	1
values[118]	77	1			T432	1		T433	1		T801	1
values[119]	77	1			T432	2		T433	1		T801	1
values[120]	75	1			T432	1		T433	1		T801	1
values[121]	76	1			T432	1		T433	5		T801	1
values[122]	94	1			T432	4		T433	3		T801	2
values[123]	76	1			T432	1		T433	1		T801	3
values[124]	61	1			T432	2		T433	4		T801	1
values[125]	93	1			T432	1		T433	1		T801	5
values[126]	181	1			T432	1		T433	3		T801	6
values[127]	777	1			T432	29		T433	23		T801	36
values[128]	5505	1			T432	336		T433	337		T801	265