Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.37	95.32	93.65	91.81		94.46	97.38	99.58

Total tests in report: 2801

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.62	40.62	44.57	44.57	42.79	42.79	32.47	32.47			57.43	57.43	66.30	66.30	0.14	0.14	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2873554504
50.23	9.61	50.18	5.61	57.25	14.46	33.43	0.96			68.65	11.22	90.74	24.44	1.14	1.00	/workspace/coverage/cover_reg_top/9.chip_csr_rw.143097028
56.96	6.73	62.24	12.06	60.19	2.94	40.56	7.13			68.99	0.34	90.74	0.00	19.07	17.93	/workspace/coverage/cover_reg_top/75.xbar_stress_all.3500981224
62.68	5.72	74.46	12.23	68.48	8.29	43.11	2.55			80.22	11.23	90.74	0.00	19.07	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3894903522
67.09	4.41	74.46	0.00	68.80	0.33	43.11	0.00			80.34	0.11	90.74	0.00	45.09	26.03	/workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1824903246
69.80	2.71	80.46	6.00	73.05	4.25	47.06	3.94			82.40	2.06	90.74	0.00	45.09	0.00	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1397637387
72.29	2.49	80.46	0.00	73.05	0.00	47.06	0.00			82.40	0.00	90.74	0.00	60.00	14.91	/workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3523587267
74.70	2.41	82.02	1.56	75.80	2.75	52.54	5.48			84.25	1.86	91.11	0.37	62.45	2.44	/workspace/coverage/default/2.chip_sw_alert_test.2149314313
76.95	2.26	82.02	0.00	75.80	0.00	66.08	13.54			84.25	0.00	91.11	0.00	62.45	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2666937944
78.65	1.70	82.02	0.00	75.92	0.12	66.08	0.00			84.25	0.00	91.11	0.00	72.54	10.09	/workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3115811540
79.95	1.29	83.46	1.44	76.87	0.95	69.77	3.69			85.54	1.28	91.48	0.37	72.55	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.862476878
81.11	1.16	83.46	0.00	76.87	0.00	69.77	0.00			85.54	0.00	91.48	0.00	79.53	6.98	/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3795641848
82.27	1.16	85.03	1.57	79.58	2.71	69.97	0.20			88.03	2.49	91.48	0.00	79.53	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.483849848
83.20	0.93	85.03	0.00	80.01	0.42	69.97	0.00			88.14	0.11	91.48	0.00	84.55	5.02	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.1559252318
84.11	0.91	86.42	1.40	80.83	0.82	72.51	2.54			88.69	0.55	91.67	0.19	84.55	0.00	/workspace/coverage/default/2.rom_e2e_smoke.3856444739
84.98	0.87	87.17	0.74	81.00	0.17	72.52	0.01			88.90	0.20	95.74	4.07	84.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3744796210
85.72	0.74	88.58	1.41	82.04	1.04	73.62	1.10			89.60	0.70	95.93	0.19	84.55	0.00	/workspace/coverage/default/1.chip_sw_gpio.259875779
86.44	0.72	89.79	1.21	83.03	0.99	74.59	0.97			90.78	1.18	95.93	0.00	84.55	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2217770736
87.16	0.72	89.82	0.03	83.03	0.00	78.88	4.29			90.78	0.00	95.93	0.00	84.55	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1955773589
87.84	0.68	89.82	0.00	83.34	0.31	78.88	0.00			90.79	0.02	95.93	0.00	88.30	3.75	/workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2977847365
88.41	0.57	89.82	0.01	83.64	0.30	79.60	0.72			90.83	0.03	95.93	0.00	90.65	2.35	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2573805765
88.97	0.55	89.82	0.00	83.76	0.11	79.60	0.00			90.84	0.02	95.93	0.00	93.84	3.20	/workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.3995729415
89.50	0.54	90.75	0.92	84.65	0.90	80.29	0.69			91.56	0.72	95.93	0.00	93.84	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1624316524
90.02	0.52	90.76	0.01	87.34	2.68	80.29	0.00			91.56	0.00	95.93	0.00	94.25	0.41	/workspace/coverage/cover_reg_top/26.chip_tl_errors.1357107413
90.48	0.46	91.52	0.76	88.88	1.55	80.36	0.07			91.94	0.38	95.93	0.00	94.27	0.01	/workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.2434868277
90.83	0.35	91.54	0.02	88.88	0.00	82.43	2.07			91.94	0.00	95.93	0.00	94.27	0.00	/workspace/coverage/default/0.chip_sw_otbn_randomness.1573110144
91.13	0.30	92.50	0.95	89.07	0.19	83.01	0.58			92.03	0.09	95.93	0.00	94.27	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3882793752
91.43	0.30	92.50	0.00	89.10	0.03	84.56	1.55			92.04	0.02	96.11	0.19	94.28	0.01	/workspace/coverage/default/1.chip_sw_flash_init.2792154745
91.73	0.30	92.50	0.00	89.14	0.04	84.56	0.00			92.04	0.00	96.11	0.00	96.03	1.75	/workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.4051604158
92.01	0.28	92.53	0.04	89.16	0.01	86.17	1.61			92.05	0.01	96.11	0.00	96.03	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3624618845
92.29	0.28	93.01	0.47	89.61	0.46	86.43	0.26			92.52	0.47	96.11	0.00	96.03	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3459474082
92.50	0.22	93.09	0.08	89.69	0.08	87.42	0.99			92.69	0.17	96.11	0.00	96.03	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1637093159
92.68	0.17	93.16	0.08	90.12	0.43	87.48	0.06			93.17	0.48	96.11	0.00	96.03	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1426819794
92.85	0.17	93.16	0.00	90.20	0.08	87.48	0.00			93.17	0.00	96.11	0.00	96.97	0.94	/workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2277932941
92.98	0.13	93.39	0.23	90.39	0.19	87.50	0.02			93.49	0.32	96.11	0.00	96.97	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3222374171
93.09	0.12	93.39	0.00	90.39	0.00	88.17	0.66			93.49	0.00	96.11	0.00	97.00	0.04	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3706769731
93.21	0.12	93.42	0.03	90.49	0.09	88.50	0.33			93.55	0.06	96.30	0.19	97.00	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.610196086
93.32	0.11	93.42	0.00	90.53	0.04	88.50	0.00			93.57	0.02	96.30	0.00	97.61	0.61	/workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3687602362
93.43	0.11	93.69	0.27	90.65	0.12	88.50	0.01			93.64	0.07	96.48	0.19	97.63	0.01	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.4269958974
93.54	0.11	93.71	0.02	90.94	0.29	88.51	0.01			93.97	0.33	96.48	0.00	97.63	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1310959582
93.64	0.10	93.71	0.00	90.94	0.00	89.14	0.63			93.97	0.00	96.48	0.00	97.63	0.00	/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2844099961
93.74	0.09	93.71	0.00	91.10	0.16	89.14	0.00			93.97	0.00	96.48	0.00	98.03	0.40	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1246313642
93.83	0.09	93.79	0.08	91.49	0.39	89.18	0.04			94.00	0.03	96.48	0.00	98.03	0.00	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.3308590082
93.90	0.08	93.94	0.15	91.61	0.11	89.26	0.07			94.12	0.12	96.48	0.00	98.03	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.259435498
93.97	0.07	94.12	0.18	91.76	0.15	89.26	0.00			94.21	0.09	96.48	0.00	98.03	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3281288538
94.03	0.06	94.12	0.00	92.11	0.35	89.26	0.00			94.21	0.00	96.48	0.00	98.04	0.01	/workspace/coverage/cover_reg_top/21.chip_tl_errors.3669994334
94.09	0.06	94.12	0.00	92.11	0.00	89.59	0.33			94.21	0.00	96.48	0.00	98.04	0.00	/workspace/coverage/default/0.chip_sw_edn_sw_mode.638246850
94.15	0.06	94.24	0.13	92.11	0.01	89.77	0.18			94.23	0.02	96.48	0.00	98.04	0.00	/workspace/coverage/default/2.chip_tap_straps_testunlock0.1248950651
94.20	0.05	94.26	0.02	92.12	0.01	90.04	0.27			94.24	0.01	96.48	0.00	98.04	0.00	/workspace/coverage/default/0.chip_sw_power_sleep_load.576205499
94.24	0.04	94.27	0.01	92.13	0.01	90.29	0.25			94.24	0.00	96.48	0.00	98.04	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.649217039
94.29	0.04	94.27	0.00	92.13	0.01	90.29	0.00			94.24	0.00	96.48	0.00	98.30	0.26	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.3776814128
94.33	0.04	94.30	0.03	92.14	0.01	90.30	0.01			94.25	0.02	96.67	0.19	98.31	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.3861259435
94.37	0.04	94.32	0.01	92.15	0.01	90.30	0.00			94.28	0.02	96.85	0.19	98.32	0.01	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.4161839504
94.41	0.04	94.32	0.01	92.16	0.01	90.30	0.01			94.29	0.01	97.04	0.19	98.33	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3685444957
94.44	0.04	94.32	0.01	92.17	0.01	90.31	0.01			94.29	0.01	97.22	0.19	98.34	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.3017383363
94.48	0.04	94.32	0.00	92.17	0.00	90.34	0.03			94.29	0.00	97.41	0.19	98.34	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3015090979
94.51	0.03	94.32	0.00	92.17	0.00	90.55	0.20			94.29	0.00	97.41	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3561387677
94.55	0.03	94.37	0.05	92.23	0.06	90.61	0.06			94.32	0.02	97.41	0.00	98.34	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1859129772
94.58	0.03	94.37	0.00	92.23	0.00	90.79	0.19			94.32	0.00	97.41	0.00	98.34	0.00	/workspace/coverage/default/2.chip_sw_flash_init.98729220
94.61	0.03	94.37	0.00	92.23	0.00	90.96	0.16			94.32	0.00	97.41	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_kmac_entropy.3886035478
94.63	0.03	94.37	0.00	92.39	0.16	90.96	0.00			94.32	0.00	97.41	0.00	98.34	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1349282527
94.66	0.02	94.37	0.00	92.45	0.06	90.96	0.00			94.32	0.00	97.41	0.00	98.43	0.08	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3235614084
94.68	0.02	94.45	0.08	92.50	0.05	90.96	0.00			94.33	0.02	97.41	0.00	98.43	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.51842972
94.70	0.02	94.46	0.01	92.53	0.03	91.05	0.09			94.34	0.01	97.41	0.00	98.43	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.349399659
94.72	0.02	94.53	0.07	92.58	0.05	91.05	0.00			94.36	0.02	97.41	0.00	98.43	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1649430142
94.74	0.02	94.56	0.03	92.63	0.05	91.06	0.01			94.38	0.02	97.41	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3219374004
94.76	0.02	94.59	0.03	92.67	0.04	91.08	0.02			94.40	0.02	97.41	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.252436163
94.78	0.02	94.61	0.02	92.68	0.01	91.15	0.07			94.42	0.02	97.41	0.00	98.43	0.00	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3353211170
94.80	0.02	94.61	0.00	92.69	0.01	91.15	0.00			94.42	0.00	97.41	0.00	98.52	0.09	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.620620641
94.82	0.02	94.64	0.03	92.73	0.04	91.17	0.03			94.42	0.01	97.41	0.00	98.52	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.72616821
94.83	0.02	94.65	0.01	92.73	0.01	91.26	0.09			94.42	0.00	97.41	0.00	98.52	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2559296032
94.85	0.02	94.65	0.00	92.83	0.09	91.26	0.00			94.42	0.00	97.41	0.00	98.52	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.3817475537
94.86	0.01	94.65	0.00	92.90	0.08	91.27	0.01			94.42	0.00	97.41	0.00	98.52	0.00	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3089078995
94.87	0.01	94.65	0.00	92.90	0.00	91.35	0.08			94.42	0.00	97.41	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_flash_init.2464338865
94.89	0.01	94.65	0.00	92.91	0.01	91.35	0.00			94.42	0.00	97.41	0.00	98.58	0.06	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.999913731
94.90	0.01	94.65	0.01	92.92	0.01	91.40	0.05			94.42	0.00	97.41	0.00	98.58	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.781737101
94.91	0.01	94.65	0.00	92.99	0.06	91.40	0.00			94.42	0.00	97.41	0.00	98.58	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.107586058
94.92	0.01	94.65	0.00	93.05	0.06	91.40	0.00			94.42	0.00	97.41	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/19.xbar_stress_all.24955066
94.93	0.01	94.65	0.00	93.11	0.06	91.40	0.00			94.42	0.00	97.41	0.00	98.58	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1407665699
94.94	0.01	94.65	0.00	93.11	0.00	91.46	0.06			94.42	0.00	97.41	0.00	98.58	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3675392687
94.95	0.01	94.65	0.00	93.16	0.05	91.46	0.00			94.42	0.00	97.41	0.00	98.58	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3358628330
94.96	0.01	94.65	0.00	93.16	0.01	91.46	0.00			94.42	0.00	97.41	0.00	98.63	0.05	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2327124587
94.96	0.01	94.68	0.02	93.17	0.01	91.46	0.01			94.44	0.02	97.41	0.00	98.63	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1776492218
94.97	0.01	94.68	0.01	93.20	0.03	91.47	0.01			94.44	0.00	97.41	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2136503062
94.98	0.01	94.68	0.00	93.21	0.01	91.47	0.00			94.44	0.00	97.41	0.00	98.66	0.04	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.737205451
94.99	0.01	94.69	0.01	93.22	0.01	91.50	0.03			94.44	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1629697674
94.99	0.01	94.69	0.00	93.22	0.01	91.54	0.03			94.44	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.150682223
95.00	0.01	94.69	0.00	93.22	0.00	91.57	0.03			94.44	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3102156468
95.00	0.01	94.69	0.00	93.25	0.03	91.57	0.00			94.44	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.3338501214
95.01	0.01	94.69	0.00	93.25	0.00	91.60	0.03			94.44	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.344315371
95.01	0.01	94.69	0.00	93.25	0.00	91.63	0.03			94.44	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2349711045
95.02	0.01	94.69	0.00	93.28	0.03	91.63	0.00			94.44	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/4.xbar_stress_all.2476277547
95.02	0.01	94.69	0.00	93.31	0.03	91.63	0.00			94.44	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1531762695
95.03	0.01	94.69	0.00	93.34	0.03	91.63	0.00			94.44	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.2977574961
95.03	0.01	94.69	0.00	93.37	0.03	91.63	0.00			94.44	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.3005768110
95.04	0.01	94.69	0.00	93.38	0.01	91.63	0.00			94.44	0.00	97.41	0.00	98.67	0.01	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1487780095
95.04	0.01	94.69	0.00	93.38	0.00	91.64	0.01			94.44	0.00	97.41	0.00	98.68	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.120483457
95.04	0.01	94.69	0.00	93.38	0.00	91.67	0.03			94.44	0.00	97.41	0.00	98.68	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1878644903
95.05	0.01	94.69	0.00	93.38	0.00	91.67	0.00			94.44	0.00	97.41	0.00	98.71	0.02	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.158295853
95.05	0.01	94.69	0.00	93.38	0.00	91.67	0.00			94.44	0.00	97.41	0.00	98.73	0.02	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1904741298
95.06	0.01	94.69	0.00	93.38	0.00	91.67	0.00			94.44	0.00	97.41	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3665775719
95.06	0.01	94.69	0.00	93.38	0.00	91.69	0.02			94.44	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_jtag_mem_access.3584959203
95.06	0.01	94.69	0.00	93.40	0.02	91.69	0.00			94.44	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/cover_reg_top/95.xbar_stress_all.3546558256
95.07	0.01	94.69	0.00	93.42	0.02	91.69	0.00			94.44	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1126471566
95.07	0.01	94.69	0.00	93.44	0.02	91.69	0.00			94.44	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/2.chip_sw_gpio.895639054
95.07	0.01	94.69	0.00	93.44	0.00	91.71	0.02			94.44	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2495927119
95.08	0.01	94.70	0.01	93.44	0.00	91.72	0.01			94.44	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3278216887
95.08	0.01	94.70	0.00	93.44	0.00	91.73	0.02			94.44	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.639193393
95.08	0.01	94.71	0.01	93.44	0.00	91.74	0.01			94.44	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2172444230
95.08	0.01	94.71	0.00	93.45	0.01	91.74	0.00			94.44	0.00	97.41	0.00	98.77	0.01	/workspace/coverage/cover_reg_top/13.xbar_stress_all.2534032990
95.09	0.01	94.71	0.00	93.46	0.01	91.74	0.00			94.44	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.400267195
95.09	0.01	94.71	0.00	93.48	0.01	91.74	0.00			94.44	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.274720297
95.09	0.01	94.71	0.00	93.49	0.01	91.74	0.00			94.44	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.744864917
95.09	0.01	94.72	0.01	93.50	0.01	91.74	0.00			94.44	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/2.chip_sw_pattgen_ios.2173078853
95.10	0.01	94.72	0.00	93.51	0.01	91.74	0.01			94.44	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1240087721
95.10	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.78	0.01	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3244636025
95.10	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.79	0.01	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1887971448
95.10	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.80	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1286162563
95.10	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.81	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.3576883230
95.11	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.83	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2113966134
95.11	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.84	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.47863125
95.11	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.85	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2245390006
95.11	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.86	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3074748928
95.11	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.87	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.2513965380
95.12	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.88	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.219378043
95.12	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.90	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.686978525
95.12	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.91	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1200487823
95.12	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.92	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2639546369
95.12	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.93	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3243096540
95.13	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.94	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.640127031
95.13	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.95	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2193125086
95.13	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.97	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.643600518
95.13	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.98	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.3652336931
95.13	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	98.99	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2104958772
95.14	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.00	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.4032250612
95.14	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.01	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.720614246
95.14	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.02	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2317279962
95.14	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.04	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.4245349686
95.14	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.05	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.749805605
95.15	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.06	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.3165736955
95.15	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.07	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2219590571
95.15	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.08	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1811897850
95.15	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.10	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.762506747
95.15	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.11	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3065453946
95.16	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.12	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.142697273
95.16	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.13	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3016091343
95.16	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.14	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3264778844
95.16	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.15	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.799567800
95.16	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.17	0.01	/workspace/coverage/default/33.chip_sw_all_escalation_resets.3748596610
95.16	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.18	0.01	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2478845709
95.17	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.19	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.4254126550
95.17	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.20	0.01	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.131105338
95.17	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.21	0.01	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2048511566
95.17	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.22	0.01	/workspace/coverage/default/4.chip_sw_all_escalation_resets.743227342
95.17	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.24	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1543005885
95.18	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.25	0.01	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2043788141
95.18	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.26	0.01	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3121923348
95.18	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.27	0.01	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.799422278
95.18	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.28	0.01	/workspace/coverage/default/45.chip_sw_all_escalation_resets.4044839943
95.18	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.30	0.01	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3228772512
95.19	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.31	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.1674114023
95.19	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.32	0.01	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.965878095
95.19	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.33	0.01	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.360877601
95.19	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.34	0.01	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3216744129
95.19	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.35	0.01	/workspace/coverage/default/54.chip_sw_all_escalation_resets.2747442509
95.20	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.37	0.01	/workspace/coverage/default/55.chip_sw_all_escalation_resets.70506814
95.20	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.38	0.01	/workspace/coverage/default/56.chip_sw_all_escalation_resets.2410091318
95.20	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.39	0.01	/workspace/coverage/default/6.chip_sw_all_escalation_resets.1706398501
95.20	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.40	0.01	/workspace/coverage/default/60.chip_sw_all_escalation_resets.799456800
95.20	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.41	0.01	/workspace/coverage/default/63.chip_sw_all_escalation_resets.3325321178
95.21	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.42	0.01	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1839004318
95.21	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.44	0.01	/workspace/coverage/default/66.chip_sw_all_escalation_resets.1159343040
95.21	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.45	0.01	/workspace/coverage/default/7.chip_sw_all_escalation_resets.32999886
95.21	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.46	0.01	/workspace/coverage/default/70.chip_sw_all_escalation_resets.3509906873
95.21	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.47	0.01	/workspace/coverage/default/74.chip_sw_all_escalation_resets.1302848154
95.22	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.48	0.01	/workspace/coverage/default/75.chip_sw_all_escalation_resets.861500641
95.22	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2220976048
95.22	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.61819090
95.22	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/82.chip_sw_all_escalation_resets.1491359011
95.22	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.956148464
95.23	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.54	0.01	/workspace/coverage/default/83.chip_sw_all_escalation_resets.591480204
95.23	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.55	0.01	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1184461018
95.23	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.57	0.01	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2142985657
95.23	0.01	94.72	0.00	93.51	0.00	91.74	0.00			94.44	0.00	97.41	0.00	99.58	0.01	/workspace/coverage/default/95.chip_sw_all_escalation_resets.3187963353
95.23	0.01	94.72	0.00	93.52	0.01	91.74	0.00			94.44	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.2949820789
95.23	0.01	94.72	0.00	93.53	0.01	91.74	0.00			94.44	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/15.chip_tl_errors.3147071241
95.24	0.01	94.72	0.00	93.54	0.01	91.74	0.00			94.44	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/40.xbar_random_large_delays.1405094026
95.24	0.01	94.72	0.00	93.55	0.01	91.74	0.00			94.44	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.178249715
95.24	0.01	94.72	0.00	93.56	0.01	91.74	0.00			94.44	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3998818767
95.24	0.01	94.72	0.01	93.56	0.01	91.74	0.00			94.44	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1932340268
95.24	0.01	94.72	0.00	93.56	0.00	91.75	0.01			94.44	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.925504286
95.25	0.01	94.73	0.01	93.56	0.00	91.76	0.01			94.44	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/52.chip_sw_all_escalation_resets.2278953722
95.25	0.01	94.73	0.00	93.56	0.00	91.77	0.01			94.44	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3746095958
95.25	0.01	94.73	0.00	93.57	0.01	91.77	0.01			94.44	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.502059223
95.25	0.01	94.73	0.00	93.57	0.00	91.77	0.00			94.45	0.01	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1227762901
95.25	0.01	94.73	0.00	93.57	0.00	91.77	0.00			94.46	0.01	97.41	0.00	99.58	0.00	/workspace/coverage/default/3.chip_tap_straps_dev.2571417543
95.25	0.01	94.73	0.00	93.57	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.4285304194
95.25	0.01	94.73	0.00	93.58	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/12.xbar_stress_all.3358473309
95.25	0.01	94.73	0.00	93.59	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/14.xbar_stress_all.3722678119
95.26	0.01	94.73	0.00	93.59	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.1550133640
95.26	0.01	94.73	0.00	93.60	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.1298925275
95.26	0.01	94.73	0.00	93.61	0.01	91.77	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.576074585
95.26	0.01	94.73	0.01	93.61	0.00	91.77	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.85636251
95.26	0.01	94.73	0.00	93.61	0.00	91.78	0.01			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1592184591
95.26	0.01	94.73	0.00	93.61	0.00	91.78	0.01			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3357561356
95.26	0.01	94.73	0.00	93.61	0.00	91.79	0.01			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3836928450
95.26	0.01	94.73	0.00	93.61	0.00	91.79	0.01			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.420202962
95.26	0.01	94.73	0.00	93.61	0.00	91.80	0.01			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2336058933
95.26	0.01	94.73	0.00	93.61	0.01	91.80	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2593209638
95.26	0.01	94.73	0.00	93.62	0.01	91.80	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.322171505
95.27	0.01	94.73	0.00	93.62	0.01	91.80	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.561243545
95.27	0.01	94.73	0.00	93.62	0.01	91.80	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.2403925639
95.27	0.01	94.73	0.00	93.63	0.01	91.80	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.3250033244
95.27	0.01	94.73	0.00	93.63	0.01	91.80	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3904156562
95.27	0.01	94.73	0.00	93.63	0.01	91.80	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.466248332
95.27	0.01	94.73	0.00	93.64	0.01	91.80	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.4209095497
95.27	0.01	94.73	0.00	93.64	0.01	91.80	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_gpio.3055459656
95.27	0.01	94.73	0.00	93.64	0.01	91.80	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2629165411
95.27	0.01	94.73	0.00	93.65	0.01	91.80	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_spi_device_tpm.582223278
95.27	0.01	94.73	0.00	93.65	0.01	91.80	0.00			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_aon_timer_irq.517931584
95.27	0.01	94.73	0.00	93.65	0.00	91.80	0.01			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2317051093
95.27	0.01	94.73	0.00	93.65	0.00	91.80	0.01			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.362864892
95.27	0.01	94.73	0.00	93.65	0.00	91.80	0.01			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1467788552
95.27	0.01	94.73	0.00	93.65	0.00	91.81	0.01			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3548002757
95.27	0.01	94.73	0.00	93.65	0.00	91.81	0.01			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3769172165
95.27	0.01	94.73	0.00	93.65	0.00	91.81	0.01			94.46	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1135345746

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1889798864
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2171167310
/workspace/coverage/cover_reg_top/0.chip_csr_rw.286908245
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1189595204
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.4256435874
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2248011224
/workspace/coverage/cover_reg_top/0.chip_tl_errors.2107817671
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2814498407
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.105246627
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.996218295
/workspace/coverage/cover_reg_top/0.xbar_error_random.1310827859
/workspace/coverage/cover_reg_top/0.xbar_random.766194878
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3698838623
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.817579843
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2175809656
/workspace/coverage/cover_reg_top/0.xbar_same_source.2932534013
/workspace/coverage/cover_reg_top/0.xbar_smoke.4150639784
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.578585129
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1062277198
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3843712209
/workspace/coverage/cover_reg_top/0.xbar_stress_all.687980370
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3507338880
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3996903114
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1725447947
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.974990058
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3310573634
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2563939759
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1717649053
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3297563588
/workspace/coverage/cover_reg_top/1.chip_tl_errors.3502238437
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.4247313696
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1447448600
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3264527559
/workspace/coverage/cover_reg_top/1.xbar_error_random.2897478128
/workspace/coverage/cover_reg_top/1.xbar_random.2751562152
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2137707852
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.655849515
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1986739967
/workspace/coverage/cover_reg_top/1.xbar_same_source.3893422858
/workspace/coverage/cover_reg_top/1.xbar_smoke.3011127058
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1567953610
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.391093146
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.4208286990
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1844912301
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.162999719
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1904398164
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.65784871
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.624362522
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2248547091
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1743455378
/workspace/coverage/cover_reg_top/10.chip_tl_errors.926496918
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1660726372
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.4230534078
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3648226549
/workspace/coverage/cover_reg_top/10.xbar_error_random.2830696724
/workspace/coverage/cover_reg_top/10.xbar_random.4179846189
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.272273084
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2981102115
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.353577467
/workspace/coverage/cover_reg_top/10.xbar_same_source.1781237684
/workspace/coverage/cover_reg_top/10.xbar_smoke.1226122976
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3676008849
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3278618100
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3593007473
/workspace/coverage/cover_reg_top/10.xbar_stress_all.765334983
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.323656211
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3974068989
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.4051795048
/workspace/coverage/cover_reg_top/11.chip_csr_rw.4084620716
/workspace/coverage/cover_reg_top/11.chip_tl_errors.284566585
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3637074775
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1655660575
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.644186410
/workspace/coverage/cover_reg_top/11.xbar_error_random.3252639224
/workspace/coverage/cover_reg_top/11.xbar_random.1453489013
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.166237501
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3289649554
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3653263435
/workspace/coverage/cover_reg_top/11.xbar_same_source.2644133027
/workspace/coverage/cover_reg_top/11.xbar_smoke.361617328
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2422953226
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1879298091
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4024774711
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2105406885
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2612668982
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1839338741
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1510123446
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3018362576
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2105915635
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3565899380
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3304567418
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3815334677
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1553494158
/workspace/coverage/cover_reg_top/12.xbar_error_random.139667446
/workspace/coverage/cover_reg_top/12.xbar_random.483792654
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2804701408
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.310927891
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.124931398
/workspace/coverage/cover_reg_top/12.xbar_same_source.1485687407
/workspace/coverage/cover_reg_top/12.xbar_smoke.670142124
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2238929792
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1176935382
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1489317386
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1769763863
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2091775307
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1328204162
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2489297138
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2936764592
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3364683600
/workspace/coverage/cover_reg_top/13.chip_tl_errors.1393975801
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2151524664
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.683335721
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2502513390
/workspace/coverage/cover_reg_top/13.xbar_error_random.2776940327
/workspace/coverage/cover_reg_top/13.xbar_random.4111491964
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2049410153
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3948295467
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3535838511
/workspace/coverage/cover_reg_top/13.xbar_same_source.610075645
/workspace/coverage/cover_reg_top/13.xbar_smoke.1131469187
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3149973013
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.77291306
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.32498708
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.612446124
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.4019343868
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3183390663
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/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1987922782
/workspace/coverage/default/4.chip_tap_straps_dev.3777265177
/workspace/coverage/default/4.chip_tap_straps_prod.4281675152
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3131468164
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1280832131
/workspace/coverage/default/41.chip_sw_all_escalation_resets.947087607
/workspace/coverage/default/42.chip_sw_all_escalation_resets.77601485
/workspace/coverage/default/43.chip_sw_all_escalation_resets.162259986
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.958632931
/workspace/coverage/default/44.chip_sw_all_escalation_resets.745723469
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2804880052
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.874235831
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2016607234
/workspace/coverage/default/48.chip_sw_all_escalation_resets.835652222
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2238605309
/workspace/coverage/default/49.chip_sw_all_escalation_resets.29514910
/workspace/coverage/default/5.chip_sw_all_escalation_resets.999084920
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.4138604911
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1608703328
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.416406359
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1596704138
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1487383882
/workspace/coverage/default/51.chip_sw_all_escalation_resets.61150651
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.4283496693
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3617769657
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1477593871
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.4270117989
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1503069383
/workspace/coverage/default/58.chip_sw_all_escalation_resets.813856760
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1612837747
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.624642003
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3532989608
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4077296702
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4163853922
/workspace/coverage/default/61.chip_sw_all_escalation_resets.375000730
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2622909359
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2496957176
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.331216144
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3959886633
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1777248560
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2980296865
/workspace/coverage/default/65.chip_sw_all_escalation_resets.548635323
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.676831956
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3153509091
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.894910953
/workspace/coverage/default/68.chip_sw_all_escalation_resets.1300968896
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2303802127
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3586184586
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1695501427
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3774786763
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3019226180
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1512605558
/workspace/coverage/default/71.chip_sw_all_escalation_resets.1007041117
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2186178903
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1609842386
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2641865504
/workspace/coverage/default/73.chip_sw_all_escalation_resets.4050158501
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4258294752
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3626775279
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4018407714
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1402218052
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.793505807
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2948541834
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2626547579
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2959182226
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3242561626
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3798660613
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2367684397
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3773929248
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1405036519
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1663121566
/workspace/coverage/default/81.chip_sw_all_escalation_resets.902570413
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3646290389
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3181781257
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.860094906
/workspace/coverage/default/85.chip_sw_all_escalation_resets.807356901
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.84507021
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3255637349
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3392890192
/workspace/coverage/default/87.chip_sw_all_escalation_resets.564557584
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3276336701
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3129949206
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3140326182
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3783768321
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3641231876
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2361851693
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3765242324
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1720519331
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2803751018
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1075950154
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1407551357
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3569808005
/workspace/coverage/default/98.chip_sw_all_escalation_resets.720291515
/workspace/coverage/default/99.chip_sw_all_escalation_resets.275222906
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3219509846
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3529844471
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2419360816
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.4147739081
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2606616335
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1597389820
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2689315356
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1552525248

---

Total test records in report: 2801

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.797227654			May 23 04:13:07 PM PDT 24	May 23 04:28:51 PM PDT 24	8642711600 ps
T2	/workspace/coverage/default/0.chip_sw_spi_device_tpm.582223278			May 23 04:01:54 PM PDT 24	May 23 04:08:01 PM PDT 24	3663603574 ps
T3	/workspace/coverage/default/1.chip_sw_rv_timer_irq.2830634651			May 23 04:00:16 PM PDT 24	May 23 04:03:09 PM PDT 24	3345397316 ps
T32	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1637093159			May 23 04:00:35 PM PDT 24	May 23 04:11:10 PM PDT 24	5341443136 ps
T93	/workspace/coverage/default/0.chip_sw_otbn_randomness.1573110144			May 23 04:02:30 PM PDT 24	May 23 04:19:58 PM PDT 24	5777546318 ps
T97	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.219378043			May 23 04:18:42 PM PDT 24	May 23 04:24:49 PM PDT 24	4343005360 ps
T91	/workspace/coverage/default/0.chip_sw_edn_sw_mode.638246850			May 23 04:00:54 PM PDT 24	May 23 04:24:28 PM PDT 24	6520148120 ps
T4	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3561387677			May 23 04:06:02 PM PDT 24	May 23 04:14:15 PM PDT 24	8920088160 ps
T16	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2873554504			May 23 04:02:05 PM PDT 24	May 23 04:27:57 PM PDT 24	19148998056 ps
T45	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3353211170			May 23 04:14:14 PM PDT 24	May 23 04:20:00 PM PDT 24	3981209458 ps
T122	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1876788460			May 23 04:23:07 PM PDT 24	May 23 04:26:13 PM PDT 24	2007626552 ps
T70	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1683402502			May 23 04:10:10 PM PDT 24	May 23 04:14:35 PM PDT 24	2723668845 ps
T86	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3534992305			May 23 04:04:46 PM PDT 24	May 23 04:11:45 PM PDT 24	7059200840 ps
T76	/workspace/coverage/default/13.chip_sw_all_escalation_resets.862476878			May 23 04:19:50 PM PDT 24	May 23 04:30:43 PM PDT 24	4218184472 ps
T77	/workspace/coverage/default/95.chip_sw_all_escalation_resets.3187963353			May 23 04:22:07 PM PDT 24	May 23 04:34:08 PM PDT 24	5165412010 ps
T123	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.331216144			May 23 04:22:58 PM PDT 24	May 23 04:30:48 PM PDT 24	3406515522 ps
T46	/workspace/coverage/default/1.chip_tap_straps_dev.4238497708			May 23 04:03:13 PM PDT 24	May 23 04:06:33 PM PDT 24	2876186089 ps
T13	/workspace/coverage/default/1.chip_sw_gpio.259875779			May 23 04:04:46 PM PDT 24	May 23 04:11:50 PM PDT 24	3768053506 ps
T194	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2172844012			May 23 04:18:36 PM PDT 24	May 23 04:28:23 PM PDT 24	4351356528 ps
T149	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1624316524			May 23 04:16:12 PM PDT 24	May 23 04:24:30 PM PDT 24	5147650738 ps
T346	/workspace/coverage/default/0.chip_sw_csrng_smoketest.377935141			May 23 04:01:13 PM PDT 24	May 23 04:06:45 PM PDT 24	3290057880 ps
T87	/workspace/coverage/default/39.chip_sw_all_escalation_resets.746350166			May 23 04:19:37 PM PDT 24	May 23 04:31:11 PM PDT 24	4351562194 ps
T5	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2559296032			May 23 04:07:26 PM PDT 24	May 23 05:04:04 PM PDT 24	14061635073 ps
T200	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.502815944			May 23 04:17:32 PM PDT 24	May 23 04:41:57 PM PDT 24	7534155056 ps
T6	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3013893779			May 23 04:12:19 PM PDT 24	May 23 05:42:23 PM PDT 24	22137346555 ps
T41	/workspace/coverage/default/2.rom_e2e_smoke.3856444739			May 23 04:20:00 PM PDT 24	May 23 05:11:16 PM PDT 24	14658761074 ps
T205	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.4205425917			May 23 04:06:25 PM PDT 24	May 23 05:08:11 PM PDT 24	14254843300 ps
T63	/workspace/coverage/default/2.chip_sw_alert_test.2149314313			May 23 04:08:39 PM PDT 24	May 23 04:14:17 PM PDT 24	3243175872 ps
T347	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4018407714			May 23 04:22:41 PM PDT 24	May 23 04:29:49 PM PDT 24	3247713690 ps
T172	/workspace/coverage/default/46.chip_sw_all_escalation_resets.1674114023			May 23 04:21:48 PM PDT 24	May 23 04:30:04 PM PDT 24	4858890316 ps
T375	/workspace/coverage/default/1.chip_sw_hmac_smoketest.1965581087			May 23 04:05:28 PM PDT 24	May 23 04:10:29 PM PDT 24	3163277160 ps
T85	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3796230114			May 23 04:02:29 PM PDT 24	May 23 04:30:08 PM PDT 24	8491759784 ps
T42	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1101936988			May 23 04:03:34 PM PDT 24	May 23 04:14:32 PM PDT 24	6018126774 ps
T124	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.984843716			May 23 04:03:14 PM PDT 24	May 23 05:02:03 PM PDT 24	17018446100 ps
T204	/workspace/coverage/default/62.chip_sw_all_escalation_resets.2496957176			May 23 04:24:44 PM PDT 24	May 23 04:37:35 PM PDT 24	4551817880 ps
T233	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1629697674			May 23 04:02:44 PM PDT 24	May 23 04:22:04 PM PDT 24	8849203025 ps
T142	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.649217039			May 23 04:05:34 PM PDT 24	May 23 04:48:21 PM PDT 24	11897306441 ps
T639	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3657785284			May 23 04:21:49 PM PDT 24	May 23 04:29:45 PM PDT 24	3738555646 ps
T14	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1859129772			May 23 04:21:22 PM PDT 24	May 23 04:49:58 PM PDT 24	8707761242 ps
T127	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1256370717			May 23 04:06:47 PM PDT 24	May 23 04:10:43 PM PDT 24	2390944880 ps
T73	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3624618845			May 23 03:59:57 PM PDT 24	May 23 04:10:39 PM PDT 24	6208933006 ps
T138	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.150682223			May 23 04:00:52 PM PDT 24	May 23 04:09:15 PM PDT 24	18354977488 ps
T324	/workspace/coverage/default/54.chip_sw_all_escalation_resets.2747442509			May 23 04:21:23 PM PDT 24	May 23 04:32:35 PM PDT 24	5714042650 ps
T143	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1403851439			May 23 04:00:27 PM PDT 24	May 23 04:03:49 PM PDT 24	2910026649 ps
T234	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.163213620			May 23 04:01:38 PM PDT 24	May 23 04:19:58 PM PDT 24	8440853580 ps
T78	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1612773134			May 23 04:02:11 PM PDT 24	May 23 04:31:13 PM PDT 24	7893916096 ps
T43	/workspace/coverage/default/2.chip_tap_straps_testunlock0.1248950651			May 23 04:12:52 PM PDT 24	May 23 04:21:57 PM PDT 24	5386438291 ps
T104	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.624642003			May 23 04:22:18 PM PDT 24	May 23 04:28:39 PM PDT 24	3858108100 ps
T33	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.72616821			May 23 04:03:35 PM PDT 24	May 23 04:08:31 PM PDT 24	3207022568 ps
T113	/workspace/coverage/default/78.chip_sw_all_escalation_resets.120483457			May 23 04:22:31 PM PDT 24	May 23 04:31:26 PM PDT 24	4351789192 ps
T15	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2613719566			May 23 04:18:59 PM PDT 24	May 23 04:41:56 PM PDT 24	8751145032 ps
T114	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.4269958974			May 23 04:23:03 PM PDT 24	May 23 04:29:23 PM PDT 24	3762617080 ps
T115	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1320642423			May 23 04:02:58 PM PDT 24	May 23 04:12:57 PM PDT 24	5901807242 ps
T116	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2136503062			May 23 03:59:04 PM PDT 24	May 23 07:42:11 PM PDT 24	76827038228 ps
T117	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2980296865			May 23 04:21:46 PM PDT 24	May 23 04:28:41 PM PDT 24	3736682526 ps
T25	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2958829653			May 23 04:04:20 PM PDT 24	May 23 04:10:13 PM PDT 24	3341434462 ps
T118	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3392890192			May 23 04:25:09 PM PDT 24	May 23 04:30:34 PM PDT 24	3609328360 ps
T266	/workspace/coverage/default/7.chip_sw_all_escalation_resets.32999886			May 23 04:17:27 PM PDT 24	May 23 04:31:48 PM PDT 24	6453691220 ps
T150	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3846114897			May 23 04:03:36 PM PDT 24	May 23 04:11:10 PM PDT 24	5376679290 ps
T92	/workspace/coverage/default/3.chip_tap_straps_dev.2571417543			May 23 04:16:43 PM PDT 24	May 23 04:44:50 PM PDT 24	15143661515 ps
T267	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.4147263563			May 23 04:04:05 PM PDT 24	May 23 04:20:13 PM PDT 24	5066051414 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.252436163			May 23 03:59:05 PM PDT 24	May 23 04:07:52 PM PDT 24	3678336264 ps
T144	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1244400462			May 23 04:03:11 PM PDT 24	May 23 04:06:02 PM PDT 24	2459815652 ps
T383	/workspace/coverage/default/1.chip_sw_uart_smoketest.1018940783			May 23 04:06:50 PM PDT 24	May 23 04:09:45 PM PDT 24	3367315680 ps
T131	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.180701008			May 23 04:03:37 PM PDT 24	May 23 04:16:44 PM PDT 24	6444387112 ps
T374	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2241073373			May 23 04:19:49 PM PDT 24	May 23 05:13:20 PM PDT 24	15732279272 ps
T165	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.3631338525			May 23 04:03:50 PM PDT 24	May 23 07:11:08 PM PDT 24	64702209010 ps
T18	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2180293615			May 23 04:08:40 PM PDT 24	May 23 04:32:25 PM PDT 24	18279350400 ps
T694	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2353126239			May 23 04:03:30 PM PDT 24	May 23 04:23:01 PM PDT 24	7176193042 ps
T315	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1228871583			May 23 03:57:59 PM PDT 24	May 23 04:09:49 PM PDT 24	5847697900 ps
T218	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2198813421			May 23 04:07:39 PM PDT 24	May 23 04:18:27 PM PDT 24	5489244800 ps
T196	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.680063313			May 23 04:00:39 PM PDT 24	May 23 04:10:24 PM PDT 24	4079263072 ps
T100	/workspace/coverage/default/0.chip_tap_straps_dev.2906057211			May 23 03:59:24 PM PDT 24	May 23 04:21:36 PM PDT 24	11628861775 ps
T162	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3998818767			May 23 04:04:55 PM PDT 24	May 23 04:12:46 PM PDT 24	6025002568 ps
T132	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.610196086			May 23 04:14:39 PM PDT 24	May 23 04:24:57 PM PDT 24	4912683654 ps
T325	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.870191257			May 23 04:01:22 PM PDT 24	May 23 04:09:59 PM PDT 24	4463645586 ps
T362	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.656914041			May 23 04:14:19 PM PDT 24	May 23 04:28:21 PM PDT 24	7110995126 ps
T692	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1467657084			May 23 04:19:01 PM PDT 24	May 23 04:27:25 PM PDT 24	4247532152 ps
T842	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1207477283			May 23 04:04:11 PM PDT 24	May 23 04:11:01 PM PDT 24	6060631800 ps
T237	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2523990346			May 23 04:04:05 PM PDT 24	May 23 04:22:19 PM PDT 24	5382743144 ps
T843	/workspace/coverage/default/1.chip_sw_example_manufacturer.2582230728			May 23 04:08:46 PM PDT 24	May 23 04:12:16 PM PDT 24	2381699360 ps
T105	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2641865504			May 23 04:22:51 PM PDT 24	May 23 04:28:54 PM PDT 24	3623398192 ps
T197	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2214449594			May 23 04:03:15 PM PDT 24	May 23 04:14:59 PM PDT 24	5220453998 ps
T691	/workspace/coverage/default/59.chip_sw_all_escalation_resets.1612837747			May 23 04:20:19 PM PDT 24	May 23 04:30:28 PM PDT 24	4781549480 ps
T40	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.659430733			May 23 04:03:58 PM PDT 24	May 23 04:59:34 PM PDT 24	11079573578 ps
T844	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3401313122			May 23 04:16:25 PM PDT 24	May 23 04:20:35 PM PDT 24	3299594112 ps
T845	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2935844965			May 23 03:59:47 PM PDT 24	May 23 04:08:19 PM PDT 24	4881562260 ps
T171	/workspace/coverage/default/0.chip_tap_straps_prod.50512746			May 23 04:00:59 PM PDT 24	May 23 04:17:51 PM PDT 24	9017356378 ps
T163	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.4016942613			May 23 04:15:44 PM PDT 24	May 23 04:19:16 PM PDT 24	3044959710 ps
T249	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3909827960			May 23 04:14:44 PM PDT 24	May 23 04:23:53 PM PDT 24	3325811664 ps
T689	/workspace/coverage/default/49.chip_sw_all_escalation_resets.29514910			May 23 04:20:41 PM PDT 24	May 23 04:29:50 PM PDT 24	4071182364 ps
T235	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3289270876			May 23 04:00:11 PM PDT 24	May 23 04:28:03 PM PDT 24	11802592184 ps
T125	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3802873863			May 23 04:03:53 PM PDT 24	May 23 05:08:16 PM PDT 24	24952988944 ps
T846	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3759055618			May 23 04:00:37 PM PDT 24	May 23 04:08:00 PM PDT 24	3665445446 ps
T157	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1776492218			May 23 04:17:25 PM PDT 24	May 23 04:27:56 PM PDT 24	5208973450 ps
T317	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.703383459			May 23 04:02:17 PM PDT 24	May 23 04:13:23 PM PDT 24	18138188760 ps
T88	/workspace/coverage/default/1.chip_sw_flash_init.2792154745			May 23 04:06:00 PM PDT 24	May 23 04:41:33 PM PDT 24	17886347944 ps
T174	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3949588225			May 23 04:05:23 PM PDT 24	May 23 04:11:19 PM PDT 24	4154034200 ps
T353	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1211594710			May 23 04:14:33 PM PDT 24	May 23 05:51:14 PM PDT 24	22506512700 ps
T201	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3090901779			May 23 04:17:27 PM PDT 24	May 23 04:25:35 PM PDT 24	4267784458 ps
T173	/workspace/coverage/default/2.rom_keymgr_functest.2350366333			May 23 04:16:00 PM PDT 24	May 23 04:25:58 PM PDT 24	3723137560 ps
T657	/workspace/coverage/default/2.chip_sw_aes_idle.1683652847			May 23 04:06:00 PM PDT 24	May 23 04:09:00 PM PDT 24	2695288160 ps
T847	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1029987372			May 23 04:00:59 PM PDT 24	May 23 04:14:55 PM PDT 24	9278532500 ps
T848	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2155527323			May 23 04:13:51 PM PDT 24	May 23 04:32:31 PM PDT 24	7704951436 ps
T849	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2936228153			May 23 04:08:02 PM PDT 24	May 23 05:27:51 PM PDT 24	15770257456 ps
T202	/workspace/coverage/default/2.chip_sw_uart_tx_rx.303242995			May 23 04:02:10 PM PDT 24	May 23 04:15:20 PM PDT 24	4254155532 ps
T850	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2348227413			May 23 03:59:31 PM PDT 24	May 23 04:02:37 PM PDT 24	2862450120 ps
T134	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3342796003			May 23 04:05:54 PM PDT 24	May 23 04:08:59 PM PDT 24	2705915312 ps
T69	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1137125746			May 23 04:13:33 PM PDT 24	May 23 04:23:19 PM PDT 24	4716460898 ps
T75	/workspace/coverage/default/67.chip_sw_all_escalation_resets.3153509091			May 23 04:21:53 PM PDT 24	May 23 04:32:44 PM PDT 24	5900061482 ps
T81	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2382658422			May 23 03:59:03 PM PDT 24	May 23 04:11:22 PM PDT 24	3646357080 ps
T272	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4061419348			May 23 04:07:40 PM PDT 24	May 23 04:19:21 PM PDT 24	5284100194 ps
T273	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2608105085			May 23 04:04:18 PM PDT 24	May 23 04:10:32 PM PDT 24	3275670300 ps
T184	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.4043477811			May 23 04:07:10 PM PDT 24	May 23 07:17:22 PM PDT 24	64276441169 ps
T274	/workspace/coverage/default/2.chip_sival_flash_info_access.4082137725			May 23 04:07:41 PM PDT 24	May 23 04:12:19 PM PDT 24	2473225416 ps
T175	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2429655937			May 23 04:04:38 PM PDT 24	May 23 04:10:07 PM PDT 24	3279460362 ps
T275	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2197401188			May 23 04:07:05 PM PDT 24	May 23 07:33:29 PM PDT 24	77477546135 ps
T851	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.1316156363			May 23 04:01:39 PM PDT 24	May 23 04:20:29 PM PDT 24	7246647964 ps
T852	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.873841599			May 23 04:08:40 PM PDT 24	May 23 04:22:14 PM PDT 24	8953774074 ps
T148	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3746095958			May 23 03:59:49 PM PDT 24	May 23 04:05:57 PM PDT 24	6531500903 ps
T853	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3170213992			May 23 03:59:02 PM PDT 24	May 23 04:17:09 PM PDT 24	6528054100 ps
T126	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.657144935			May 23 04:03:15 PM PDT 24	May 23 05:09:30 PM PDT 24	19116607360 ps
T94	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1835241400			May 23 04:04:58 PM PDT 24	May 23 04:12:18 PM PDT 24	5204633160 ps
T60	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1955773589			May 23 04:04:51 PM PDT 24	May 23 04:21:40 PM PDT 24	7652215100 ps
T71	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.4107037679			May 23 04:00:28 PM PDT 24	May 23 04:05:17 PM PDT 24	2777638632 ps
T290	/workspace/coverage/default/0.chip_plic_all_irqs_0.3894903522			May 23 04:04:54 PM PDT 24	May 23 04:25:54 PM PDT 24	5492307956 ps
T854	/workspace/coverage/default/1.rom_e2e_smoke.3154086614			May 23 04:07:49 PM PDT 24	May 23 05:01:40 PM PDT 24	14253831204 ps
T624	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3836928450			May 23 04:05:04 PM PDT 24	May 23 05:07:08 PM PDT 24	24139217307 ps
T492	/workspace/coverage/default/91.chip_sw_all_escalation_resets.1720519331			May 23 04:25:44 PM PDT 24	May 23 04:35:33 PM PDT 24	4972898004 ps
T298	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.279540216			May 23 04:04:09 PM PDT 24	May 23 04:16:46 PM PDT 24	4821894250 ps
T250	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.624033919			May 23 04:03:57 PM PDT 24	May 23 05:03:38 PM PDT 24	13374601059 ps
T82	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2061120822			May 23 04:04:54 PM PDT 24	May 23 05:21:53 PM PDT 24	17718023160 ps
T354	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3769172165			May 23 04:04:50 PM PDT 24	May 23 05:35:36 PM PDT 24	22725520392 ps
T675	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2830908036			May 23 04:19:56 PM PDT 24	May 23 04:31:25 PM PDT 24	5022030040 ps
T855	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.1795599204			May 23 04:14:59 PM PDT 24	May 23 04:19:12 PM PDT 24	2581040240 ps
T35	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.791720339			May 23 04:11:20 PM PDT 24	May 23 04:17:19 PM PDT 24	5163584350 ps
T22	/workspace/coverage/default/0.chip_sw_usbdev_config_host.639193393			May 23 04:01:29 PM PDT 24	May 23 04:33:02 PM PDT 24	8043947288 ps
T66	/workspace/coverage/default/2.chip_tap_straps_prod.3987407958			May 23 04:13:08 PM PDT 24	May 23 04:15:43 PM PDT 24	2105607336 ps
T856	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3595499650			May 23 04:04:13 PM PDT 24	May 23 04:20:12 PM PDT 24	7443600088 ps
T49	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.51842972			May 23 04:07:29 PM PDT 24	May 23 04:12:02 PM PDT 24	2948125200 ps
T176	/workspace/coverage/default/0.chip_sw_kmac_entropy.3886035478			May 23 04:01:54 PM PDT 24	May 23 04:05:39 PM PDT 24	2772387960 ps
T395	/workspace/coverage/default/0.rom_e2e_asm_init_dev.4215090444			May 23 04:14:05 PM PDT 24	May 23 05:11:28 PM PDT 24	14458678222 ps
T396	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1625196477			May 23 04:05:25 PM PDT 24	May 23 04:47:05 PM PDT 24	26594062860 ps
T316	/workspace/coverage/default/32.chip_sw_all_escalation_resets.799567800			May 23 04:20:58 PM PDT 24	May 23 04:32:00 PM PDT 24	6089663384 ps
T397	/workspace/coverage/default/82.chip_sw_all_escalation_resets.1491359011			May 23 04:24:21 PM PDT 24	May 23 04:34:36 PM PDT 24	4823979668 ps
T369	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1994864394			May 23 04:04:20 PM PDT 24	May 23 04:13:05 PM PDT 24	5426834376 ps
T398	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2893656062			May 23 04:16:41 PM PDT 24	May 23 05:11:06 PM PDT 24	25291437886 ps
T399	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2436652404			May 23 04:00:07 PM PDT 24	May 23 04:03:58 PM PDT 24	2814346502 ps
T133	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1655770203			May 23 03:58:39 PM PDT 24	May 23 04:10:53 PM PDT 24	5109756550 ps
T857	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1888297838			May 23 04:06:15 PM PDT 24	May 23 04:10:20 PM PDT 24	2459320492 ps
T312	/workspace/coverage/default/0.chip_sival_flash_info_access.4161139894			May 23 03:59:17 PM PDT 24	May 23 04:05:19 PM PDT 24	3314156012 ps
T858	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1994436726			May 23 04:09:38 PM PDT 24	May 23 05:17:32 PM PDT 24	14350004470 ps
T89	/workspace/coverage/default/2.chip_sw_flash_init.98729220			May 23 04:02:12 PM PDT 24	May 23 04:39:49 PM PDT 24	20485222840 ps
T859	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.4089844520			May 23 04:01:31 PM PDT 24	May 23 04:18:10 PM PDT 24	5377026247 ps
T170	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3860309899			May 23 04:19:00 PM PDT 24	May 23 04:45:23 PM PDT 24	8492267216 ps
T860	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1685929546			May 23 04:04:00 PM PDT 24	May 23 04:09:54 PM PDT 24	3680571096 ps
T861	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1731029407			May 23 04:06:11 PM PDT 24	May 23 05:06:29 PM PDT 24	10880653704 ps
T658	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3906820677			May 23 04:03:09 PM PDT 24	May 23 04:06:51 PM PDT 24	2814610306 ps
T862	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1645860622			May 23 04:00:42 PM PDT 24	May 23 04:07:56 PM PDT 24	5603912908 ps
T151	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3222374171			May 23 04:05:38 PM PDT 24	May 23 04:24:21 PM PDT 24	8731770784 ps
T770	/workspace/coverage/default/81.chip_sw_all_escalation_resets.902570413			May 23 04:22:51 PM PDT 24	May 23 04:35:19 PM PDT 24	5602293192 ps
T319	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2756945468			May 23 04:01:23 PM PDT 24	May 23 04:05:10 PM PDT 24	2344349983 ps
T190	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.259435498			May 23 04:04:38 PM PDT 24	May 23 04:08:44 PM PDT 24	2249644891 ps
T863	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.960038343			May 23 03:59:23 PM PDT 24	May 23 04:09:59 PM PDT 24	3609235020 ps
T179	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1800004569			May 23 04:01:41 PM PDT 24	May 23 04:19:39 PM PDT 24	8237261182 ps
T864	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1562409936			May 23 04:04:10 PM PDT 24	May 23 04:08:09 PM PDT 24	2770593270 ps
T145	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.580953922			May 23 04:03:11 PM PDT 24	May 23 04:25:58 PM PDT 24	8870708885 ps
T292	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3774786763			May 23 04:21:37 PM PDT 24	May 23 04:43:24 PM PDT 24	8097495350 ps
T865	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.834058922			May 23 04:03:33 PM PDT 24	May 23 04:20:59 PM PDT 24	6035461872 ps
T678	/workspace/coverage/default/84.chip_sw_all_escalation_resets.3181781257			May 23 04:22:25 PM PDT 24	May 23 04:32:47 PM PDT 24	5555664248 ps
T291	/workspace/coverage/default/0.chip_plic_all_irqs_20.2217770736			May 23 04:07:07 PM PDT 24	May 23 04:21:28 PM PDT 24	4421450824 ps
T866	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3584614596			May 23 04:25:27 PM PDT 24	May 23 05:15:36 PM PDT 24	14038820700 ps
T867	/workspace/coverage/default/1.chip_sw_aes_idle.3588887690			May 23 04:03:42 PM PDT 24	May 23 04:07:21 PM PDT 24	3369515224 ps
T376	/workspace/coverage/default/1.chip_sw_kmac_app_rom.931563901			May 23 04:03:12 PM PDT 24	May 23 04:05:43 PM PDT 24	2704584628 ps
T677	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1839004318			May 23 04:21:10 PM PDT 24	May 23 04:29:17 PM PDT 24	3840919512 ps
T868	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2796363078			May 23 04:12:40 PM PDT 24	May 23 05:12:53 PM PDT 24	14152211196 ps
T23	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.394897214			May 23 03:59:46 PM PDT 24	May 23 05:55:08 PM PDT 24	31538995680 ps
T24	/workspace/coverage/default/0.chip_sw_usbdev_dpi.3810629009			May 23 04:00:45 PM PDT 24	May 23 04:47:57 PM PDT 24	11503662904 ps
T869	/workspace/coverage/default/2.chip_sw_example_flash.661132149			May 23 04:07:14 PM PDT 24	May 23 04:11:47 PM PDT 24	2614694264 ps
T44	/workspace/coverage/default/1.chip_jtag_mem_access.4022486305			May 23 03:49:15 PM PDT 24	May 23 04:12:40 PM PDT 24	13564433064 ps
T98	/workspace/coverage/default/1.chip_tap_straps_testunlock0.1143702235			May 23 04:01:52 PM PDT 24	May 23 04:08:37 PM PDT 24	4143247722 ps
T90	/workspace/coverage/default/0.chip_sw_flash_init.2464338865			May 23 03:57:31 PM PDT 24	May 23 04:39:34 PM PDT 24	26317233390 ps
T358	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2714100500			May 23 04:05:24 PM PDT 24	May 23 04:08:34 PM PDT 24	2677050900 ps
T303	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3925632939			May 23 04:02:23 PM PDT 24	May 23 04:15:54 PM PDT 24	4280631736 ps
T260	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.636234431			May 23 04:05:01 PM PDT 24	May 23 04:13:25 PM PDT 24	3503470238 ps
T696	/workspace/coverage/default/1.chip_sw_otbn_smoketest.2245971209			May 23 04:07:26 PM PDT 24	May 23 04:35:18 PM PDT 24	7561273130 ps
T293	/workspace/coverage/default/1.chip_plic_all_irqs_0.1349282527			May 23 04:02:31 PM PDT 24	May 23 04:22:49 PM PDT 24	6367693888 ps
T47	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1596194717			May 23 04:04:26 PM PDT 24	May 23 04:12:25 PM PDT 24	4956115200 ps
T870	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.498478329			May 23 04:02:46 PM PDT 24	May 23 04:09:27 PM PDT 24	2811556620 ps
T199	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3376098062			May 23 04:03:15 PM PDT 24	May 23 04:14:34 PM PDT 24	4463427640 ps
T711	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.337850719			May 23 04:21:33 PM PDT 24	May 23 04:29:23 PM PDT 24	3821423670 ps
T660	/workspace/coverage/default/2.chip_sw_hmac_smoketest.3109868886			May 23 04:17:25 PM PDT 24	May 23 04:23:03 PM PDT 24	2899498326 ps
T871	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.601079810			May 23 04:21:12 PM PDT 24	May 23 04:28:54 PM PDT 24	6196952472 ps
T489	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.4017010314			May 23 04:02:44 PM PDT 24	May 23 04:17:07 PM PDT 24	4373845518 ps
T685	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3216744129			May 23 04:22:25 PM PDT 24	May 23 04:27:54 PM PDT 24	3446182510 ps
T872	/workspace/coverage/default/2.rom_e2e_asm_init_dev.943259089			May 23 04:19:56 PM PDT 24	May 23 05:14:04 PM PDT 24	14174079284 ps
T61	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2014454578			May 23 03:58:11 PM PDT 24	May 23 04:10:08 PM PDT 24	7579874925 ps
T873	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1735355259			May 23 04:02:50 PM PDT 24	May 23 04:10:41 PM PDT 24	3817369204 ps
T206	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2666937944			May 23 04:03:44 PM PDT 24	May 23 05:01:00 PM PDT 24	15126977472 ps
T874	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2823067944			May 23 04:07:43 PM PDT 24	May 23 04:12:16 PM PDT 24	2204866160 ps
T875	/workspace/coverage/default/2.chip_sw_aes_enc.3735257850			May 23 04:05:35 PM PDT 24	May 23 04:08:58 PM PDT 24	2766083338 ps
T102	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.4214530463			May 23 04:08:00 PM PDT 24	May 23 04:16:51 PM PDT 24	5031745624 ps
T876	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1605036519			May 23 04:09:42 PM PDT 24	May 23 04:13:37 PM PDT 24	2566981752 ps
T152	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.381957784			May 23 04:04:35 PM PDT 24	May 23 04:14:21 PM PDT 24	5874003264 ps
T877	/workspace/coverage/default/0.chip_sw_otbn_smoketest.2638108970			May 23 04:02:01 PM PDT 24	May 23 04:46:46 PM PDT 24	11752998510 ps
T223	/workspace/coverage/default/18.chip_sw_all_escalation_resets.643600518			May 23 04:23:10 PM PDT 24	May 23 04:33:56 PM PDT 24	4556650156 ps
T177	/workspace/coverage/default/2.chip_sw_kmac_smoketest.855198619			May 23 04:15:55 PM PDT 24	May 23 04:20:24 PM PDT 24	3277787672 ps
T164	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1507324352			May 23 04:05:43 PM PDT 24	May 23 04:09:22 PM PDT 24	3193859253 ps
T135	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1445056376			May 23 04:11:14 PM PDT 24	May 23 04:23:47 PM PDT 24	8693542670 ps
T878	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3125179498			May 23 04:08:16 PM PDT 24	May 23 04:27:44 PM PDT 24	4918393397 ps
T231	/workspace/coverage/default/0.chip_sw_rv_timer_irq.864801832			May 23 03:58:57 PM PDT 24	May 23 04:03:11 PM PDT 24	2598400512 ps
T628	/workspace/coverage/default/1.chip_sw_aes_masking_off.537539427			May 23 04:00:57 PM PDT 24	May 23 04:05:45 PM PDT 24	2637006332 ps
T749	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3959886633			May 23 04:23:45 PM PDT 24	May 23 04:31:45 PM PDT 24	3770858308 ps
T198	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2744184262			May 23 04:05:09 PM PDT 24	May 23 04:28:22 PM PDT 24	8795160080 ps
T768	/workspace/coverage/default/99.chip_sw_all_escalation_resets.275222906			May 23 04:24:28 PM PDT 24	May 23 04:35:26 PM PDT 24	4518117592 ps
T688	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1726861581			May 23 04:02:29 PM PDT 24	May 23 04:11:00 PM PDT 24	4420753736 ps
T295	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1531762695			May 23 04:01:38 PM PDT 24	May 23 04:12:14 PM PDT 24	4603023816 ps
T251	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2169330676			May 23 04:19:25 PM PDT 24	May 23 05:28:47 PM PDT 24	14048397400 ps
T19	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2334935564			May 23 04:04:32 PM PDT 24	May 23 04:57:34 PM PDT 24	20023591346 ps
T107	/workspace/coverage/default/3.chip_sw_all_escalation_resets.142697273			May 23 04:18:16 PM PDT 24	May 23 04:30:25 PM PDT 24	5964173024 ps
T108	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3685444957			May 23 04:18:21 PM PDT 24	May 23 04:28:28 PM PDT 24	5678669714 ps
T178	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3357561356			May 23 04:00:43 PM PDT 24	May 23 04:24:27 PM PDT 24	6700023712 ps
T232	/workspace/coverage/default/2.chip_sw_rv_timer_irq.582713866			May 23 04:09:06 PM PDT 24	May 23 04:12:36 PM PDT 24	3006697200 ps
T345	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.787948197			May 23 04:00:12 PM PDT 24	May 23 07:13:15 PM PDT 24	63174668502 ps
T684	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1477593871			May 23 04:20:47 PM PDT 24	May 23 04:28:40 PM PDT 24	3522191288 ps
T879	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2164191951			May 23 04:01:11 PM PDT 24	May 23 04:09:54 PM PDT 24	7515881536 ps
T880	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2051150899			May 23 04:07:15 PM PDT 24	May 23 04:10:53 PM PDT 24	2215227024 ps
T109	/workspace/coverage/default/23.chip_sw_all_escalation_resets.2242342757			May 23 04:21:34 PM PDT 24	May 23 04:34:50 PM PDT 24	6357446696 ps
T881	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2544498511			May 23 04:22:22 PM PDT 24	May 23 04:31:44 PM PDT 24	4428970754 ps
T139	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.925504286			May 23 04:14:49 PM PDT 24	May 23 04:57:22 PM PDT 24	19103130562 ps
T146	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3675392687			May 23 03:59:19 PM PDT 24	May 23 04:09:11 PM PDT 24	3906809400 ps
T882	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1542703739			May 23 04:02:01 PM PDT 24	May 23 04:09:19 PM PDT 24	3152521614 ps
T883	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.4201512144			May 23 04:10:01 PM PDT 24	May 23 04:17:12 PM PDT 24	5118304826 ps
T641	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196705433			May 23 04:20:12 PM PDT 24	May 23 04:27:07 PM PDT 24	4039377040 ps
T192	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2819087559			May 23 04:01:57 PM PDT 24	May 23 04:13:32 PM PDT 24	4067636994 ps
T26	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3281288538			May 23 04:06:36 PM PDT 24	May 23 04:12:16 PM PDT 24	4611191680 ps
T219	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2450539284			May 23 04:03:35 PM PDT 24	May 23 04:19:22 PM PDT 24	6453154696 ps
T244	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2110072999			May 23 04:06:04 PM PDT 24	May 23 05:04:28 PM PDT 24	36033238280 ps
T245	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2360120159			May 23 04:00:10 PM PDT 24	May 23 04:46:03 PM PDT 24	25018350252 ps
T228	/workspace/coverage/default/1.chip_sw_plic_sw_irq.3943350627			May 23 04:07:39 PM PDT 24	May 23 04:13:30 PM PDT 24	2436594056 ps
T159	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3067498142			May 23 04:03:04 PM PDT 24	May 23 04:12:28 PM PDT 24	5031368940 ps
T246	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3528231004			May 23 04:05:27 PM PDT 24	May 23 05:09:00 PM PDT 24	14647451294 ps
T247	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1894720570			May 23 04:00:53 PM PDT 24	May 23 04:14:37 PM PDT 24	4878760012 ps
T52	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4258920901			May 23 04:07:42 PM PDT 24	May 23 04:40:32 PM PDT 24	22050525368 ps
T180	/workspace/coverage/default/1.chip_sw_kmac_entropy.2302041731			May 23 04:00:27 PM PDT 24	May 23 04:05:51 PM PDT 24	3166657896 ps
T248	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.666991711			May 23 04:05:14 PM PDT 24	May 23 05:29:53 PM PDT 24	17827071400 ps
T884	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3540248918			May 23 04:02:41 PM PDT 24	May 23 04:07:02 PM PDT 24	2770240280 ps
T67	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2724792344			May 23 04:16:47 PM PDT 24	May 23 04:24:31 PM PDT 24	5214204333 ps
T261	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3868726764			May 23 04:14:37 PM PDT 24	May 23 04:23:36 PM PDT 24	4738553258 ps
T669	/workspace/coverage/default/96.chip_sw_all_escalation_resets.1407551357			May 23 04:22:15 PM PDT 24	May 23 04:35:05 PM PDT 24	5971009560 ps